L 1 "..\user\src\swj.c" N#include "stm32f10x.h" L 1 "..\..\template\Libraries\CMSIS\stm32f10x.h" 1 N/** N ****************************************************************************** N * @file stm32f10x.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. N * This file contains all the peripheral register's definitions, bits N * definitions and memory mapping for STM32F10x Connectivity line, N * High density, High density value line, Medium density, N * Medium density Value line, Low density, Low density Value line N * and XL-density devices. N * N * The file is the unique include file that the application programmer N * is using in the C source code, usually in main.c. This file contains: N * - Configuration section that allows to select: N * - The device used in the target application N * - To use or not the peripheral抯 drivers in application code(i.e. N * code will be based on direct access to peripheral抯 registers N * rather than drivers API), this option is controlled by N * "#define USE_STDPERIPH_DRIVER" N * - To change few application-specific parameters such as the HSE N * crystal frequency N * - Data structures and the address mapping for all peripherals N * - Peripheral's registers declarations and bits definition N * - Macros to access peripheral抯 registers hardware N * N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/** @addtogroup CMSIS N * @{ N */ N N/** @addtogroup stm32f10x N * @{ N */ N N#ifndef __STM32F10x_H N#define __STM32F10x_H N N#ifdef __cplusplus S extern "C" { N#endif N N/** @addtogroup Library_configuration_section N * @{ N */ N N/* Uncomment the line below according to the target STM32 device used in your N application N */ N N#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) X#if !0L && !0L && !1L && !0L && !0L && !0L && !0L && !0L S /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ S /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ S /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ S /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ S /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ S /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ S /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ S /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ N#endif N/* Tip: To avoid modifying this file each time you need to switch between these N devices, you can define the device in your toolchain compiler preprocessor. N N - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers N where the Flash memory density ranges between 16 and 32 Kbytes. N - Low-density value line devices are STM32F100xx microcontrollers where the Flash N memory density ranges between 16 and 32 Kbytes. N - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers N where the Flash memory density ranges between 64 and 128 Kbytes. N - Medium-density value line devices are STM32F100xx microcontrollers where the N Flash memory density ranges between 64 and 128 Kbytes. N - High-density devices are STM32F101xx and STM32F103xx microcontrollers where N the Flash memory density ranges between 256 and 512 Kbytes. N - High-density value line devices are STM32F100xx microcontrollers where the N Flash memory density ranges between 256 and 512 Kbytes. N - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where N the Flash memory density ranges between 512 and 1024 Kbytes. N - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. N */ N N#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) X#if !0L && !0L && !1L && !0L && !0L && !0L && !0L && !0L S #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" N#endif N N#if !defined USE_STDPERIPH_DRIVER X#if !1L S/** S * @brief Comment the line below if you will not use the peripherals drivers. S In this case, these drivers will not be included and the application code will S be based on direct access to peripherals registers S */ S /*#define USE_STDPERIPH_DRIVER*/ N#endif N N/** N * @brief In the following line adjust the value of External High Speed oscillator (HSE) N used in your application N N Tip: To avoid modifying this file each time you need to use different HSE, you N can define the HSE value in your toolchain compiler preprocessor. N */ N#if !defined HSE_VALUE X#if !0L N #ifdef STM32F10X_CL S #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ N #else N #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ N #endif /* STM32F10X_CL */ N#endif /* HSE_VALUE */ N N N/** N * @brief In the following line adjust the External High Speed oscillator (HSE) Startup N Timeout value N */ N#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ N N#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ N N/** N * @brief STM32F10x Standard Peripheral Library version number N */ N#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ N#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ N#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ N#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ N#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ N |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ N |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ N |(__STM32F10X_STDPERIPH_VERSION_RC)) X#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24) |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16) |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8) |(__STM32F10X_STDPERIPH_VERSION_RC)) N N/** N * @} N */ N N/** @addtogroup Configuration_section_for_CMSIS N * @{ N */ N N/** N * @brief Configuration of the Cortex-M3 Processor and Core Peripherals N */ N#ifdef STM32F10X_XL S #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ N#else N #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ N#endif /* STM32F10X_XL */ N#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ N#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ N N/** N * @brief STM32F10x Interrupt Number Definition, according to the selected device N * in @ref Library_configuration_section N */ Ntypedef enum IRQn N{ N/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ N NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ N MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ N BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ N UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ N SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ N DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ N PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ N SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ N N/****** STM32 specific Interrupt Numbers *********************************************************/ N WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ N PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ N TAMPER_IRQn = 2, /*!< Tamper Interrupt */ N RTC_IRQn = 3, /*!< RTC global Interrupt */ N FLASH_IRQn = 4, /*!< FLASH global Interrupt */ N RCC_IRQn = 5, /*!< RCC global Interrupt */ N EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ N EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ N EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ N EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ N EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ N DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ N DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ N DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ N DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ N DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ N DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ N DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ N N#ifdef STM32F10X_LD S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ N#endif /* STM32F10X_LD */ N N#ifdef STM32F10X_LD_VL S ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ S TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ S TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ S TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ S TIM7_IRQn = 55 /*!< TIM7 Interrupt */ N#endif /* STM32F10X_LD_VL */ N N#ifdef STM32F10X_MD N ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ N USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ N USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ N CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ N CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ N EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ N TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ N TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ N TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ N TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ N TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ N TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ N TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ N I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ N I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ N I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ N I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ N SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ N SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ N USART1_IRQn = 37, /*!< USART1 global Interrupt */ N USART2_IRQn = 38, /*!< USART2 global Interrupt */ N USART3_IRQn = 39, /*!< USART3 global Interrupt */ N EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ N RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ N USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ N#endif /* STM32F10X_MD */ N N#ifdef STM32F10X_MD_VL S ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ S TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ S TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ S TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ S TIM7_IRQn = 55 /*!< TIM7 Interrupt */ N#endif /* STM32F10X_MD_VL */ N N#ifdef STM32F10X_HD S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ S TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ S TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ S TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ S TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ S ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ S FSMC_IRQn = 48, /*!< FSMC global Interrupt */ S SDIO_IRQn = 49, /*!< SDIO global Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ N#endif /* STM32F10X_HD */ N N#ifdef STM32F10X_HD_VL S ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ S TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ S TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ S TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ S TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ S TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ S DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is S mapped at position 60 only if the MISC_REMAP bit in S the AFIO_MAPR2 register is set) */ N#endif /* STM32F10X_HD_VL */ N N#ifdef STM32F10X_XL S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ S TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ S TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ S TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ S TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ S TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ S TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ S ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ S FSMC_IRQn = 48, /*!< FSMC global Interrupt */ S SDIO_IRQn = 49, /*!< SDIO global Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ N#endif /* STM32F10X_XL */ N N#ifdef STM32F10X_CL S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ S DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ S ETH_IRQn = 61, /*!< Ethernet global Interrupt */ S ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ S CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ S CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ S CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ S CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ S OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ N#endif /* STM32F10X_CL */ N} IRQn_Type; N N/** N * @} N */ N N#include "core_cm3.h" L 1 "..\..\template\Libraries\CMSIS\core_cm3.h" 1 N/**************************************************************************//** N * @file core_cm3.h N * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File N * @version V1.30 N * @date 30. October 2009 N * N * @note N * Copyright (C) 2009 ARM Limited. All rights reserved. N * N * @par N * ARM Limited (ARM) is supplying this software for use with Cortex-M N * processor based microcontrollers. This file can be freely distributed N * within development tools that are supporting such ARM based processors. N * N * @par N * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. N * N ******************************************************************************/ N N#ifndef __CM3_CORE_H__ N#define __CM3_CORE_H__ N N/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration N * N * List of Lint messages which will be suppressed and not shown: N * - Error 10: \n N * register uint32_t __regBasePri __asm("basepri"); \n N * Error 10: Expecting ';' N * . N * - Error 530: \n N * return(__regBasePri); \n N * Warning 530: Symbol '__regBasePri' (line 264) not initialized N * . N * - Error 550: \n N * __regBasePri = (basePri & 0x1ff); \n N * Warning 550: Symbol '__regBasePri' (line 271) not accessed N * . N * - Error 754: \n N * uint32_t RESERVED0[24]; \n N * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced N * . N * - Error 750: \n N * #define __CM3_CORE_H__ \n N * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced N * . N * - Error 528: \n N * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n N * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced N * . N * - Error 751: \n N * } InterruptType_Type; \n N * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced N * . N * Note: To re-enable a Message, insert a space before 'lint' * N * N */ N N/*lint -save */ N/*lint -e10 */ N/*lint -e530 */ N/*lint -e550 */ N/*lint -e754 */ N/*lint -e750 */ N/*lint -e528 */ N/*lint -e751 */ N N N/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions N This file defines all structures and symbols for CMSIS core: N - CMSIS version number N - Cortex-M core registers and bitfields N - Cortex-M core peripheral base address N @{ N */ N N#ifdef __cplusplus S extern "C" { N#endif N N#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ N#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ N#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ N N#define __CORTEX_M (0x03) /*!< Cortex core */ N N#include /* Include standard types */ L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1 N/* Copyright (C) ARM Ltd., 1999,2014 */ N/* All rights reserved */ N N/* N * RCS $Revision$ N * Checkin $Date$ N * Revising $Author: agrant $ N */ N N#ifndef __stdint_h N#define __stdint_h N#define __ARMCLIB_VERSION 5060037 N N #ifdef __INT64_TYPE__ S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */ S #define __INT64 __INT64_TYPE__ N #else N /* armcc has builtin '__int64' which can be used in --strict mode */ N #define __INT64 __int64 N #define __INT64_C_SUFFIX__ ll N #endif N #define __PASTE2(x, y) x ## y N #define __PASTE(x, y) __PASTE2(x, y) N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) X #if 0L || (1L && !0L) N /* armclang and non-strict armcc allow 'long long' in system headers */ N #define __LONGLONG long long N #else S /* strict armcc has '__int64' */ S #define __LONGLONG __int64 N #endif N N #ifndef __STDINT_DECLS N #define __STDINT_DECLS N N #undef __CLIBNS N N #ifdef __cplusplus S namespace std { S #define __CLIBNS std:: S extern "C" { N #else N #define __CLIBNS N #endif /* __cplusplus */ N N N/* N * 'signed' is redundant below, except for 'signed char' and if N * the typedef is used to declare a bitfield. N */ N N /* 7.18.1.1 */ N N /* exact-width signed integer types */ Ntypedef signed char int8_t; Ntypedef signed short int int16_t; Ntypedef signed int int32_t; Ntypedef signed __INT64 int64_t; Xtypedef signed __int64 int64_t; N N /* exact-width unsigned integer types */ Ntypedef unsigned char uint8_t; Ntypedef unsigned short int uint16_t; Ntypedef unsigned int uint32_t; Ntypedef unsigned __INT64 uint64_t; Xtypedef unsigned __int64 uint64_t; N N /* 7.18.1.2 */ N N /* smallest type of at least n bits */ N /* minimum-width signed integer types */ Ntypedef signed char int_least8_t; Ntypedef signed short int int_least16_t; Ntypedef signed int int_least32_t; Ntypedef signed __INT64 int_least64_t; Xtypedef signed __int64 int_least64_t; N N /* minimum-width unsigned integer types */ Ntypedef unsigned char uint_least8_t; Ntypedef unsigned short int uint_least16_t; Ntypedef unsigned int uint_least32_t; Ntypedef unsigned __INT64 uint_least64_t; Xtypedef unsigned __int64 uint_least64_t; N N /* 7.18.1.3 */ N N /* fastest minimum-width signed integer types */ Ntypedef signed int int_fast8_t; Ntypedef signed int int_fast16_t; Ntypedef signed int int_fast32_t; Ntypedef signed __INT64 int_fast64_t; Xtypedef signed __int64 int_fast64_t; N N /* fastest minimum-width unsigned integer types */ Ntypedef unsigned int uint_fast8_t; Ntypedef unsigned int uint_fast16_t; Ntypedef unsigned int uint_fast32_t; Ntypedef unsigned __INT64 uint_fast64_t; Xtypedef unsigned __int64 uint_fast64_t; N N /* 7.18.1.4 integer types capable of holding object pointers */ N#if __sizeof_ptr == 8 X#if 4 == 8 Stypedef signed __INT64 intptr_t; Stypedef unsigned __INT64 uintptr_t; N#else Ntypedef signed int intptr_t; Ntypedef unsigned int uintptr_t; N#endif N N /* 7.18.1.5 greatest-width integer types */ Ntypedef signed __LONGLONG intmax_t; Xtypedef signed long long intmax_t; Ntypedef unsigned __LONGLONG uintmax_t; Xtypedef unsigned long long uintmax_t; N N N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) X#if !0L || 0L N N /* 7.18.2.1 */ N N /* minimum values of exact-width signed integer types */ N#define INT8_MIN -128 N#define INT16_MIN -32768 N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */ N N /* maximum values of exact-width signed integer types */ N#define INT8_MAX 127 N#define INT16_MAX 32767 N#define INT32_MAX 2147483647 N#define INT64_MAX __INT64_C(9223372036854775807) N N /* maximum values of exact-width unsigned integer types */ N#define UINT8_MAX 255 N#define UINT16_MAX 65535 N#define UINT32_MAX 4294967295u N#define UINT64_MAX __UINT64_C(18446744073709551615) N N /* 7.18.2.2 */ N N /* minimum values of minimum-width signed integer types */ N#define INT_LEAST8_MIN -128 N#define INT_LEAST16_MIN -32768 N#define INT_LEAST32_MIN (~0x7fffffff) N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) N N /* maximum values of minimum-width signed integer types */ N#define INT_LEAST8_MAX 127 N#define INT_LEAST16_MAX 32767 N#define INT_LEAST32_MAX 2147483647 N#define INT_LEAST64_MAX __INT64_C(9223372036854775807) N N /* maximum values of minimum-width unsigned integer types */ N#define UINT_LEAST8_MAX 255 N#define UINT_LEAST16_MAX 65535 N#define UINT_LEAST32_MAX 4294967295u N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615) N N /* 7.18.2.3 */ N N /* minimum values of fastest minimum-width signed integer types */ N#define INT_FAST8_MIN (~0x7fffffff) N#define INT_FAST16_MIN (~0x7fffffff) N#define INT_FAST32_MIN (~0x7fffffff) N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) N N /* maximum values of fastest minimum-width signed integer types */ N#define INT_FAST8_MAX 2147483647 N#define INT_FAST16_MAX 2147483647 N#define INT_FAST32_MAX 2147483647 N#define INT_FAST64_MAX __INT64_C(9223372036854775807) N N /* maximum values of fastest minimum-width unsigned integer types */ N#define UINT_FAST8_MAX 4294967295u N#define UINT_FAST16_MAX 4294967295u N#define UINT_FAST32_MAX 4294967295u N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615) N N /* 7.18.2.4 */ N N /* minimum value of pointer-holding signed integer type */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define INTPTR_MIN INT64_MIN N#else N#define INTPTR_MIN INT32_MIN N#endif N N /* maximum value of pointer-holding signed integer type */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define INTPTR_MAX INT64_MAX N#else N#define INTPTR_MAX INT32_MAX N#endif N N /* maximum value of pointer-holding unsigned integer type */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define UINTPTR_MAX UINT64_MAX N#else N#define UINTPTR_MAX UINT32_MAX N#endif N N /* 7.18.2.5 */ N N /* minimum value of greatest-width signed integer type */ N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) N N /* maximum value of greatest-width signed integer type */ N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll) N N /* maximum value of greatest-width unsigned integer type */ N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) N N /* 7.18.3 */ N N /* limits of ptrdiff_t */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define PTRDIFF_MIN INT64_MIN S#define PTRDIFF_MAX INT64_MAX N#else N#define PTRDIFF_MIN INT32_MIN N#define PTRDIFF_MAX INT32_MAX N#endif N N /* limits of sig_atomic_t */ N#define SIG_ATOMIC_MIN (~0x7fffffff) N#define SIG_ATOMIC_MAX 2147483647 N N /* limit of size_t */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define SIZE_MAX UINT64_MAX N#else N#define SIZE_MAX UINT32_MAX N#endif N N /* limits of wchar_t */ N /* NB we have to undef and redef because they're defined in both N * stdint.h and wchar.h */ N#undef WCHAR_MIN N#undef WCHAR_MAX N N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4) S #define WCHAR_MIN 0 S #define WCHAR_MAX 0xffffffffU N#else N #define WCHAR_MIN 0 N #define WCHAR_MAX 65535 N#endif N N /* limits of wint_t */ N#define WINT_MIN (~0x7fffffff) N#define WINT_MAX 2147483647 N N#endif /* __STDC_LIMIT_MACROS */ N N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) X#if !0L || 0L N N /* 7.18.4.1 macros for minimum-width integer constants */ N#define INT8_C(x) (x) N#define INT16_C(x) (x) N#define INT32_C(x) (x) N#define INT64_C(x) __INT64_C(x) N N#define UINT8_C(x) (x ## u) N#define UINT16_C(x) (x ## u) N#define UINT32_C(x) (x ## u) N#define UINT64_C(x) __UINT64_C(x) N N /* 7.18.4.2 macros for greatest-width integer constants */ N#define INTMAX_C(x) __ESCAPE__(x ## ll) N#define UINTMAX_C(x) __ESCAPE__(x ## ull) N N#endif /* __STDC_CONSTANT_MACROS */ N N #ifdef __cplusplus S } /* extern "C" */ S } /* namespace std */ N #endif /* __cplusplus */ N #endif /* __STDINT_DECLS */ N N #ifdef __cplusplus S #ifndef __STDINT_NO_EXPORTS S using ::std::int8_t; S using ::std::int16_t; S using ::std::int32_t; S using ::std::int64_t; S using ::std::uint8_t; S using ::std::uint16_t; S using ::std::uint32_t; S using ::std::uint64_t; S using ::std::int_least8_t; S using ::std::int_least16_t; S using ::std::int_least32_t; S using ::std::int_least64_t; S using ::std::uint_least8_t; S using ::std::uint_least16_t; S using ::std::uint_least32_t; S using ::std::uint_least64_t; S using ::std::int_fast8_t; S using ::std::int_fast16_t; S using ::std::int_fast32_t; S using ::std::int_fast64_t; S using ::std::uint_fast8_t; S using ::std::uint_fast16_t; S using ::std::uint_fast32_t; S using ::std::uint_fast64_t; S using ::std::intptr_t; S using ::std::uintptr_t; S using ::std::intmax_t; S using ::std::uintmax_t; S #endif N #endif /* __cplusplus */ N N#undef __INT64 N#undef __LONGLONG N N#endif /* __stdint_h */ N N/* end of stdint.h */ L 91 "..\..\template\Libraries\CMSIS\core_cm3.h" 2 N N#if defined (__ICCARM__) X#if 0L S #include /* IAR Intrinsics */ N#endif N N N#ifndef __NVIC_PRIO_BITS S #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ N#endif N N N N N/** N * IO definitions N * N * define access restrictions to peripheral registers N */ N N#ifdef __cplusplus S #define __I volatile /*!< defines 'read only' permissions */ N#else N #define __I volatile const /*!< defines 'read only' permissions */ N#endif N#define __O volatile /*!< defines 'write only' permissions */ N#define __IO volatile /*!< defines 'read / write' permissions */ N N N N/******************************************************************************* N * Register Abstraction N ******************************************************************************/ N/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register N @{ N*/ N N N/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC N memory mapped structure for Nested Vectored Interrupt Controller (NVIC) N @{ N */ Ntypedef struct N{ N __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ X volatile uint32_t ISER[8]; N uint32_t RESERVED0[24]; N __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ X volatile uint32_t ICER[8]; N uint32_t RSERVED1[24]; N __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ X volatile uint32_t ISPR[8]; N uint32_t RESERVED2[24]; N __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ X volatile uint32_t ICPR[8]; N uint32_t RESERVED3[24]; N __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ X volatile uint32_t IABR[8]; N uint32_t RESERVED4[56]; N __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ X volatile uint8_t IP[240]; N uint32_t RESERVED5[644]; N __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ X volatile uint32_t STIR; N} NVIC_Type; N/*@}*/ /* end of group CMSIS_CM3_NVIC */ N N N/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB N memory mapped structure for System Control Block (SCB) N @{ N */ Ntypedef struct N{ N __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ X volatile const uint32_t CPUID; N __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ X volatile uint32_t ICSR; N __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ X volatile uint32_t VTOR; N __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ X volatile uint32_t AIRCR; N __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ X volatile uint32_t SCR; N __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ X volatile uint32_t CCR; N __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ X volatile uint8_t SHP[12]; N __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ X volatile uint32_t SHCSR; N __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ X volatile uint32_t CFSR; N __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ X volatile uint32_t HFSR; N __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ X volatile uint32_t DFSR; N __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ X volatile uint32_t MMFAR; N __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ X volatile uint32_t BFAR; N __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ X volatile uint32_t AFSR; N __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ X volatile const uint32_t PFR[2]; N __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ X volatile const uint32_t DFR; N __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ X volatile const uint32_t ADR; N __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ X volatile const uint32_t MMFR[4]; N __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ X volatile const uint32_t ISAR[5]; N} SCB_Type; N N/* SCB CPUID Register Definitions */ N#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ N N#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ N#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ N N#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ N#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ N N#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ N#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ N N/* SCB Interrupt Control State Register Definitions */ N#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ N#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ N N#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ N#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ N N#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ N#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ N N#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ N#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ N N#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ N#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ N N#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ N#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ N N#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ N#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ N N#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ N#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ N N#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ N#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ N N#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ N N/* SCB Interrupt Control State Register Definitions */ N#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ N#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ N N#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ N#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ N N/* SCB Application Interrupt and Reset Control Register Definitions */ N#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ N N#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ N N#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ N#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ N N#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ N#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ N N#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ N#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ N N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ N N#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ N#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ N N/* SCB System Control Register Definitions */ N#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ N#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ N N#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ N#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ N N#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ N#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ N N/* SCB Configuration Control Register Definitions */ N#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ N#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ N N#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ N#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ N N#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ N#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ N N#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ N#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ N N#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ N#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ N N#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ N#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ N N/* SCB System Handler Control and State Register Definitions */ N#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ N#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ N N#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ N#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ N N#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ N#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ N N#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ N#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ N N#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ N#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ N N#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ N#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ N N#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ N#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ N N#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ N#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ N N#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ N#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ N N#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ N#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ N N#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ N#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ N N#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ N#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ N N#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ N#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ N N#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ N#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ N N/* SCB Configurable Fault Status Registers Definitions */ N#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ N#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ N N#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ N#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ N N#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ N#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ N N/* SCB Hard Fault Status Registers Definitions */ N#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ N#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ N N#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ N#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ N N#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ N#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ N N/* SCB Debug Fault Status Register Definitions */ N#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ N#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ N N#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ N#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ N N#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ N#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ N N#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ N#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ N N#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ N#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ N/*@}*/ /* end of group CMSIS_CM3_SCB */ N N N/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick N memory mapped structure for SysTick N @{ N */ Ntypedef struct N{ N __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ X volatile uint32_t CTRL; N __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ X volatile uint32_t LOAD; N __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ X volatile uint32_t VAL; N __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ X volatile const uint32_t CALIB; N} SysTick_Type; N N/* SysTick Control / Status Register Definitions */ N#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ N#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ N N#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ N#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ N N#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ N#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ N N#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ N#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ N N/* SysTick Reload Register Definitions */ N#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ N#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ N N/* SysTick Current Register Definitions */ N#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ N#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ N N/* SysTick Calibration Register Definitions */ N#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ N#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ N N#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ N#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ N N#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ N#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ N/*@}*/ /* end of group CMSIS_CM3_SysTick */ N N N/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM N memory mapped structure for Instrumentation Trace Macrocell (ITM) N @{ N */ Ntypedef struct N{ N __O union X volatile union N { N __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ X volatile uint8_t u8; N __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ X volatile uint16_t u16; N __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ X volatile uint32_t u32; N } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ N uint32_t RESERVED0[864]; N __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ X volatile uint32_t TER; N uint32_t RESERVED1[15]; N __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ X volatile uint32_t TPR; N uint32_t RESERVED2[15]; N __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ X volatile uint32_t TCR; N uint32_t RESERVED3[29]; N __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ X volatile uint32_t IWR; N __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ X volatile uint32_t IRR; N __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ X volatile uint32_t IMCR; N uint32_t RESERVED4[43]; N __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ X volatile uint32_t LAR; N __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ X volatile uint32_t LSR; N uint32_t RESERVED5[6]; N __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ X volatile const uint32_t PID4; N __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ X volatile const uint32_t PID5; N __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ X volatile const uint32_t PID6; N __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ X volatile const uint32_t PID7; N __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ X volatile const uint32_t PID0; N __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ X volatile const uint32_t PID1; N __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ X volatile const uint32_t PID2; N __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ X volatile const uint32_t PID3; N __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ X volatile const uint32_t CID0; N __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ X volatile const uint32_t CID1; N __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ X volatile const uint32_t CID2; N __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ X volatile const uint32_t CID3; N} ITM_Type; N N/* ITM Trace Privilege Register Definitions */ N#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ N#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ N N/* ITM Trace Control Register Definitions */ N#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ N#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ N N#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ N#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ N N#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ N#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ N N#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ N#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ N N#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ N#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ N N#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ N#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ N N#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ N#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ N N#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ N#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ N N/* ITM Integration Write Register Definitions */ N#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ N#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ N N/* ITM Integration Read Register Definitions */ N#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ N#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ N N/* ITM Integration Mode Control Register Definitions */ N#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ N#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ N N/* ITM Lock Status Register Definitions */ N#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ N#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ N N#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ N#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ N N#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ N#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ N/*@}*/ /* end of group CMSIS_CM3_ITM */ N N N/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type N memory mapped structure for Interrupt Type N @{ N */ Ntypedef struct N{ N uint32_t RESERVED0; N __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ X volatile const uint32_t ICTR; N#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) X#if ((0L) && (__CM3_REV >= 0x200)) S __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ N#else N uint32_t RESERVED1; N#endif N} InterruptType_Type; N N/* Interrupt Controller Type Register Definitions */ N#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ N#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ N N/* Auxiliary Control Register Definitions */ N#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ N#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ N N#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ N#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ N N#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ N#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ N/*@}*/ /* end of group CMSIS_CM3_InterruptType */ N N N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) X#if 1L && (0 == 1) S/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU S memory mapped structure for Memory Protection Unit (MPU) S @{ S */ Stypedef struct S{ S __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ S __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ S __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ S __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ S __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ S __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ S __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ S __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ S __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ S __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ S __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ S} MPU_Type; S S/* MPU Type Register */ S#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ S#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ S S#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ S#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ S S#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ S#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ S S/* MPU Control Register */ S#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ S#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ S S#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ S#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ S S#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ S#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ S S/* MPU Region Number Register */ S#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ S#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ S S/* MPU Region Base Address Register */ S#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ S#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ S S#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ S#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ S S#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ S#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ S S/* MPU Region Attribute and Size Register */ S#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ S#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ S S#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ S#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ S S#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ S#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ S S#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ S#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ S S#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ S#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ S S#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ S#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ S S#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ S#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ S S#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ S#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ S S#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ S#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ S S/*@}*/ /* end of group CMSIS_CM3_MPU */ N#endif N N N/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug N memory mapped structure for Core Debug Register N @{ N */ Ntypedef struct N{ N __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ X volatile uint32_t DHCSR; N __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ X volatile uint32_t DCRSR; N __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ X volatile uint32_t DCRDR; N __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ X volatile uint32_t DEMCR; N} CoreDebug_Type; N N/* Debug Halting Control and Status Register */ N#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ N#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ N N#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ N#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ N N#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ N#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ N N#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ N#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ N N#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ N#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ N N#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ N#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ N N#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ N#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ N N#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ N#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ N N#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ N#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ N N#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ N#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ N N#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ N#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ N N#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ N#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ N N/* Debug Core Register Selector Register */ N#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ N#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ N N#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ N#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ N N/* Debug Exception and Monitor Control Register */ N#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ N#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ N N#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ N#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ N N#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ N#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ N N#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ N#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ N N#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ N#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ N N#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ N#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ N N#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ N#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ N N#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ N#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ N N#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ N#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ N N#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ N#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ N N#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ N#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ N N#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ N#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ N N#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ N#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ N/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ N N N/* Memory mapping of Cortex-M3 Hardware */ N#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ N#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ N#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ N#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ N#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ N#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ N N#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ N#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ N#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ N#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ N#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ N#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ N N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) X#if 1L && (0 == 1) S #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ S #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ N#endif N N/*@}*/ /* end of group CMSIS_CM3_core_register */ N N N/******************************************************************************* N * Hardware Abstraction Layer N ******************************************************************************/ N N#if defined ( __CC_ARM ) X#if 1L N #define __ASM __asm /*!< asm keyword for ARM Compiler */ N #define __INLINE __inline /*!< inline keyword for ARM Compiler */ N N#elif defined ( __ICCARM__ ) S #define __ASM __asm /*!< asm keyword for IAR Compiler */ S #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ S S#elif defined ( __GNUC__ ) S #define __ASM __asm /*!< asm keyword for GNU Compiler */ S #define __INLINE inline /*!< inline keyword for GNU Compiler */ S S#elif defined ( __TASKING__ ) S #define __ASM __asm /*!< asm keyword for TASKING Compiler */ S #define __INLINE inline /*!< inline keyword for TASKING Compiler */ S N#endif N N N/* ################### Compiler specific Intrinsics ########################### */ N N#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ X#if 1L N/* ARM armcc specific functions */ N N#define __enable_fault_irq __enable_fiq N#define __disable_fault_irq __disable_fiq N N#define __NOP __nop N#define __WFI __wfi N#define __WFE __wfe N#define __SEV __sev N#define __ISB() __isb(0) N#define __DSB() __dsb(0) N#define __DMB() __dmb(0) N#define __REV __rev N#define __RBIT __rbit N#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) N#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) N#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) N#define __STREXB(value, ptr) __strex(value, ptr) N#define __STREXH(value, ptr) __strex(value, ptr) N#define __STREXW(value, ptr) __strex(value, ptr) N N N/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ N/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ N/* intrinsic void __enable_irq(); */ N/* intrinsic void __disable_irq(); */ N N N/** N * @brief Return the Process Stack Pointer N * N * @return ProcessStackPointer N * N * Return the actual process stack pointer N */ Nextern uint32_t __get_PSP(void); N N/** N * @brief Set the Process Stack Pointer N * N * @param topOfProcStack Process Stack Pointer N * N * Assign the value ProcessStackPointer to the MSP N * (process stack pointer) Cortex processor register N */ Nextern void __set_PSP(uint32_t topOfProcStack); N N/** N * @brief Return the Main Stack Pointer N * N * @return Main Stack Pointer N * N * Return the current value of the MSP (main stack pointer) N * Cortex processor register N */ Nextern uint32_t __get_MSP(void); N N/** N * @brief Set the Main Stack Pointer N * N * @param topOfMainStack Main Stack Pointer N * N * Assign the value mainStackPointer to the MSP N * (main stack pointer) Cortex processor register N */ Nextern void __set_MSP(uint32_t topOfMainStack); N N/** N * @brief Reverse byte order in unsigned short value N * N * @param value value to reverse N * @return reversed value N * N * Reverse byte order in unsigned short value N */ Nextern uint32_t __REV16(uint16_t value); N N/** N * @brief Reverse byte order in signed short value with sign extension to integer N * N * @param value value to reverse N * @return reversed value N * N * Reverse byte order in signed short value with sign extension to integer N */ Nextern int32_t __REVSH(int16_t value); N N N#if (__ARMCC_VERSION < 400000) X#if (5060750 < 400000) S S/** S * @brief Remove the exclusive lock created by ldrex S * S * Removes the exclusive lock which is created by ldrex. S */ Sextern void __CLREX(void); S S/** S * @brief Return the Base Priority value S * S * @return BasePriority S * S * Return the content of the base priority register S */ Sextern uint32_t __get_BASEPRI(void); S S/** S * @brief Set the Base Priority value S * S * @param basePri BasePriority S * S * Set the base priority register S */ Sextern void __set_BASEPRI(uint32_t basePri); S S/** S * @brief Return the Priority Mask value S * S * @return PriMask S * S * Return state of the priority mask bit from the priority mask register S */ Sextern uint32_t __get_PRIMASK(void); S S/** S * @brief Set the Priority Mask value S * S * @param priMask PriMask S * S * Set the priority mask bit in the priority mask register S */ Sextern void __set_PRIMASK(uint32_t priMask); S S/** S * @brief Return the Fault Mask value S * S * @return FaultMask S * S * Return the content of the fault mask register S */ Sextern uint32_t __get_FAULTMASK(void); S S/** S * @brief Set the Fault Mask value S * S * @param faultMask faultMask value S * S * Set the fault mask register S */ Sextern void __set_FAULTMASK(uint32_t faultMask); S S/** S * @brief Return the Control Register value S * S * @return Control value S * S * Return the content of the control register S */ Sextern uint32_t __get_CONTROL(void); S S/** S * @brief Set the Control Register value S * S * @param control Control value S * S * Set the control register S */ Sextern void __set_CONTROL(uint32_t control); S N#else /* (__ARMCC_VERSION >= 400000) */ N N/** N * @brief Remove the exclusive lock created by ldrex N * N * Removes the exclusive lock which is created by ldrex. N */ N#define __CLREX __clrex N N/** N * @brief Return the Base Priority value N * N * @return BasePriority N * N * Return the content of the base priority register N */ Nstatic __INLINE uint32_t __get_BASEPRI(void) Xstatic __inline uint32_t __get_BASEPRI(void) N{ N register uint32_t __regBasePri __ASM("basepri"); X register uint32_t __regBasePri __asm("basepri"); N return(__regBasePri); N} N N/** N * @brief Set the Base Priority value N * N * @param basePri BasePriority N * N * Set the base priority register N */ Nstatic __INLINE void __set_BASEPRI(uint32_t basePri) Xstatic __inline void __set_BASEPRI(uint32_t basePri) N{ N register uint32_t __regBasePri __ASM("basepri"); X register uint32_t __regBasePri __asm("basepri"); N __regBasePri = (basePri & 0xff); N} N N/** N * @brief Return the Priority Mask value N * N * @return PriMask N * N * Return state of the priority mask bit from the priority mask register N */ Nstatic __INLINE uint32_t __get_PRIMASK(void) Xstatic __inline uint32_t __get_PRIMASK(void) N{ N register uint32_t __regPriMask __ASM("primask"); X register uint32_t __regPriMask __asm("primask"); N return(__regPriMask); N} N N/** N * @brief Set the Priority Mask value N * N * @param priMask PriMask N * N * Set the priority mask bit in the priority mask register N */ Nstatic __INLINE void __set_PRIMASK(uint32_t priMask) Xstatic __inline void __set_PRIMASK(uint32_t priMask) N{ N register uint32_t __regPriMask __ASM("primask"); X register uint32_t __regPriMask __asm("primask"); N __regPriMask = (priMask); N} N N/** N * @brief Return the Fault Mask value N * N * @return FaultMask N * N * Return the content of the fault mask register N */ Nstatic __INLINE uint32_t __get_FAULTMASK(void) Xstatic __inline uint32_t __get_FAULTMASK(void) N{ N register uint32_t __regFaultMask __ASM("faultmask"); X register uint32_t __regFaultMask __asm("faultmask"); N return(__regFaultMask); N} N N/** N * @brief Set the Fault Mask value N * N * @param faultMask faultMask value N * N * Set the fault mask register N */ Nstatic __INLINE void __set_FAULTMASK(uint32_t faultMask) Xstatic __inline void __set_FAULTMASK(uint32_t faultMask) N{ N register uint32_t __regFaultMask __ASM("faultmask"); X register uint32_t __regFaultMask __asm("faultmask"); N __regFaultMask = (faultMask & 1); N} N N/** N * @brief Return the Control Register value N * N * @return Control value N * N * Return the content of the control register N */ Nstatic __INLINE uint32_t __get_CONTROL(void) Xstatic __inline uint32_t __get_CONTROL(void) N{ N register uint32_t __regControl __ASM("control"); X register uint32_t __regControl __asm("control"); N return(__regControl); N} N N/** N * @brief Set the Control Register value N * N * @param control Control value N * N * Set the control register N */ Nstatic __INLINE void __set_CONTROL(uint32_t control) Xstatic __inline void __set_CONTROL(uint32_t control) N{ N register uint32_t __regControl __ASM("control"); X register uint32_t __regControl __asm("control"); N __regControl = control; N} N N#endif /* __ARMCC_VERSION */ N N N N#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ S/* IAR iccarm specific functions */ S S#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ S#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ S Sstatic __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } Sstatic __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } S S#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ Sstatic __INLINE void __WFI() { __ASM ("wfi"); } Sstatic __INLINE void __WFE() { __ASM ("wfe"); } Sstatic __INLINE void __SEV() { __ASM ("sev"); } Sstatic __INLINE void __CLREX() { __ASM ("clrex"); } S S/* intrinsic void __ISB(void) */ S/* intrinsic void __DSB(void) */ S/* intrinsic void __DMB(void) */ S/* intrinsic void __set_PRIMASK(); */ S/* intrinsic void __get_PRIMASK(); */ S/* intrinsic void __set_FAULTMASK(); */ S/* intrinsic void __get_FAULTMASK(); */ S/* intrinsic uint32_t __REV(uint32_t value); */ S/* intrinsic uint32_t __REVSH(uint32_t value); */ S/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ S/* intrinsic unsigned long __LDREX(unsigned long *); */ S S S/** S * @brief Return the Process Stack Pointer S * S * @return ProcessStackPointer S * S * Return the actual process stack pointer S */ Sextern uint32_t __get_PSP(void); S S/** S * @brief Set the Process Stack Pointer S * S * @param topOfProcStack Process Stack Pointer S * S * Assign the value ProcessStackPointer to the MSP S * (process stack pointer) Cortex processor register S */ Sextern void __set_PSP(uint32_t topOfProcStack); S S/** S * @brief Return the Main Stack Pointer S * S * @return Main Stack Pointer S * S * Return the current value of the MSP (main stack pointer) S * Cortex processor register S */ Sextern uint32_t __get_MSP(void); S S/** S * @brief Set the Main Stack Pointer S * S * @param topOfMainStack Main Stack Pointer S * S * Assign the value mainStackPointer to the MSP S * (main stack pointer) Cortex processor register S */ Sextern void __set_MSP(uint32_t topOfMainStack); S S/** S * @brief Reverse byte order in unsigned short value S * S * @param value value to reverse S * @return reversed value S * S * Reverse byte order in unsigned short value S */ Sextern uint32_t __REV16(uint16_t value); S S/** S * @brief Reverse bit order of value S * S * @param value value to reverse S * @return reversed value S * S * Reverse bit order of value S */ Sextern uint32_t __RBIT(uint32_t value); S S/** S * @brief LDR Exclusive (8 bit) S * S * @param *addr address pointer S * @return value of (*address) S * S * Exclusive LDR command for 8 bit values) S */ Sextern uint8_t __LDREXB(uint8_t *addr); S S/** S * @brief LDR Exclusive (16 bit) S * S * @param *addr address pointer S * @return value of (*address) S * S * Exclusive LDR command for 16 bit values S */ Sextern uint16_t __LDREXH(uint16_t *addr); S S/** S * @brief LDR Exclusive (32 bit) S * S * @param *addr address pointer S * @return value of (*address) S * S * Exclusive LDR command for 32 bit values S */ Sextern uint32_t __LDREXW(uint32_t *addr); S S/** S * @brief STR Exclusive (8 bit) S * S * @param value value to store S * @param *addr address pointer S * @return successful / failed S * S * Exclusive STR command for 8 bit values S */ Sextern uint32_t __STREXB(uint8_t value, uint8_t *addr); S S/** S * @brief STR Exclusive (16 bit) S * S * @param value value to store S * @param *addr address pointer S * @return successful / failed S * S * Exclusive STR command for 16 bit values S */ Sextern uint32_t __STREXH(uint16_t value, uint16_t *addr); S S/** S * @brief STR Exclusive (32 bit) S * S * @param value value to store S * @param *addr address pointer S * @return successful / failed S * S * Exclusive STR command for 32 bit values S */ Sextern uint32_t __STREXW(uint32_t value, uint32_t *addr); S S S S#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ S/* GNU gcc specific functions */ S Sstatic __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } Sstatic __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } S Sstatic __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } Sstatic __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } S Sstatic __INLINE void __NOP() { __ASM volatile ("nop"); } Sstatic __INLINE void __WFI() { __ASM volatile ("wfi"); } Sstatic __INLINE void __WFE() { __ASM volatile ("wfe"); } Sstatic __INLINE void __SEV() { __ASM volatile ("sev"); } Sstatic __INLINE void __ISB() { __ASM volatile ("isb"); } Sstatic __INLINE void __DSB() { __ASM volatile ("dsb"); } Sstatic __INLINE void __DMB() { __ASM volatile ("dmb"); } Sstatic __INLINE void __CLREX() { __ASM volatile ("clrex"); } S S S/** S * @brief Return the Process Stack Pointer S * S * @return ProcessStackPointer S * S * Return the actual process stack pointer S */ Sextern uint32_t __get_PSP(void); S S/** S * @brief Set the Process Stack Pointer S * S * @param topOfProcStack Process Stack Pointer S * S * Assign the value ProcessStackPointer to the MSP S * (process stack pointer) Cortex processor register S */ Sextern void __set_PSP(uint32_t topOfProcStack); S S/** S * @brief Return the Main Stack Pointer S * S * @return Main Stack Pointer S * S * Return the current value of the MSP (main stack pointer) S * Cortex processor register S */ Sextern uint32_t __get_MSP(void); S S/** S * @brief Set the Main Stack Pointer S * S * @param topOfMainStack Main Stack Pointer S * S * Assign the value mainStackPointer to the MSP S * (main stack pointer) Cortex processor register S */ Sextern void __set_MSP(uint32_t topOfMainStack); S S/** S * @brief Return the Base Priority value S * S * @return BasePriority S * S * Return the content of the base priority register S */ Sextern uint32_t __get_BASEPRI(void); S S/** S * @brief Set the Base Priority value S * S * @param basePri BasePriority S * S * Set the base priority register S */ Sextern void __set_BASEPRI(uint32_t basePri); S S/** S * @brief Return the Priority Mask value S * S * @return PriMask S * S * Return state of the priority mask bit from the priority mask register S */ Sextern uint32_t __get_PRIMASK(void); S S/** S * @brief Set the Priority Mask value S * S * @param priMask PriMask S * S * Set the priority mask bit in the priority mask register S */ Sextern void __set_PRIMASK(uint32_t priMask); S S/** S * @brief Return the Fault Mask value S * S * @return FaultMask S * S * Return the content of the fault mask register S */ Sextern uint32_t __get_FAULTMASK(void); S S/** S * @brief Set the Fault Mask value S * S * @param faultMask faultMask value S * S * Set the fault mask register S */ Sextern void __set_FAULTMASK(uint32_t faultMask); S S/** S * @brief Return the Control Register value S* S* @return Control value S * S * Return the content of the control register S */ Sextern uint32_t __get_CONTROL(void); S S/** S * @brief Set the Control Register value S * S * @param control Control value S * S * Set the control register S */ Sextern void __set_CONTROL(uint32_t control); S S/** S * @brief Reverse byte order in integer value S * S * @param value value to reverse S * @return reversed value S * S * Reverse byte order in integer value S */ Sextern uint32_t __REV(uint32_t value); S S/** S * @brief Reverse byte order in unsigned short value S * S * @param value value to reverse S * @return reversed value S * S * Reverse byte order in unsigned short value S */ Sextern uint32_t __REV16(uint16_t value); S S/** S * @brief Reverse byte order in signed short value with sign extension to integer S * S * @param value value to reverse S * @return reversed value S * S * Reverse byte order in signed short value with sign extension to integer S */ Sextern int32_t __REVSH(int16_t value); S S/** S * @brief Reverse bit order of value S * S * @param value value to reverse S * @return reversed value S * S * Reverse bit order of value S */ Sextern uint32_t __RBIT(uint32_t value); S S/** S * @brief LDR Exclusive (8 bit) S * S * @param *addr address pointer S * @return value of (*address) S * S * Exclusive LDR command for 8 bit value S */ Sextern uint8_t __LDREXB(uint8_t *addr); S S/** S * @brief LDR Exclusive (16 bit) S * S * @param *addr address pointer S * @return value of (*address) S * S * Exclusive LDR command for 16 bit values S */ Sextern uint16_t __LDREXH(uint16_t *addr); S S/** S * @brief LDR Exclusive (32 bit) S * S * @param *addr address pointer S * @return value of (*address) S * S * Exclusive LDR command for 32 bit values S */ Sextern uint32_t __LDREXW(uint32_t *addr); S S/** S * @brief STR Exclusive (8 bit) S * S * @param value value to store S * @param *addr address pointer S * @return successful / failed S * S * Exclusive STR command for 8 bit values S */ Sextern uint32_t __STREXB(uint8_t value, uint8_t *addr); S S/** S * @brief STR Exclusive (16 bit) S * S * @param value value to store S * @param *addr address pointer S * @return successful / failed S * S * Exclusive STR command for 16 bit values S */ Sextern uint32_t __STREXH(uint16_t value, uint16_t *addr); S S/** S * @brief STR Exclusive (32 bit) S * S * @param value value to store S * @param *addr address pointer S * @return successful / failed S * S * Exclusive STR command for 32 bit values S */ Sextern uint32_t __STREXW(uint32_t value, uint32_t *addr); S S S#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ S/* TASKING carm specific functions */ S S/* S * The CMSIS functions have been implemented as intrinsics in the compiler. S * Please use "carm -?i" to get an up to date list of all instrinsics, S * Including the CMSIS ones. S */ S N#endif N N N/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface N Core Function Interface containing: N - Core NVIC Functions N - Core SysTick Functions N - Core Reset Functions N*/ N/*@{*/ N N/* ########################## NVIC functions #################################### */ N N/** N * @brief Set the Priority Grouping in NVIC Interrupt Controller N * N * @param PriorityGroup is priority grouping field N * N * Set the priority grouping field using the required unlock sequence. N * The parameter priority_grouping is assigned to the field N * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. N * In case of a conflict between priority grouping and available N * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. N */ Nstatic __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) Xstatic __inline void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) N{ N uint32_t reg_value; N uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ N N reg_value = SCB->AIRCR; /* read old register configuration */ X reg_value = ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR; N reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ X reg_value &= ~((0xFFFFul << 16) | (7ul << 8)); N reg_value = (reg_value | N (0x5FA << SCB_AIRCR_VECTKEY_Pos) | X (0x5FA << 16) | N (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ N SCB->AIRCR = reg_value; X ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR = reg_value; N} N N/** N * @brief Get the Priority Grouping from NVIC Interrupt Controller N * N * @return priority grouping field N * N * Get the priority grouping from NVIC Interrupt Controller. N * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. N */ Nstatic __INLINE uint32_t NVIC_GetPriorityGrouping(void) Xstatic __inline uint32_t NVIC_GetPriorityGrouping(void) N{ N return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ X return ((((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR & (7ul << 8)) >> 8); N} N N/** N * @brief Enable Interrupt in NVIC Interrupt Controller N * N * @param IRQn The positive number of the external interrupt to enable N * N * Enable a device specific interupt in the NVIC interrupt controller. N * The interrupt number cannot be a negative value. N */ Nstatic __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) Xstatic __inline void NVIC_EnableIRQ(IRQn_Type IRQn) N{ N NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); N} N N/** N * @brief Disable the interrupt line for external interrupt specified N * N * @param IRQn The positive number of the external interrupt to disable N * N * Disable a device specific interupt in the NVIC interrupt controller. N * The interrupt number cannot be a negative value. N */ Nstatic __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) Xstatic __inline void NVIC_DisableIRQ(IRQn_Type IRQn) N{ N NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); N} N N/** N * @brief Read the interrupt pending bit for a device specific interrupt source N * N * @param IRQn The number of the device specifc interrupt N * @return 1 = interrupt pending, 0 = interrupt not pending N * N * Read the pending register in NVIC and return 1 if its status is pending, N * otherwise it returns 0 N */ Nstatic __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) Xstatic __inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) N{ N return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ X return((uint32_t) ((((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); N} N N/** N * @brief Set the pending bit for an external interrupt N * N * @param IRQn The number of the interrupt for set pending N * N * Set the pending bit for the specified interrupt. N * The interrupt number cannot be a negative value. N */ Nstatic __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) Xstatic __inline void NVIC_SetPendingIRQ(IRQn_Type IRQn) N{ N NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); N} N N/** N * @brief Clear the pending bit for an external interrupt N * N * @param IRQn The number of the interrupt for clear pending N * N * Clear the pending bit for the specified interrupt. N * The interrupt number cannot be a negative value. N */ Nstatic __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) Xstatic __inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn) N{ N NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); N} N N/** N * @brief Read the active bit for an external interrupt N * N * @param IRQn The number of the interrupt for read active bit N * @return 1 = interrupt active, 0 = interrupt not active N * N * Read the active register in NVIC and returns 1 if its status is active, N * otherwise it returns 0. N */ Nstatic __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) Xstatic __inline uint32_t NVIC_GetActive(IRQn_Type IRQn) N{ N return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ X return((uint32_t)((((NVIC_Type *) ((0xE000E000) + 0x0100))->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); N} N N/** N * @brief Set the priority for an interrupt N * N * @param IRQn The number of the interrupt for set priority N * @param priority The priority to set N * N * Set the priority for the specified interrupt. The interrupt N * number can be positive to specify an external (device specific) N * interrupt, or negative to specify an internal (core) interrupt. N * N * Note: The priority cannot be set for every core interrupt. N */ Nstatic __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) Xstatic __inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) N{ N if(IRQn < 0) { N SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ X ((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - 4)) & 0xff); } N else { N NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ X ((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)] = ((priority << (8 - 4)) & 0xff); } N} N N/** N * @brief Read the priority for an interrupt N * N * @param IRQn The number of the interrupt for get priority N * @return The priority for the interrupt N * N * Read the priority for the specified interrupt. The interrupt N * number can be positive to specify an external (device specific) N * interrupt, or negative to specify an internal (core) interrupt. N * N * The returned priority value is automatically aligned to the implemented N * priority bits of the microcontroller. N * N * Note: The priority cannot be set for every core interrupt. N */ Nstatic __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) Xstatic __inline uint32_t NVIC_GetPriority(IRQn_Type IRQn) N{ N N if(IRQn < 0) { N return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ X return((uint32_t)(((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - 4))); } N else { N return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ X return((uint32_t)(((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)] >> (8 - 4))); } N} N N N/** N * @brief Encode the priority for an interrupt N * N * @param PriorityGroup The used priority group N * @param PreemptPriority The preemptive priority value (starting from 0) N * @param SubPriority The sub priority value (starting from 0) N * @return The encoded priority for the interrupt N * N * Encode the priority for an interrupt with the given priority group, N * preemptive priority value and sub priority value. N * In case of a conflict between priority grouping and available N * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. N * N * The returned priority value can be used for NVIC_SetPriority(...) function N */ Nstatic __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) N{ N uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ N uint32_t PreemptPriorityBits; N uint32_t SubPriorityBits; N N PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; X PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp; N SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; X SubPriorityBits = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4; N N return ( N ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | N ((SubPriority & ((1 << (SubPriorityBits )) - 1))) N ); N} N N N/** N * @brief Decode the priority of an interrupt N * N * @param Priority The priority for the interrupt N * @param PriorityGroup The used priority group N * @param pPreemptPriority The preemptive priority value (starting from 0) N * @param pSubPriority The sub priority value (starting from 0) N * N * Decode an interrupt priority value with the given priority group to N * preemptive priority value and sub priority value. N * In case of a conflict between priority grouping and available N * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. N * N * The priority value can be retrieved with NVIC_GetPriority(...) function N */ Nstatic __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) N{ N uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ N uint32_t PreemptPriorityBits; N uint32_t SubPriorityBits; N N PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; X PreemptPriorityBits = ((7 - PriorityGroupTmp) > 4) ? 4 : 7 - PriorityGroupTmp; N SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; X SubPriorityBits = ((PriorityGroupTmp + 4) < 7) ? 0 : PriorityGroupTmp - 7 + 4; N N *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); N *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); N} N N N N/* ################################## SysTick function ############################################ */ N N#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) X#if (!1L) || (0 == 0) N N/** N * @brief Initialize and start the SysTick counter and its interrupt. N * N * @param ticks number of ticks between two interrupts N * @return 1 = failed, 0 = successful N * N * Initialise the system tick timer and its interrupt and start the N * system tick timer / counter in free running mode to generate N * periodical interrupts. N */ Nstatic __INLINE uint32_t SysTick_Config(uint32_t ticks) Xstatic __inline uint32_t SysTick_Config(uint32_t ticks) N{ N if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ X if (ticks > (0xFFFFFFul << 0)) return (1); N N SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ X ((SysTick_Type *) ((0xE000E000) + 0x0010))->LOAD = (ticks & (0xFFFFFFul << 0)) - 1; N NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ X NVIC_SetPriority (SysTick_IRQn, (1<<4) - 1); N SysTick->VAL = 0; /* Load the SysTick Counter Value */ X ((SysTick_Type *) ((0xE000E000) + 0x0010))->VAL = 0; N SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | X ((SysTick_Type *) ((0xE000E000) + 0x0010))->CTRL = (1ul << 2) | N SysTick_CTRL_TICKINT_Msk | X (1ul << 1) | N SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ X (1ul << 0); N return (0); /* Function successful */ N} N N#endif N N N N N/* ################################## Reset function ############################################ */ N N/** N * @brief Initiate a system reset request. N * N * Initiate a system reset request to reset the MCU N */ Nstatic __INLINE void NVIC_SystemReset(void) Xstatic __inline void NVIC_SystemReset(void) N{ N SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | X ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR = ((0x5FA << 16) | N (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | X (((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR & (7ul << 8)) | N SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ X (1ul << 2)); N __DSB(); /* Ensure completion of memory access */ X __dsb(0); N while(1); /* wait until reset */ N} N N/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ N N N N/* ##################################### Debug In/Output function ########################################### */ N N/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface N Core Debug Interface containing: N - Core Debug Receive / Transmit Functions N - Core Debug Defines N - Core Debug Variables N*/ N/*@{*/ N Nextern volatile int ITM_RxBuffer; /*!< variable to receive characters */ N#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ N N N/** N * @brief Outputs a character via the ITM channel 0 N * N * @param ch character to output N * @return character to output N * N * The function outputs a character via the ITM channel 0. N * The function returns when no debugger is connected that has booked the output. N * It is blocking when a debugger is connected, but the previous character send is not transmitted. N */ Nstatic __INLINE uint32_t ITM_SendChar (uint32_t ch) Xstatic __inline uint32_t ITM_SendChar (uint32_t ch) N{ N if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ X if ((((CoreDebug_Type *) (0xE000EDF0))->DEMCR & (1ul << 24)) && N (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ X (((ITM_Type *) (0xE0000000))->TCR & (1ul << 0)) && N (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ X (((ITM_Type *) (0xE0000000))->TER & (1ul << 0) ) ) N { N while (ITM->PORT[0].u32 == 0); X while (((ITM_Type *) (0xE0000000))->PORT[0].u32 == 0); N ITM->PORT[0].u8 = (uint8_t) ch; X ((ITM_Type *) (0xE0000000))->PORT[0].u8 = (uint8_t) ch; N } N return (ch); N} N N N/** N * @brief Inputs a character via variable ITM_RxBuffer N * N * @return received character, -1 = no character received N * N * The function inputs a character via variable ITM_RxBuffer. N * The function returns when no debugger is connected that has booked the output. N * It is blocking when a debugger is connected, but the previous character send is not transmitted. N */ Nstatic __INLINE int ITM_ReceiveChar (void) { Xstatic __inline int ITM_ReceiveChar (void) { N int ch = -1; /* no character available */ N N if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { X if (ITM_RxBuffer != 0x5AA55AA5) { N ch = ITM_RxBuffer; N ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ X ITM_RxBuffer = 0x5AA55AA5; N } N N return (ch); N} N N N/** N * @brief Check if a character via variable ITM_RxBuffer is available N * N * @return 1 = character available, 0 = no character available N * N * The function checks variable ITM_RxBuffer whether a character is available or not. N * The function returns '1' if a character is available and '0' if no character is available. N */ Nstatic __INLINE int ITM_CheckChar (void) { Xstatic __inline int ITM_CheckChar (void) { N N if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { X if (ITM_RxBuffer == 0x5AA55AA5) { N return (0); /* no character available */ N } else { N return (1); /* character available */ N } N} N N/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ N N N#ifdef __cplusplus S} N#endif N N/*@}*/ /* end of group CMSIS_CM3_core_definitions */ N N#endif /* __CM3_CORE_H__ */ N N/*lint -restore */ L 479 "..\..\template\Libraries\CMSIS\stm32f10x.h" 2 N#include "system_stm32f10x.h" L 1 "..\..\template\Libraries\CMSIS\system_stm32f10x.h" 1 N/** N ****************************************************************************** N * @file system_stm32f10x.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/** @addtogroup CMSIS N * @{ N */ N N/** @addtogroup stm32f10x_system N * @{ N */ N N/** N * @brief Define to prevent recursive inclusion N */ N#ifndef __SYSTEM_STM32F10X_H N#define __SYSTEM_STM32F10X_H N N#ifdef __cplusplus S extern "C" { N#endif N N/** @addtogroup STM32F10x_System_Includes N * @{ N */ N N/** N * @} N */ N N N/** @addtogroup STM32F10x_System_Exported_types N * @{ N */ N Nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ N N/** N * @} N */ N N/** @addtogroup STM32F10x_System_Exported_Constants N * @{ N */ N N/** N * @} N */ N N/** @addtogroup STM32F10x_System_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @addtogroup STM32F10x_System_Exported_Functions N * @{ N */ N Nextern void SystemInit(void); Nextern void SystemCoreClockUpdate(void); N/** N * @} N */ N N#ifdef __cplusplus S} N#endif N N#endif /*__SYSTEM_STM32F10X_H */ N N/** N * @} N */ N N/** N * @} N */ N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 480 "..\..\template\Libraries\CMSIS\stm32f10x.h" 2 N#include N N/** @addtogroup Exported_types N * @{ N */ N N/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ Ntypedef int32_t s32; Ntypedef int16_t s16; Ntypedef int8_t s8; N Ntypedef const int32_t sc32; /*!< Read Only */ Ntypedef const int16_t sc16; /*!< Read Only */ Ntypedef const int8_t sc8; /*!< Read Only */ N Ntypedef __IO int32_t vs32; Xtypedef volatile int32_t vs32; Ntypedef __IO int16_t vs16; Xtypedef volatile int16_t vs16; Ntypedef __IO int8_t vs8; Xtypedef volatile int8_t vs8; N Ntypedef __I int32_t vsc32; /*!< Read Only */ Xtypedef volatile const int32_t vsc32; Ntypedef __I int16_t vsc16; /*!< Read Only */ Xtypedef volatile const int16_t vsc16; Ntypedef __I int8_t vsc8; /*!< Read Only */ Xtypedef volatile const int8_t vsc8; N Ntypedef uint32_t u32; Ntypedef uint16_t u16; Ntypedef uint8_t u8; N Ntypedef const uint32_t uc32; /*!< Read Only */ Ntypedef const uint16_t uc16; /*!< Read Only */ Ntypedef const uint8_t uc8; /*!< Read Only */ N Ntypedef __IO uint32_t vu32; Xtypedef volatile uint32_t vu32; Ntypedef __IO uint16_t vu16; Xtypedef volatile uint16_t vu16; Ntypedef __IO uint8_t vu8; Xtypedef volatile uint8_t vu8; N Ntypedef __I uint32_t vuc32; /*!< Read Only */ Xtypedef volatile const uint32_t vuc32; Ntypedef __I uint16_t vuc16; /*!< Read Only */ Xtypedef volatile const uint16_t vuc16; Ntypedef __I uint8_t vuc8; /*!< Read Only */ Xtypedef volatile const uint8_t vuc8; N Ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; N Ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; N#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) N Ntypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; N N/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ N#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT N#define HSE_Value HSE_VALUE N#define HSI_Value HSI_VALUE N/** N * @} N */ N N/** @addtogroup Peripheral_registers_structures N * @{ N */ N N/** N * @brief Analog to Digital Converter N */ N Ntypedef struct N{ N __IO uint32_t SR; X volatile uint32_t SR; N __IO uint32_t CR1; X volatile uint32_t CR1; N __IO uint32_t CR2; X volatile uint32_t CR2; N __IO uint32_t SMPR1; X volatile uint32_t SMPR1; N __IO uint32_t SMPR2; X volatile uint32_t SMPR2; N __IO uint32_t JOFR1; X volatile uint32_t JOFR1; N __IO uint32_t JOFR2; X volatile uint32_t JOFR2; N __IO uint32_t JOFR3; X volatile uint32_t JOFR3; N __IO uint32_t JOFR4; X volatile uint32_t JOFR4; N __IO uint32_t HTR; X volatile uint32_t HTR; N __IO uint32_t LTR; X volatile uint32_t LTR; N __IO uint32_t SQR1; X volatile uint32_t SQR1; N __IO uint32_t SQR2; X volatile uint32_t SQR2; N __IO uint32_t SQR3; X volatile uint32_t SQR3; N __IO uint32_t JSQR; X volatile uint32_t JSQR; N __IO uint32_t JDR1; X volatile uint32_t JDR1; N __IO uint32_t JDR2; X volatile uint32_t JDR2; N __IO uint32_t JDR3; X volatile uint32_t JDR3; N __IO uint32_t JDR4; X volatile uint32_t JDR4; N __IO uint32_t DR; X volatile uint32_t DR; N} ADC_TypeDef; N N/** N * @brief Backup Registers N */ N Ntypedef struct N{ N uint32_t RESERVED0; N __IO uint16_t DR1; X volatile uint16_t DR1; N uint16_t RESERVED1; N __IO uint16_t DR2; X volatile uint16_t DR2; N uint16_t RESERVED2; N __IO uint16_t DR3; X volatile uint16_t DR3; N uint16_t RESERVED3; N __IO uint16_t DR4; X volatile uint16_t DR4; N uint16_t RESERVED4; N __IO uint16_t DR5; X volatile uint16_t DR5; N uint16_t RESERVED5; N __IO uint16_t DR6; X volatile uint16_t DR6; N uint16_t RESERVED6; N __IO uint16_t DR7; X volatile uint16_t DR7; N uint16_t RESERVED7; N __IO uint16_t DR8; X volatile uint16_t DR8; N uint16_t RESERVED8; N __IO uint16_t DR9; X volatile uint16_t DR9; N uint16_t RESERVED9; N __IO uint16_t DR10; X volatile uint16_t DR10; N uint16_t RESERVED10; N __IO uint16_t RTCCR; X volatile uint16_t RTCCR; N uint16_t RESERVED11; N __IO uint16_t CR; X volatile uint16_t CR; N uint16_t RESERVED12; N __IO uint16_t CSR; X volatile uint16_t CSR; N uint16_t RESERVED13[5]; N __IO uint16_t DR11; X volatile uint16_t DR11; N uint16_t RESERVED14; N __IO uint16_t DR12; X volatile uint16_t DR12; N uint16_t RESERVED15; N __IO uint16_t DR13; X volatile uint16_t DR13; N uint16_t RESERVED16; N __IO uint16_t DR14; X volatile uint16_t DR14; N uint16_t RESERVED17; N __IO uint16_t DR15; X volatile uint16_t DR15; N uint16_t RESERVED18; N __IO uint16_t DR16; X volatile uint16_t DR16; N uint16_t RESERVED19; N __IO uint16_t DR17; X volatile uint16_t DR17; N uint16_t RESERVED20; N __IO uint16_t DR18; X volatile uint16_t DR18; N uint16_t RESERVED21; N __IO uint16_t DR19; X volatile uint16_t DR19; N uint16_t RESERVED22; N __IO uint16_t DR20; X volatile uint16_t DR20; N uint16_t RESERVED23; N __IO uint16_t DR21; X volatile uint16_t DR21; N uint16_t RESERVED24; N __IO uint16_t DR22; X volatile uint16_t DR22; N uint16_t RESERVED25; N __IO uint16_t DR23; X volatile uint16_t DR23; N uint16_t RESERVED26; N __IO uint16_t DR24; X volatile uint16_t DR24; N uint16_t RESERVED27; N __IO uint16_t DR25; X volatile uint16_t DR25; N uint16_t RESERVED28; N __IO uint16_t DR26; X volatile uint16_t DR26; N uint16_t RESERVED29; N __IO uint16_t DR27; X volatile uint16_t DR27; N uint16_t RESERVED30; N __IO uint16_t DR28; X volatile uint16_t DR28; N uint16_t RESERVED31; N __IO uint16_t DR29; X volatile uint16_t DR29; N uint16_t RESERVED32; N __IO uint16_t DR30; X volatile uint16_t DR30; N uint16_t RESERVED33; N __IO uint16_t DR31; X volatile uint16_t DR31; N uint16_t RESERVED34; N __IO uint16_t DR32; X volatile uint16_t DR32; N uint16_t RESERVED35; N __IO uint16_t DR33; X volatile uint16_t DR33; N uint16_t RESERVED36; N __IO uint16_t DR34; X volatile uint16_t DR34; N uint16_t RESERVED37; N __IO uint16_t DR35; X volatile uint16_t DR35; N uint16_t RESERVED38; N __IO uint16_t DR36; X volatile uint16_t DR36; N uint16_t RESERVED39; N __IO uint16_t DR37; X volatile uint16_t DR37; N uint16_t RESERVED40; N __IO uint16_t DR38; X volatile uint16_t DR38; N uint16_t RESERVED41; N __IO uint16_t DR39; X volatile uint16_t DR39; N uint16_t RESERVED42; N __IO uint16_t DR40; X volatile uint16_t DR40; N uint16_t RESERVED43; N __IO uint16_t DR41; X volatile uint16_t DR41; N uint16_t RESERVED44; N __IO uint16_t DR42; X volatile uint16_t DR42; N uint16_t RESERVED45; N} BKP_TypeDef; N N/** N * @brief Controller Area Network TxMailBox N */ N Ntypedef struct N{ N __IO uint32_t TIR; X volatile uint32_t TIR; N __IO uint32_t TDTR; X volatile uint32_t TDTR; N __IO uint32_t TDLR; X volatile uint32_t TDLR; N __IO uint32_t TDHR; X volatile uint32_t TDHR; N} CAN_TxMailBox_TypeDef; N N/** N * @brief Controller Area Network FIFOMailBox N */ N Ntypedef struct N{ N __IO uint32_t RIR; X volatile uint32_t RIR; N __IO uint32_t RDTR; X volatile uint32_t RDTR; N __IO uint32_t RDLR; X volatile uint32_t RDLR; N __IO uint32_t RDHR; X volatile uint32_t RDHR; N} CAN_FIFOMailBox_TypeDef; N N/** N * @brief Controller Area Network FilterRegister N */ N Ntypedef struct N{ N __IO uint32_t FR1; X volatile uint32_t FR1; N __IO uint32_t FR2; X volatile uint32_t FR2; N} CAN_FilterRegister_TypeDef; N N/** N * @brief Controller Area Network N */ N Ntypedef struct N{ N __IO uint32_t MCR; X volatile uint32_t MCR; N __IO uint32_t MSR; X volatile uint32_t MSR; N __IO uint32_t TSR; X volatile uint32_t TSR; N __IO uint32_t RF0R; X volatile uint32_t RF0R; N __IO uint32_t RF1R; X volatile uint32_t RF1R; N __IO uint32_t IER; X volatile uint32_t IER; N __IO uint32_t ESR; X volatile uint32_t ESR; N __IO uint32_t BTR; X volatile uint32_t BTR; N uint32_t RESERVED0[88]; N CAN_TxMailBox_TypeDef sTxMailBox[3]; N CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; N uint32_t RESERVED1[12]; N __IO uint32_t FMR; X volatile uint32_t FMR; N __IO uint32_t FM1R; X volatile uint32_t FM1R; N uint32_t RESERVED2; N __IO uint32_t FS1R; X volatile uint32_t FS1R; N uint32_t RESERVED3; N __IO uint32_t FFA1R; X volatile uint32_t FFA1R; N uint32_t RESERVED4; N __IO uint32_t FA1R; X volatile uint32_t FA1R; N uint32_t RESERVED5[8]; N#ifndef STM32F10X_CL N CAN_FilterRegister_TypeDef sFilterRegister[14]; N#else S CAN_FilterRegister_TypeDef sFilterRegister[28]; N#endif /* STM32F10X_CL */ N} CAN_TypeDef; N N/** N * @brief Consumer Electronics Control (CEC) N */ Ntypedef struct N{ N __IO uint32_t CFGR; X volatile uint32_t CFGR; N __IO uint32_t OAR; X volatile uint32_t OAR; N __IO uint32_t PRES; X volatile uint32_t PRES; N __IO uint32_t ESR; X volatile uint32_t ESR; N __IO uint32_t CSR; X volatile uint32_t CSR; N __IO uint32_t TXD; X volatile uint32_t TXD; N __IO uint32_t RXD; X volatile uint32_t RXD; N} CEC_TypeDef; N N/** N * @brief CRC calculation unit N */ N Ntypedef struct N{ N __IO uint32_t DR; X volatile uint32_t DR; N __IO uint8_t IDR; X volatile uint8_t IDR; N uint8_t RESERVED0; N uint16_t RESERVED1; N __IO uint32_t CR; X volatile uint32_t CR; N} CRC_TypeDef; N N/** N * @brief Digital to Analog Converter N */ N Ntypedef struct N{ N __IO uint32_t CR; X volatile uint32_t CR; N __IO uint32_t SWTRIGR; X volatile uint32_t SWTRIGR; N __IO uint32_t DHR12R1; X volatile uint32_t DHR12R1; N __IO uint32_t DHR12L1; X volatile uint32_t DHR12L1; N __IO uint32_t DHR8R1; X volatile uint32_t DHR8R1; N __IO uint32_t DHR12R2; X volatile uint32_t DHR12R2; N __IO uint32_t DHR12L2; X volatile uint32_t DHR12L2; N __IO uint32_t DHR8R2; X volatile uint32_t DHR8R2; N __IO uint32_t DHR12RD; X volatile uint32_t DHR12RD; N __IO uint32_t DHR12LD; X volatile uint32_t DHR12LD; N __IO uint32_t DHR8RD; X volatile uint32_t DHR8RD; N __IO uint32_t DOR1; X volatile uint32_t DOR1; N __IO uint32_t DOR2; X volatile uint32_t DOR2; N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S __IO uint32_t SR; N#endif N} DAC_TypeDef; N N/** N * @brief Debug MCU N */ N Ntypedef struct N{ N __IO uint32_t IDCODE; X volatile uint32_t IDCODE; N __IO uint32_t CR; X volatile uint32_t CR; N}DBGMCU_TypeDef; N N/** N * @brief DMA Controller N */ N Ntypedef struct N{ N __IO uint32_t CCR; X volatile uint32_t CCR; N __IO uint32_t CNDTR; X volatile uint32_t CNDTR; N __IO uint32_t CPAR; X volatile uint32_t CPAR; N __IO uint32_t CMAR; X volatile uint32_t CMAR; N} DMA_Channel_TypeDef; N Ntypedef struct N{ N __IO uint32_t ISR; X volatile uint32_t ISR; N __IO uint32_t IFCR; X volatile uint32_t IFCR; N} DMA_TypeDef; N N/** N * @brief Ethernet MAC N */ N Ntypedef struct N{ N __IO uint32_t MACCR; X volatile uint32_t MACCR; N __IO uint32_t MACFFR; X volatile uint32_t MACFFR; N __IO uint32_t MACHTHR; X volatile uint32_t MACHTHR; N __IO uint32_t MACHTLR; X volatile uint32_t MACHTLR; N __IO uint32_t MACMIIAR; X volatile uint32_t MACMIIAR; N __IO uint32_t MACMIIDR; X volatile uint32_t MACMIIDR; N __IO uint32_t MACFCR; X volatile uint32_t MACFCR; N __IO uint32_t MACVLANTR; /* 8 */ X volatile uint32_t MACVLANTR; N uint32_t RESERVED0[2]; N __IO uint32_t MACRWUFFR; /* 11 */ X volatile uint32_t MACRWUFFR; N __IO uint32_t MACPMTCSR; X volatile uint32_t MACPMTCSR; N uint32_t RESERVED1[2]; N __IO uint32_t MACSR; /* 15 */ X volatile uint32_t MACSR; N __IO uint32_t MACIMR; X volatile uint32_t MACIMR; N __IO uint32_t MACA0HR; X volatile uint32_t MACA0HR; N __IO uint32_t MACA0LR; X volatile uint32_t MACA0LR; N __IO uint32_t MACA1HR; X volatile uint32_t MACA1HR; N __IO uint32_t MACA1LR; X volatile uint32_t MACA1LR; N __IO uint32_t MACA2HR; X volatile uint32_t MACA2HR; N __IO uint32_t MACA2LR; X volatile uint32_t MACA2LR; N __IO uint32_t MACA3HR; X volatile uint32_t MACA3HR; N __IO uint32_t MACA3LR; /* 24 */ X volatile uint32_t MACA3LR; N uint32_t RESERVED2[40]; N __IO uint32_t MMCCR; /* 65 */ X volatile uint32_t MMCCR; N __IO uint32_t MMCRIR; X volatile uint32_t MMCRIR; N __IO uint32_t MMCTIR; X volatile uint32_t MMCTIR; N __IO uint32_t MMCRIMR; X volatile uint32_t MMCRIMR; N __IO uint32_t MMCTIMR; /* 69 */ X volatile uint32_t MMCTIMR; N uint32_t RESERVED3[14]; N __IO uint32_t MMCTGFSCCR; /* 84 */ X volatile uint32_t MMCTGFSCCR; N __IO uint32_t MMCTGFMSCCR; X volatile uint32_t MMCTGFMSCCR; N uint32_t RESERVED4[5]; N __IO uint32_t MMCTGFCR; X volatile uint32_t MMCTGFCR; N uint32_t RESERVED5[10]; N __IO uint32_t MMCRFCECR; X volatile uint32_t MMCRFCECR; N __IO uint32_t MMCRFAECR; X volatile uint32_t MMCRFAECR; N uint32_t RESERVED6[10]; N __IO uint32_t MMCRGUFCR; X volatile uint32_t MMCRGUFCR; N uint32_t RESERVED7[334]; N __IO uint32_t PTPTSCR; X volatile uint32_t PTPTSCR; N __IO uint32_t PTPSSIR; X volatile uint32_t PTPSSIR; N __IO uint32_t PTPTSHR; X volatile uint32_t PTPTSHR; N __IO uint32_t PTPTSLR; X volatile uint32_t PTPTSLR; N __IO uint32_t PTPTSHUR; X volatile uint32_t PTPTSHUR; N __IO uint32_t PTPTSLUR; X volatile uint32_t PTPTSLUR; N __IO uint32_t PTPTSAR; X volatile uint32_t PTPTSAR; N __IO uint32_t PTPTTHR; X volatile uint32_t PTPTTHR; N __IO uint32_t PTPTTLR; X volatile uint32_t PTPTTLR; N uint32_t RESERVED8[567]; N __IO uint32_t DMABMR; X volatile uint32_t DMABMR; N __IO uint32_t DMATPDR; X volatile uint32_t DMATPDR; N __IO uint32_t DMARPDR; X volatile uint32_t DMARPDR; N __IO uint32_t DMARDLAR; X volatile uint32_t DMARDLAR; N __IO uint32_t DMATDLAR; X volatile uint32_t DMATDLAR; N __IO uint32_t DMASR; X volatile uint32_t DMASR; N __IO uint32_t DMAOMR; X volatile uint32_t DMAOMR; N __IO uint32_t DMAIER; X volatile uint32_t DMAIER; N __IO uint32_t DMAMFBOCR; X volatile uint32_t DMAMFBOCR; N uint32_t RESERVED9[9]; N __IO uint32_t DMACHTDR; X volatile uint32_t DMACHTDR; N __IO uint32_t DMACHRDR; X volatile uint32_t DMACHRDR; N __IO uint32_t DMACHTBAR; X volatile uint32_t DMACHTBAR; N __IO uint32_t DMACHRBAR; X volatile uint32_t DMACHRBAR; N} ETH_TypeDef; N N/** N * @brief External Interrupt/Event Controller N */ N Ntypedef struct N{ N __IO uint32_t IMR; X volatile uint32_t IMR; N __IO uint32_t EMR; X volatile uint32_t EMR; N __IO uint32_t RTSR; X volatile uint32_t RTSR; N __IO uint32_t FTSR; X volatile uint32_t FTSR; N __IO uint32_t SWIER; X volatile uint32_t SWIER; N __IO uint32_t PR; X volatile uint32_t PR; N} EXTI_TypeDef; N N/** N * @brief FLASH Registers N */ N Ntypedef struct N{ N __IO uint32_t ACR; X volatile uint32_t ACR; N __IO uint32_t KEYR; X volatile uint32_t KEYR; N __IO uint32_t OPTKEYR; X volatile uint32_t OPTKEYR; N __IO uint32_t SR; X volatile uint32_t SR; N __IO uint32_t CR; X volatile uint32_t CR; N __IO uint32_t AR; X volatile uint32_t AR; N __IO uint32_t RESERVED; X volatile uint32_t RESERVED; N __IO uint32_t OBR; X volatile uint32_t OBR; N __IO uint32_t WRPR; X volatile uint32_t WRPR; N#ifdef STM32F10X_XL S uint32_t RESERVED1[8]; S __IO uint32_t KEYR2; S uint32_t RESERVED2; S __IO uint32_t SR2; S __IO uint32_t CR2; S __IO uint32_t AR2; N#endif /* STM32F10X_XL */ N} FLASH_TypeDef; N N/** N * @brief Option Bytes Registers N */ N Ntypedef struct N{ N __IO uint16_t RDP; X volatile uint16_t RDP; N __IO uint16_t USER; X volatile uint16_t USER; N __IO uint16_t Data0; X volatile uint16_t Data0; N __IO uint16_t Data1; X volatile uint16_t Data1; N __IO uint16_t WRP0; X volatile uint16_t WRP0; N __IO uint16_t WRP1; X volatile uint16_t WRP1; N __IO uint16_t WRP2; X volatile uint16_t WRP2; N __IO uint16_t WRP3; X volatile uint16_t WRP3; N} OB_TypeDef; N N/** N * @brief Flexible Static Memory Controller N */ N Ntypedef struct N{ N __IO uint32_t BTCR[8]; X volatile uint32_t BTCR[8]; N} FSMC_Bank1_TypeDef; N N/** N * @brief Flexible Static Memory Controller Bank1E N */ N Ntypedef struct N{ N __IO uint32_t BWTR[7]; X volatile uint32_t BWTR[7]; N} FSMC_Bank1E_TypeDef; N N/** N * @brief Flexible Static Memory Controller Bank2 N */ N Ntypedef struct N{ N __IO uint32_t PCR2; X volatile uint32_t PCR2; N __IO uint32_t SR2; X volatile uint32_t SR2; N __IO uint32_t PMEM2; X volatile uint32_t PMEM2; N __IO uint32_t PATT2; X volatile uint32_t PATT2; N uint32_t RESERVED0; N __IO uint32_t ECCR2; X volatile uint32_t ECCR2; N} FSMC_Bank2_TypeDef; N N/** N * @brief Flexible Static Memory Controller Bank3 N */ N Ntypedef struct N{ N __IO uint32_t PCR3; X volatile uint32_t PCR3; N __IO uint32_t SR3; X volatile uint32_t SR3; N __IO uint32_t PMEM3; X volatile uint32_t PMEM3; N __IO uint32_t PATT3; X volatile uint32_t PATT3; N uint32_t RESERVED0; N __IO uint32_t ECCR3; X volatile uint32_t ECCR3; N} FSMC_Bank3_TypeDef; N N/** N * @brief Flexible Static Memory Controller Bank4 N */ N Ntypedef struct N{ N __IO uint32_t PCR4; X volatile uint32_t PCR4; N __IO uint32_t SR4; X volatile uint32_t SR4; N __IO uint32_t PMEM4; X volatile uint32_t PMEM4; N __IO uint32_t PATT4; X volatile uint32_t PATT4; N __IO uint32_t PIO4; X volatile uint32_t PIO4; N} FSMC_Bank4_TypeDef; N N/** N * @brief General Purpose I/O N */ N Ntypedef struct N{ N __IO uint32_t CRL; X volatile uint32_t CRL; N __IO uint32_t CRH; X volatile uint32_t CRH; N __IO uint32_t IDR; X volatile uint32_t IDR; N __IO uint32_t ODR; X volatile uint32_t ODR; N __IO uint32_t BSRR; X volatile uint32_t BSRR; N __IO uint32_t BRR; X volatile uint32_t BRR; N __IO uint32_t LCKR; X volatile uint32_t LCKR; N} GPIO_TypeDef; N N/** N * @brief Alternate Function I/O N */ N Ntypedef struct N{ N __IO uint32_t EVCR; X volatile uint32_t EVCR; N __IO uint32_t MAPR; X volatile uint32_t MAPR; N __IO uint32_t EXTICR[4]; X volatile uint32_t EXTICR[4]; N uint32_t RESERVED0; N __IO uint32_t MAPR2; X volatile uint32_t MAPR2; N} AFIO_TypeDef; N/** N * @brief Inter Integrated Circuit Interface N */ N Ntypedef struct N{ N __IO uint16_t CR1; X volatile uint16_t CR1; N uint16_t RESERVED0; N __IO uint16_t CR2; X volatile uint16_t CR2; N uint16_t RESERVED1; N __IO uint16_t OAR1; X volatile uint16_t OAR1; N uint16_t RESERVED2; N __IO uint16_t OAR2; X volatile uint16_t OAR2; N uint16_t RESERVED3; N __IO uint16_t DR; X volatile uint16_t DR; N uint16_t RESERVED4; N __IO uint16_t SR1; X volatile uint16_t SR1; N uint16_t RESERVED5; N __IO uint16_t SR2; X volatile uint16_t SR2; N uint16_t RESERVED6; N __IO uint16_t CCR; X volatile uint16_t CCR; N uint16_t RESERVED7; N __IO uint16_t TRISE; X volatile uint16_t TRISE; N uint16_t RESERVED8; N} I2C_TypeDef; N N/** N * @brief Independent WATCHDOG N */ N Ntypedef struct N{ N __IO uint32_t KR; X volatile uint32_t KR; N __IO uint32_t PR; X volatile uint32_t PR; N __IO uint32_t RLR; X volatile uint32_t RLR; N __IO uint32_t SR; X volatile uint32_t SR; N} IWDG_TypeDef; N N/** N * @brief Power Control N */ N Ntypedef struct N{ N __IO uint32_t CR; X volatile uint32_t CR; N __IO uint32_t CSR; X volatile uint32_t CSR; N} PWR_TypeDef; N N/** N * @brief Reset and Clock Control N */ N Ntypedef struct N{ N __IO uint32_t CR; X volatile uint32_t CR; N __IO uint32_t CFGR; X volatile uint32_t CFGR; N __IO uint32_t CIR; X volatile uint32_t CIR; N __IO uint32_t APB2RSTR; X volatile uint32_t APB2RSTR; N __IO uint32_t APB1RSTR; X volatile uint32_t APB1RSTR; N __IO uint32_t AHBENR; X volatile uint32_t AHBENR; N __IO uint32_t APB2ENR; X volatile uint32_t APB2ENR; N __IO uint32_t APB1ENR; X volatile uint32_t APB1ENR; N __IO uint32_t BDCR; X volatile uint32_t BDCR; N __IO uint32_t CSR; X volatile uint32_t CSR; N N#ifdef STM32F10X_CL S __IO uint32_t AHBRSTR; S __IO uint32_t CFGR2; N#endif /* STM32F10X_CL */ N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S uint32_t RESERVED0; S __IO uint32_t CFGR2; N#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ N} RCC_TypeDef; N N/** N * @brief Real-Time Clock N */ N Ntypedef struct N{ N __IO uint16_t CRH; X volatile uint16_t CRH; N uint16_t RESERVED0; N __IO uint16_t CRL; X volatile uint16_t CRL; N uint16_t RESERVED1; N __IO uint16_t PRLH; X volatile uint16_t PRLH; N uint16_t RESERVED2; N __IO uint16_t PRLL; X volatile uint16_t PRLL; N uint16_t RESERVED3; N __IO uint16_t DIVH; X volatile uint16_t DIVH; N uint16_t RESERVED4; N __IO uint16_t DIVL; X volatile uint16_t DIVL; N uint16_t RESERVED5; N __IO uint16_t CNTH; X volatile uint16_t CNTH; N uint16_t RESERVED6; N __IO uint16_t CNTL; X volatile uint16_t CNTL; N uint16_t RESERVED7; N __IO uint16_t ALRH; X volatile uint16_t ALRH; N uint16_t RESERVED8; N __IO uint16_t ALRL; X volatile uint16_t ALRL; N uint16_t RESERVED9; N} RTC_TypeDef; N N/** N * @brief SD host Interface N */ N Ntypedef struct N{ N __IO uint32_t POWER; X volatile uint32_t POWER; N __IO uint32_t CLKCR; X volatile uint32_t CLKCR; N __IO uint32_t ARG; X volatile uint32_t ARG; N __IO uint32_t CMD; X volatile uint32_t CMD; N __I uint32_t RESPCMD; X volatile const uint32_t RESPCMD; N __I uint32_t RESP1; X volatile const uint32_t RESP1; N __I uint32_t RESP2; X volatile const uint32_t RESP2; N __I uint32_t RESP3; X volatile const uint32_t RESP3; N __I uint32_t RESP4; X volatile const uint32_t RESP4; N __IO uint32_t DTIMER; X volatile uint32_t DTIMER; N __IO uint32_t DLEN; X volatile uint32_t DLEN; N __IO uint32_t DCTRL; X volatile uint32_t DCTRL; N __I uint32_t DCOUNT; X volatile const uint32_t DCOUNT; N __I uint32_t STA; X volatile const uint32_t STA; N __IO uint32_t ICR; X volatile uint32_t ICR; N __IO uint32_t MASK; X volatile uint32_t MASK; N uint32_t RESERVED0[2]; N __I uint32_t FIFOCNT; X volatile const uint32_t FIFOCNT; N uint32_t RESERVED1[13]; N __IO uint32_t FIFO; X volatile uint32_t FIFO; N} SDIO_TypeDef; N N/** N * @brief Serial Peripheral Interface N */ N Ntypedef struct N{ N __IO uint16_t CR1; X volatile uint16_t CR1; N uint16_t RESERVED0; N __IO uint16_t CR2; X volatile uint16_t CR2; N uint16_t RESERVED1; N __IO uint16_t SR; X volatile uint16_t SR; N uint16_t RESERVED2; N __IO uint16_t DR; X volatile uint16_t DR; N uint16_t RESERVED3; N __IO uint16_t CRCPR; X volatile uint16_t CRCPR; N uint16_t RESERVED4; N __IO uint16_t RXCRCR; X volatile uint16_t RXCRCR; N uint16_t RESERVED5; N __IO uint16_t TXCRCR; X volatile uint16_t TXCRCR; N uint16_t RESERVED6; N __IO uint16_t I2SCFGR; X volatile uint16_t I2SCFGR; N uint16_t RESERVED7; N __IO uint16_t I2SPR; X volatile uint16_t I2SPR; N uint16_t RESERVED8; N} SPI_TypeDef; N N/** N * @brief TIM N */ N Ntypedef struct N{ N __IO uint16_t CR1; X volatile uint16_t CR1; N uint16_t RESERVED0; N __IO uint16_t CR2; X volatile uint16_t CR2; N uint16_t RESERVED1; N __IO uint16_t SMCR; X volatile uint16_t SMCR; N uint16_t RESERVED2; N __IO uint16_t DIER; X volatile uint16_t DIER; N uint16_t RESERVED3; N __IO uint16_t SR; X volatile uint16_t SR; N uint16_t RESERVED4; N __IO uint16_t EGR; X volatile uint16_t EGR; N uint16_t RESERVED5; N __IO uint16_t CCMR1; X volatile uint16_t CCMR1; N uint16_t RESERVED6; N __IO uint16_t CCMR2; X volatile uint16_t CCMR2; N uint16_t RESERVED7; N __IO uint16_t CCER; X volatile uint16_t CCER; N uint16_t RESERVED8; N __IO uint16_t CNT; X volatile uint16_t CNT; N uint16_t RESERVED9; N __IO uint16_t PSC; X volatile uint16_t PSC; N uint16_t RESERVED10; N __IO uint16_t ARR; X volatile uint16_t ARR; N uint16_t RESERVED11; N __IO uint16_t RCR; X volatile uint16_t RCR; N uint16_t RESERVED12; N __IO uint16_t CCR1; X volatile uint16_t CCR1; N uint16_t RESERVED13; N __IO uint16_t CCR2; X volatile uint16_t CCR2; N uint16_t RESERVED14; N __IO uint16_t CCR3; X volatile uint16_t CCR3; N uint16_t RESERVED15; N __IO uint16_t CCR4; X volatile uint16_t CCR4; N uint16_t RESERVED16; N __IO uint16_t BDTR; X volatile uint16_t BDTR; N uint16_t RESERVED17; N __IO uint16_t DCR; X volatile uint16_t DCR; N uint16_t RESERVED18; N __IO uint16_t DMAR; X volatile uint16_t DMAR; N uint16_t RESERVED19; N} TIM_TypeDef; N N/** N * @brief Universal Synchronous Asynchronous Receiver Transmitter N */ N Ntypedef struct N{ N __IO uint16_t SR; X volatile uint16_t SR; N uint16_t RESERVED0; N __IO uint16_t DR; X volatile uint16_t DR; N uint16_t RESERVED1; N __IO uint16_t BRR; X volatile uint16_t BRR; N uint16_t RESERVED2; N __IO uint16_t CR1; X volatile uint16_t CR1; N uint16_t RESERVED3; N __IO uint16_t CR2; X volatile uint16_t CR2; N uint16_t RESERVED4; N __IO uint16_t CR3; X volatile uint16_t CR3; N uint16_t RESERVED5; N __IO uint16_t GTPR; X volatile uint16_t GTPR; N uint16_t RESERVED6; N} USART_TypeDef; N N/** N * @brief Window WATCHDOG N */ N Ntypedef struct N{ N __IO uint32_t CR; X volatile uint32_t CR; N __IO uint32_t CFR; X volatile uint32_t CFR; N __IO uint32_t SR; X volatile uint32_t SR; N} WWDG_TypeDef; N N/** N * @} N */ N N/** @addtogroup Peripheral_memory_map N * @{ N */ N N N#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ N#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ N#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ N N#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ N#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ N N#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ N N/*!< Peripheral memory map */ N#define APB1PERIPH_BASE PERIPH_BASE N#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) N#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) N N#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) N#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) N#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) N#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) N#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) N#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) N#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) N#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) N#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) N#define RTC_BASE (APB1PERIPH_BASE + 0x2800) N#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) N#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) N#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) N#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) N#define USART2_BASE (APB1PERIPH_BASE + 0x4400) N#define USART3_BASE (APB1PERIPH_BASE + 0x4800) N#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) N#define UART5_BASE (APB1PERIPH_BASE + 0x5000) N#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) N#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) N#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) N#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) N#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) N#define PWR_BASE (APB1PERIPH_BASE + 0x7000) N#define DAC_BASE (APB1PERIPH_BASE + 0x7400) N#define CEC_BASE (APB1PERIPH_BASE + 0x7800) N N#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) N#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) N#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) N#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) N#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) N#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) N#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) N#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) N#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) N#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) N#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) N#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) N#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) N#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) N#define USART1_BASE (APB2PERIPH_BASE + 0x3800) N#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) N#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) N#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) N#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) N#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) N#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) N#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) N N#define SDIO_BASE (PERIPH_BASE + 0x18000) N N#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) N#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) N#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) N#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) N#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) N#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) N#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) N#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) N#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) N#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) N#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) N#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) N#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) N#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) N#define RCC_BASE (AHBPERIPH_BASE + 0x1000) N#define CRC_BASE (AHBPERIPH_BASE + 0x3000) N N#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ N#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ N N#define ETH_BASE (AHBPERIPH_BASE + 0x8000) N#define ETH_MAC_BASE (ETH_BASE) N#define ETH_MMC_BASE (ETH_BASE + 0x0100) N#define ETH_PTP_BASE (ETH_BASE + 0x0700) N#define ETH_DMA_BASE (ETH_BASE + 0x1000) N N#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ N#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ N#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ N#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ N#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ N N#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ N N/** N * @} N */ N N/** @addtogroup Peripheral_declaration N * @{ N */ N N#define TIM2 ((TIM_TypeDef *) TIM2_BASE) N#define TIM3 ((TIM_TypeDef *) TIM3_BASE) N#define TIM4 ((TIM_TypeDef *) TIM4_BASE) N#define TIM5 ((TIM_TypeDef *) TIM5_BASE) N#define TIM6 ((TIM_TypeDef *) TIM6_BASE) N#define TIM7 ((TIM_TypeDef *) TIM7_BASE) N#define TIM12 ((TIM_TypeDef *) TIM12_BASE) N#define TIM13 ((TIM_TypeDef *) TIM13_BASE) N#define TIM14 ((TIM_TypeDef *) TIM14_BASE) N#define RTC ((RTC_TypeDef *) RTC_BASE) N#define WWDG ((WWDG_TypeDef *) WWDG_BASE) N#define IWDG ((IWDG_TypeDef *) IWDG_BASE) N#define SPI2 ((SPI_TypeDef *) SPI2_BASE) N#define SPI3 ((SPI_TypeDef *) SPI3_BASE) N#define USART2 ((USART_TypeDef *) USART2_BASE) N#define USART3 ((USART_TypeDef *) USART3_BASE) N#define UART4 ((USART_TypeDef *) UART4_BASE) N#define UART5 ((USART_TypeDef *) UART5_BASE) N#define I2C1 ((I2C_TypeDef *) I2C1_BASE) N#define I2C2 ((I2C_TypeDef *) I2C2_BASE) N#define CAN1 ((CAN_TypeDef *) CAN1_BASE) N#define CAN2 ((CAN_TypeDef *) CAN2_BASE) N#define BKP ((BKP_TypeDef *) BKP_BASE) N#define PWR ((PWR_TypeDef *) PWR_BASE) N#define DAC ((DAC_TypeDef *) DAC_BASE) N#define CEC ((CEC_TypeDef *) CEC_BASE) N#define AFIO ((AFIO_TypeDef *) AFIO_BASE) N#define EXTI ((EXTI_TypeDef *) EXTI_BASE) N#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) N#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) N#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) N#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) N#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) N#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) N#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) N#define ADC1 ((ADC_TypeDef *) ADC1_BASE) N#define ADC2 ((ADC_TypeDef *) ADC2_BASE) N#define TIM1 ((TIM_TypeDef *) TIM1_BASE) N#define SPI1 ((SPI_TypeDef *) SPI1_BASE) N#define TIM8 ((TIM_TypeDef *) TIM8_BASE) N#define USART1 ((USART_TypeDef *) USART1_BASE) N#define ADC3 ((ADC_TypeDef *) ADC3_BASE) N#define TIM15 ((TIM_TypeDef *) TIM15_BASE) N#define TIM16 ((TIM_TypeDef *) TIM16_BASE) N#define TIM17 ((TIM_TypeDef *) TIM17_BASE) N#define TIM9 ((TIM_TypeDef *) TIM9_BASE) N#define TIM10 ((TIM_TypeDef *) TIM10_BASE) N#define TIM11 ((TIM_TypeDef *) TIM11_BASE) N#define SDIO ((SDIO_TypeDef *) SDIO_BASE) N#define DMA1 ((DMA_TypeDef *) DMA1_BASE) N#define DMA2 ((DMA_TypeDef *) DMA2_BASE) N#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) N#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) N#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) N#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) N#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) N#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) N#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) N#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) N#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) N#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) N#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) N#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) N#define RCC ((RCC_TypeDef *) RCC_BASE) N#define CRC ((CRC_TypeDef *) CRC_BASE) N#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) N#define OB ((OB_TypeDef *) OB_BASE) N#define ETH ((ETH_TypeDef *) ETH_BASE) N#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) N#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) N#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) N#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) N#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) N#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) N N/** N * @} N */ N N/** @addtogroup Exported_constants N * @{ N */ N N /** @addtogroup Peripheral_Registers_Bits_Definition N * @{ N */ N N/******************************************************************************/ N/* Peripheral Registers_Bits_Definition */ N/******************************************************************************/ N N/******************************************************************************/ N/* */ N/* CRC calculation unit */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for CRC_DR register *********************/ N#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ N N N/******************* Bit definition for CRC_IDR register ********************/ N#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ N N N/******************** Bit definition for CRC_CR register ********************/ N#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ N N/******************************************************************************/ N/* */ N/* Power Control */ N/* */ N/******************************************************************************/ N N/******************** Bit definition for PWR_CR register ********************/ N#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ N#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ N#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ N#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ N#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ N N#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ N#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ N#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ N#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ N N/*!< PVD level configuration */ N#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ N#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ N#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ N#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ N#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ N#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ N#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ N#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ N N#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ N N N/******************* Bit definition for PWR_CSR register ********************/ N#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ N#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ N#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ N#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ N N/******************************************************************************/ N/* */ N/* Backup registers */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for BKP_DR1 register ********************/ N#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR2 register ********************/ N#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR3 register ********************/ N#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR4 register ********************/ N#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR5 register ********************/ N#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR6 register ********************/ N#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR7 register ********************/ N#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR8 register ********************/ N#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR9 register ********************/ N#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR10 register *******************/ N#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR11 register *******************/ N#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR12 register *******************/ N#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR13 register *******************/ N#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR14 register *******************/ N#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR15 register *******************/ N#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR16 register *******************/ N#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR17 register *******************/ N#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/****************** Bit definition for BKP_DR18 register ********************/ N#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR19 register *******************/ N#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR20 register *******************/ N#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR21 register *******************/ N#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR22 register *******************/ N#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR23 register *******************/ N#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR24 register *******************/ N#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR25 register *******************/ N#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR26 register *******************/ N#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR27 register *******************/ N#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR28 register *******************/ N#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR29 register *******************/ N#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR30 register *******************/ N#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR31 register *******************/ N#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR32 register *******************/ N#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR33 register *******************/ N#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR34 register *******************/ N#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR35 register *******************/ N#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR36 register *******************/ N#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR37 register *******************/ N#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR38 register *******************/ N#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR39 register *******************/ N#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR40 register *******************/ N#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR41 register *******************/ N#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/******************* Bit definition for BKP_DR42 register *******************/ N#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ N N/****************** Bit definition for BKP_RTCCR register *******************/ N#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ N#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ N#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ N#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ N N/******************** Bit definition for BKP_CR register ********************/ N#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ N#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ N N/******************* Bit definition for BKP_CSR register ********************/ N#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ N#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ N#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ N#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ N#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ N N/******************************************************************************/ N/* */ N/* Reset and Clock Control */ N/* */ N/******************************************************************************/ N N/******************** Bit definition for RCC_CR register ********************/ N#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ N#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ N#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ N#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ N#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ N#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ N#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ N#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ N#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ N#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ N N#ifdef STM32F10X_CL S #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ S #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ S #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ S #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ N#endif /* STM32F10X_CL */ N N/******************* Bit definition for RCC_CFGR register *******************/ N/*!< SW configuration */ N#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ N#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N N#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ N#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ N#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ N N/*!< SWS configuration */ N#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ N#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ N#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ N#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ N N/*!< HPRE configuration */ N#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ N#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ N#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ N#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ N#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ N#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ N#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ N#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ N#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ N#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ N N/*!< PPRE1 configuration */ N#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ N#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N N#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ N#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ N#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ N#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ N#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ N N/*!< PPRE2 configuration */ N#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ N#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ N#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ N#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ N N#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ N#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ N#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ N#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ N#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ N N/*!< ADCPPRE configuration */ N#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ N#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ N#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ N N#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ N#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ N#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ N#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ N N#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ N N#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ N N/*!< PLLMUL configuration */ N#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ N#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ N#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ N#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ N#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ N N#ifdef STM32F10X_CL S #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ S #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ S S #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ S #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ S S #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ S #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ S #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ S #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ S #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ S #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ S #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ S S #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ S S/*!< MCO configuration */ S #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ S #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ S #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ S #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ S #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ S #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ S #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ S #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ S #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ S #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ S#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#elif 0L || 0L || 0L S #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ S #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ S S #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ S #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ S S #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ S #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ S #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ S #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ S #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ S #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ S #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ S #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ S #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ S #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ S #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ S #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ S #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ S #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ S #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ S S/*!< MCO configuration */ S #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ S #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S S #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ S #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ S #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ S #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ S #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ N#else N #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ N #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ N N #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ N #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ N N #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ N #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ N #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ N #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ N #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ N #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ N #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ N #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ N #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ N #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ N #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ N #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ N #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ N #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ N #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ N #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ N N/*!< MCO configuration */ N #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ N #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N N #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ N #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ N #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ N #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ N #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ N#endif /* STM32F10X_CL */ N N/*!<****************** Bit definition for RCC_CIR register ********************/ N#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ N#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ N#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ N#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ N#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ N#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ N#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ N#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ N#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ N#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ N#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ N#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ N#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ N#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ N#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ N#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ N#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ N N#ifdef STM32F10X_CL S #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ S #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ S #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ S #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ S #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ S #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ N#endif /* STM32F10X_CL */ N N/***************** Bit definition for RCC_APB2RSTR register *****************/ N#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ N#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ N#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ N#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ N#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ N#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ N N#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) X#if !0L && !0L && !0L N#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ N#endif N N#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ N#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ N#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ S#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ S#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ N#endif N N#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) X#if !0L && !0L N #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ N#endif /* STM32F10X_LD && STM32F10X_LD_VL */ N N#if defined (STM32F10X_HD) || defined (STM32F10X_XL) X#if 0L || 0L S #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ S #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ S #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ S #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ N#endif N N#if defined (STM32F10X_HD_VL) X#if 0L S #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ S #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ N#endif N N#ifdef STM32F10X_XL S #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ S #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ S #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ N#endif /* STM32F10X_XL */ N N/***************** Bit definition for RCC_APB1RSTR register *****************/ N#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ N#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ N#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ N#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ N#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ N N#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) X#if !0L && !0L && !0L N#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ N#endif N N#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ N#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ N N#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) X#if !0L && !0L N #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ N #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ N #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ N #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ N#endif /* STM32F10X_LD && STM32F10X_LD_VL */ N N#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) X#if 0L || 1L || 0L || 0L N #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ N#endif N N#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) X#if 0L || 0L || 0L S #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ S #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ S #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ S #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ S #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ S #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ S #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ N#endif N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ S #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ S #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ S #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ N#endif N N#if defined (STM32F10X_HD_VL) X#if 0L S #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ S #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ S #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ S #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ S #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ S #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ S #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ N#endif N N#ifdef STM32F10X_CL S #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ N#endif /* STM32F10X_CL */ N N#ifdef STM32F10X_XL S #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ S #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ S #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ N#endif /* STM32F10X_XL */ N N/****************** Bit definition for RCC_AHBENR register ******************/ N#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ N#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ N#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ N#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ N N#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ N#endif N N#if defined (STM32F10X_HD) || defined (STM32F10X_XL) X#if 0L || 0L S #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ S #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ N#endif N N#if defined (STM32F10X_HD_VL) X#if 0L S #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ N#endif N N#ifdef STM32F10X_CL S #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ S #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ S #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ S #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ N#endif /* STM32F10X_CL */ N N/****************** Bit definition for RCC_APB2ENR register *****************/ N#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ N#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ N#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ N#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ N#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ N#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ N N#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) X#if !0L && !0L && !0L N#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ N#endif N N#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ N#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ N#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ S#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ S#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ N#endif N N#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) X#if !0L && !0L N #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ N#endif /* STM32F10X_LD && STM32F10X_LD_VL */ N N#if defined (STM32F10X_HD) || defined (STM32F10X_XL) X#if 0L || 0L S #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ S #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ S #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ S #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ N#endif N N#if defined (STM32F10X_HD_VL) X#if 0L S #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ S #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ N#endif N N#ifdef STM32F10X_XL S #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ S #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ S #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ N#endif N N/***************** Bit definition for RCC_APB1ENR register ******************/ N#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ N#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ N#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ N#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ N#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ N N#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) X#if !0L && !0L && !0L N#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ N#endif N N#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ N#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ N N#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) X#if !0L && !0L N #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ N #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ N #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ N #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ N#endif /* STM32F10X_LD && STM32F10X_LD_VL */ N N#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) X#if 0L || 1L || 0L N #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ N#endif N N#if defined (STM32F10X_HD) || defined (STM32F10X_CL) X#if 0L || 0L S #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ S #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ S #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ S #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ S #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ S #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ S #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ N#endif N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ S #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ S #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ S #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ N#endif N N#ifdef STM32F10X_HD_VL S #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ S #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ S #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ S #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ S #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ S #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ S #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ N#endif /* STM32F10X_HD_VL */ N N#ifdef STM32F10X_CL S #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ N#endif /* STM32F10X_CL */ N N#ifdef STM32F10X_XL S #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ S #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ S #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ N#endif /* STM32F10X_XL */ N N/******************* Bit definition for RCC_BDCR register *******************/ N#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ N#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ N#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ N N#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ N#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N N/*!< RTC congiguration */ N#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ N#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ N#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ N#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ N N#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ N#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ N N/******************* Bit definition for RCC_CSR register ********************/ N#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ N#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ N#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ N#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ N#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ N#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ N#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ N#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ N#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ N N#ifdef STM32F10X_CL S/******************* Bit definition for RCC_AHBRSTR register ****************/ S #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ S #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ S S/******************* Bit definition for RCC_CFGR2 register ******************/ S/*!< PREDIV1 configuration */ S #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ S #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ S #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ S #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ S #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ S #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ S #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ S #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ S #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ S #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ S #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ S #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ S #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ S #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ S #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ S #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ S #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ S S/*!< PREDIV2 configuration */ S #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ S #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ S #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ S #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ S #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ S #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ S #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ S #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ S #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ S #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ S #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ S #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ S #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ S #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ S #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ S #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ S #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ S S/*!< PLL2MUL configuration */ S #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ S #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ S #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ S #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ S #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ S #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ S #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ S #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ S #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ S #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ S S/*!< PLL3MUL configuration */ S #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ S #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ S #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ S S #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ S #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ S #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ S #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ S #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ S #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ S #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ S #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ S #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ S S #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ S #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ S #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ S #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ S #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ N#endif /* STM32F10X_CL */ N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S/******************* Bit definition for RCC_CFGR2 register ******************/ S/*!< PREDIV1 configuration */ S #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ S #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ S #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ S #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ S #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ S #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ S #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ S #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ S #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ S #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ S #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ S #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ S #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ S #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ S #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ S #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ S #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ N#endif N N/******************************************************************************/ N/* */ N/* General Purpose and Alternate Function I/O */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for GPIO_CRL register *******************/ N#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ N N#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ N#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N N#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ N#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ N#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N N#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ N#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ N#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ N N#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ N#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N N#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ N#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N N#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ N#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N N#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ N#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ N N#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ N#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ N#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N N#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ N#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N N#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ N#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ N#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ N N#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ N#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ N#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ N N#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ N#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ N#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ N N#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ N#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N N#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ N#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ N#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ N N/******************* Bit definition for GPIO_CRH register *******************/ N#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ N N#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ N#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N N#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ N#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ N#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N N#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ N#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ N#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ N N#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ N#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N N#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ N#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N N#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ N#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N N#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ N#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ N N#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ N#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ N#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N N#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ N#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N N#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ N#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ N#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ N N#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ N#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ N#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ N N#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ N#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ N#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ N N#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ N#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N N#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ N#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ N#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ N N/*!<****************** Bit definition for GPIO_IDR register *******************/ N#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ N#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ N#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ N#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ N#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ N#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ N#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ N#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ N#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ N#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ N#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ N#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ N#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ N#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ N#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ N#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ N N/******************* Bit definition for GPIO_ODR register *******************/ N#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ N#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ N#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ N#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ N#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ N#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ N#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ N#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ N#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ N#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ N#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ N#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ N#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ N#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ N#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ N#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ N N/****************** Bit definition for GPIO_BSRR register *******************/ N#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ N#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ N#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ N#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ N#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ N#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ N#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ N#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ N#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ N#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ N#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ N#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ N#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ N#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ N#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ N#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ N N#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ N#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ N#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ N#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ N#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ N#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ N#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ N#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ N#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ N#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ N#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ N#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ N#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ N#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ N#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ N#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ N N/******************* Bit definition for GPIO_BRR register *******************/ N#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ N#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ N#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ N#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ N#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ N#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ N#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ N#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ N#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ N#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ N#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ N#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ N#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ N#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ N#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ N#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ N N/****************** Bit definition for GPIO_LCKR register *******************/ N#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ N#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ N#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ N#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ N#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ N#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ N#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ N#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ N#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ N#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ N#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ N#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ N#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ N#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ N#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ N#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ N#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ N N/*----------------------------------------------------------------------------*/ N N/****************** Bit definition for AFIO_EVCR register *******************/ N#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ N#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ N#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ N#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ N#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ N N/*!< PIN configuration */ N#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ N#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ N#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ N#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ N#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ N#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ N#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ N#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ N#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ N#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ N#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ N#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ N#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ N#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ N#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ N#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ N N#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ N#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ N#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ N#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ N N/*!< PORT configuration */ N#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ N#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ N#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ N#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ N#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ N N#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ N N/****************** Bit definition for AFIO_MAPR register *******************/ N#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ N#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ N#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ N#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ N N#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ N#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N/* USART3_REMAP configuration */ N#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ N#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ N#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ N N#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ N#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N N/*!< TIM1_REMAP configuration */ N#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ N#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ N#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ N N#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ N#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N N/*!< TIM2_REMAP configuration */ N#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ N#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ N#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ N#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ N N#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ N#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N N/*!< TIM3_REMAP configuration */ N#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ N#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ N#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ N N#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ N N#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ N#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ N#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ N N/*!< CAN_REMAP configuration */ N#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ N#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ N#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ N N#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ N#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ N#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ N#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ N#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ N#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ N N/*!< SWJ_CFG configuration */ N#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ N#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N N#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ N#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ N#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ N#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ N N#ifdef STM32F10X_CL S/*!< ETH_REMAP configuration */ S #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ S S/*!< CAN2_REMAP configuration */ S #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ S S/*!< MII_RMII_SEL configuration */ S #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ S S/*!< SPI3_REMAP configuration */ S #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ S S/*!< TIM2ITR1_IREMAP configuration */ S #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ S S/*!< PTP_PPS_REMAP configuration */ S #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ N#endif N N/***************** Bit definition for AFIO_EXTICR1 register *****************/ N#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ N#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ N#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ N#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ N N/*!< EXTI0 configuration */ N#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ N#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ N#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ N#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ N#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ N#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ N#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ N N/*!< EXTI1 configuration */ N#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ N#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ N#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ N#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ N#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ N#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ N#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ N N/*!< EXTI2 configuration */ N#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ N#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ N#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ N#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ N#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ N#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ N#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ N N/*!< EXTI3 configuration */ N#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ N#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ N#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ N#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ N#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ N#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ N#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ N N/***************** Bit definition for AFIO_EXTICR2 register *****************/ N#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ N#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ N#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ N#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ N N/*!< EXTI4 configuration */ N#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ N#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ N#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ N#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ N#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ N#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ N#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ N N/* EXTI5 configuration */ N#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ N#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ N#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ N#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ N#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ N#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ N#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ N N/*!< EXTI6 configuration */ N#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ N#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ N#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ N#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ N#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ N#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ N#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ N N/*!< EXTI7 configuration */ N#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ N#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ N#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ N#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ N#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ N#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ N#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ N N/***************** Bit definition for AFIO_EXTICR3 register *****************/ N#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ N#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ N#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ N#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ N N/*!< EXTI8 configuration */ N#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ N#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ N#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ N#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ N#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ N#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ N#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ N N/*!< EXTI9 configuration */ N#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ N#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ N#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ N#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ N#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ N#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ N#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ N N/*!< EXTI10 configuration */ N#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ N#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ N#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ N#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ N#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ N#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ N#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ N N/*!< EXTI11 configuration */ N#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ N#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ N#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ N#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ N#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ N#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ N#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ N N/***************** Bit definition for AFIO_EXTICR4 register *****************/ N#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ N#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ N#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ N#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ N N/* EXTI12 configuration */ N#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ N#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ N#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ N#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ N#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ N#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ N#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ N N/* EXTI13 configuration */ N#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ N#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ N#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ N#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ N#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ N#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ N#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ N N/*!< EXTI14 configuration */ N#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ N#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ N#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ N#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ N#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ N#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ N#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ N N/*!< EXTI15 configuration */ N#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ N#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ N#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ N#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ N#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ N#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ N#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S/****************** Bit definition for AFIO_MAPR2 register ******************/ S#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ S#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ S#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ S#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ S#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ N#endif N N#ifdef STM32F10X_HD_VL S#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ S#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ S#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ S#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ S#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ S#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ N#endif N N#ifdef STM32F10X_XL S/****************** Bit definition for AFIO_MAPR2 register ******************/ S#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ S#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ S#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ S#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ S#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ S#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ N#endif N N/******************************************************************************/ N/* */ N/* SystemTick */ N/* */ N/******************************************************************************/ N N/***************** Bit definition for SysTick_CTRL register *****************/ N#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ N#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ N#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ N#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ N N/***************** Bit definition for SysTick_LOAD register *****************/ N#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ N N/***************** Bit definition for SysTick_VAL register ******************/ N#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ N N/***************** Bit definition for SysTick_CALIB register ****************/ N#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ N#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ N#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ N N/******************************************************************************/ N/* */ N/* Nested Vectored Interrupt Controller */ N/* */ N/******************************************************************************/ N N/****************** Bit definition for NVIC_ISER register *******************/ N#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ N#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ N#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ N#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ N#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ N#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ N#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ N#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ N#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ N#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ N#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ N#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ N#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ N#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ N#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ N#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ N#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ N#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ N#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ N#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ N#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ N#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ N#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ N#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ N#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ N#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ N#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ N#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ N#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ N#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ N#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ N#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ N#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ N N/****************** Bit definition for NVIC_ICER register *******************/ N#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ N#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ N#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ N#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ N#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ N#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ N#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ N#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ N#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ N#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ N#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ N#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ N#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ N#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ N#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ N#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ N#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ N#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ N#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ N#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ N#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ N#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ N#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ N#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ N#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ N#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ N#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ N#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ N#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ N#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ N#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ N#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ N#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ N N/****************** Bit definition for NVIC_ISPR register *******************/ N#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ N#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ N#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ N#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ N#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ N#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ N#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ N#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ N#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ N#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ N#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ N#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ N#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ N#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ N#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ N#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ N#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ N#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ N#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ N#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ N#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ N#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ N#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ N#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ N#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ N#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ N#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ N#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ N#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ N#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ N#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ N#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ N#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ N N/****************** Bit definition for NVIC_ICPR register *******************/ N#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ N#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ N#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ N#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ N#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ N#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ N#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ N#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ N#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ N#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ N#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ N#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ N#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ N#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ N#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ N#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ N#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ N#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ N#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ N#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ N#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ N#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ N#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ N#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ N#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ N#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ N#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ N#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ N#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ N#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ N#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ N#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ N#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ N N/****************** Bit definition for NVIC_IABR register *******************/ N#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ N#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ N#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ N#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ N#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ N#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ N#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ N#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ N#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ N#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ N#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ N#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ N#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ N#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ N#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ N#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ N#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ N#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ N#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ N#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ N#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ N#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ N#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ N#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ N#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ N#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ N#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ N#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ N#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ N#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ N#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ N#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ N#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ N N/****************** Bit definition for NVIC_PRI0 register *******************/ N#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ N#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ N#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ N#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ N N/****************** Bit definition for NVIC_PRI1 register *******************/ N#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ N#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ N#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ N#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ N N/****************** Bit definition for NVIC_PRI2 register *******************/ N#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ N#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ N#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ N#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ N N/****************** Bit definition for NVIC_PRI3 register *******************/ N#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ N#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ N#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ N#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ N N/****************** Bit definition for NVIC_PRI4 register *******************/ N#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ N#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ N#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ N#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ N N/****************** Bit definition for NVIC_PRI5 register *******************/ N#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ N#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ N#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ N#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ N N/****************** Bit definition for NVIC_PRI6 register *******************/ N#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ N#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ N#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ N#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ N N/****************** Bit definition for NVIC_PRI7 register *******************/ N#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ N#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ N#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ N#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ N N/****************** Bit definition for SCB_CPUID register *******************/ N#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ N#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ N#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ N#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ N#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ N N/******************* Bit definition for SCB_ICSR register *******************/ N#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ N#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ N#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ N#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ N#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ N#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ N#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ N#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ N#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ N#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ N N/******************* Bit definition for SCB_VTOR register *******************/ N#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ N#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ N N/*!<***************** Bit definition for SCB_AIRCR register *******************/ N#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ N#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ N#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ N N#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ N#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N N/* prority group configuration */ N#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ N#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ N#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ N#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ N#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ N#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ N#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ N#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ N N#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ N#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ N N/******************* Bit definition for SCB_SCR register ********************/ N#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ N#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ N#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ N N/******************** Bit definition for SCB_CCR register *******************/ N#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ N#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ N#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ N#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ N#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ N#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ N N/******************* Bit definition for SCB_SHPR register ********************/ N#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ N#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ N#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ N#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ N N/****************** Bit definition for SCB_SHCSR register *******************/ N#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ N#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ N#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ N#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ N#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ N#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ N#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ N#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ N#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ N#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ N#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ N#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ N#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ N#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ N N/******************* Bit definition for SCB_CFSR register *******************/ N/*!< MFSR */ N#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ N#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ N#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ N#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ N#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ N/*!< BFSR */ N#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ N#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ N#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ N#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ N#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ N#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ N/*!< UFSR */ N#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ N#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ N#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ N#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ N#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ N#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ N N/******************* Bit definition for SCB_HFSR register *******************/ N#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ N#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ N#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ N N/******************* Bit definition for SCB_DFSR register *******************/ N#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ N#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ N#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ N#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ N#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ N N/******************* Bit definition for SCB_MMFAR register ******************/ N#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ N N/******************* Bit definition for SCB_BFAR register *******************/ N#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ N N/******************* Bit definition for SCB_afsr register *******************/ N#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ N N/******************************************************************************/ N/* */ N/* External Interrupt/Event Controller */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for EXTI_IMR register *******************/ N#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ N#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ N#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ N#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ N#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ N#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ N#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ N#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ N#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ N#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ N#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ N#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ N#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ N#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ N#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ N#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ N#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ N#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ N#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ N#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ N N/******************* Bit definition for EXTI_EMR register *******************/ N#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ N#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ N#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ N#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ N#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ N#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ N#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ N#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ N#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ N#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ N#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ N#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ N#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ N#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ N#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ N#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ N#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ N#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ N#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ N#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ N N/****************** Bit definition for EXTI_RTSR register *******************/ N#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ N#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ N#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ N#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ N#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ N#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ N#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ N#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ N#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ N#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ N#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ N#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ N#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ N#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ N#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ N#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ N#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ N#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ N#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ N#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ N N/****************** Bit definition for EXTI_FTSR register *******************/ N#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ N#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ N#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ N#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ N#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ N#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ N#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ N#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ N#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ N#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ N#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ N#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ N#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ N#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ N#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ N#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ N#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ N#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ N#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ N#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ N N/****************** Bit definition for EXTI_SWIER register ******************/ N#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ N#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ N#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ N#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ N#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ N#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ N#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ N#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ N#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ N#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ N#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ N#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ N#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ N#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ N#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ N#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ N#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ N#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ N#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ N#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ N N/******************* Bit definition for EXTI_PR register ********************/ N#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ N#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ N#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ N#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ N#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ N#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ N#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ N#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ N#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ N#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ N#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ N#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ N#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ N#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ N#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ N#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ N#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ N#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ N#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ N#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ N N/******************************************************************************/ N/* */ N/* DMA Controller */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for DMA_ISR register ********************/ N#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ N#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ N#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ N#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ N#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ N#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ N#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ N#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ N#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ N#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ N#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ N#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ N#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ N#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ N#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ N#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ N#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ N#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ N#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ N#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ N#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ N#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ N#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ N#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ N#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ N#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ N#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ N#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ N N/******************* Bit definition for DMA_IFCR register *******************/ N#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ N#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ N#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ N#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ N#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ N#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ N#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ N#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ N#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ N#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ N#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ N#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ N#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ N#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ N#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ N#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ N#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ N#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ N#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ N#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ N#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ N#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ N#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ N#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ N#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ N#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ N#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ N#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ N N/******************* Bit definition for DMA_CCR1 register *******************/ N#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ N#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ N#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ N N/******************* Bit definition for DMA_CCR2 register *******************/ N#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ N#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ N#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ N N/******************* Bit definition for DMA_CCR3 register *******************/ N#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ N#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ N#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ N N/*!<****************** Bit definition for DMA_CCR4 register *******************/ N#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ N#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ N#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ N N/****************** Bit definition for DMA_CCR5 register *******************/ N#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ N#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ N#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ N N/******************* Bit definition for DMA_CCR6 register *******************/ N#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ N#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ N#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ N N/******************* Bit definition for DMA_CCR7 register *******************/ N#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ N#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ N#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ N#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ N#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ N#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ N#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ N#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ N N#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ N#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ N#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ N#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ N N/****************** Bit definition for DMA_CNDTR1 register ******************/ N#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CNDTR2 register ******************/ N#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CNDTR3 register ******************/ N#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CNDTR4 register ******************/ N#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CNDTR5 register ******************/ N#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CNDTR6 register ******************/ N#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CNDTR7 register ******************/ N#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ N N/****************** Bit definition for DMA_CPAR1 register *******************/ N#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N/****************** Bit definition for DMA_CPAR2 register *******************/ N#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N/****************** Bit definition for DMA_CPAR3 register *******************/ N#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N N/****************** Bit definition for DMA_CPAR4 register *******************/ N#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N/****************** Bit definition for DMA_CPAR5 register *******************/ N#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N/****************** Bit definition for DMA_CPAR6 register *******************/ N#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N N/****************** Bit definition for DMA_CPAR7 register *******************/ N#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ N N/****************** Bit definition for DMA_CMAR1 register *******************/ N#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N/****************** Bit definition for DMA_CMAR2 register *******************/ N#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N/****************** Bit definition for DMA_CMAR3 register *******************/ N#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N N/****************** Bit definition for DMA_CMAR4 register *******************/ N#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N/****************** Bit definition for DMA_CMAR5 register *******************/ N#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N/****************** Bit definition for DMA_CMAR6 register *******************/ N#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N/****************** Bit definition for DMA_CMAR7 register *******************/ N#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ N N/******************************************************************************/ N/* */ N/* Analog to Digital Converter */ N/* */ N/******************************************************************************/ N N/******************** Bit definition for ADC_SR register ********************/ N#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ N#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ N#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ N#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ N#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ N N/******************* Bit definition for ADC_CR1 register ********************/ N#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ N#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N N#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ N#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ N#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ N#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ N#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ N#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ N#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ N#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ N N#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ N#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ N#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ N#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ N N#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ N#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N N#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ N#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ N N N/******************* Bit definition for ADC_CR2 register ********************/ N#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ N#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ N#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ N#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ N#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ N#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ N N#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ N#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ N#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ N#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ N N#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ N N#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ N#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ N#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ N#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ N N#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ N#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ N#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ N#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ N N/****************** Bit definition for ADC_SMPR1 register *******************/ N#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ N#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ N#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ N#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ N#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ N#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ N#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ N#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ N#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ N#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ N#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ N#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ N#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ N#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ N#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ N#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ N#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ N#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ N N#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ N#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ N#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ N#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ N N/****************** Bit definition for ADC_SMPR2 register *******************/ N#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ N#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ N#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ N#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ N#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ N#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ N#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ N#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ N#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ N#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ N#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ N#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ N#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ N#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ N#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ N#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ N#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ N#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ N#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ N#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ N#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ N#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N N#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ N#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ N#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ N#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ N N/****************** Bit definition for ADC_JOFR1 register *******************/ N#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ N N/****************** Bit definition for ADC_JOFR2 register *******************/ N#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ N N/****************** Bit definition for ADC_JOFR3 register *******************/ N#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ N N/****************** Bit definition for ADC_JOFR4 register *******************/ N#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ N N/******************* Bit definition for ADC_HTR register ********************/ N#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ N N/******************* Bit definition for ADC_LTR register ********************/ N#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ N N/******************* Bit definition for ADC_SQR1 register *******************/ N#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ N#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N N#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ N#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ N#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ N#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ N#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ N#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ N N#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ N#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ N#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ N#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ N#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ N#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ N#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ N N#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ N#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N/******************* Bit definition for ADC_SQR2 register *******************/ N#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ N#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N N#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ N#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ N#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ N#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ N#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ N#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ N N#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ N#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ N#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ N#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ N#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ N#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ N#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ N N#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ N#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ N N#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ N#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ N#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ N#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ N#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ N#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ N N/******************* Bit definition for ADC_SQR3 register *******************/ N#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ N#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N N#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ N#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ N#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ N#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ N#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ N#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ N N#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ N#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ N#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ N#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ N#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ N#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ N#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ N N#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ N#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ N N#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ N#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ N#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ N#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ N#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ N#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ N N/******************* Bit definition for ADC_JSQR register *******************/ N#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ N#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N N#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ N#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ N#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ N#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ N#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ N#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ N N#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ N#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ N#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ N#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ N#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ N#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ N#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ N N#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ N#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N N/******************* Bit definition for ADC_JDR1 register *******************/ N#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ N N/******************* Bit definition for ADC_JDR2 register *******************/ N#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ N N/******************* Bit definition for ADC_JDR3 register *******************/ N#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ N N/******************* Bit definition for ADC_JDR4 register *******************/ N#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ N N/******************** Bit definition for ADC_DR register ********************/ N#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ N#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ N N/******************************************************************************/ N/* */ N/* Digital to Analog Converter */ N/* */ N/******************************************************************************/ N N/******************** Bit definition for DAC_CR register ********************/ N#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ N#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ N#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ N N#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ N#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ N#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ N#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ N N#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ N#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N N#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ N#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ N#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ N#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ N#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ N N#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ N#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ N#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ N#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ N N#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ N#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ N#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ N N#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ N#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ N N/***************** Bit definition for DAC_SWTRIGR register ******************/ N#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ N#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ N N/***************** Bit definition for DAC_DHR12R1 register ******************/ N#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ N N/***************** Bit definition for DAC_DHR12L1 register ******************/ N#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ N N/****************** Bit definition for DAC_DHR8R1 register ******************/ N#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ N N/***************** Bit definition for DAC_DHR12R2 register ******************/ N#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ N N/***************** Bit definition for DAC_DHR12L2 register ******************/ N#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ N N/****************** Bit definition for DAC_DHR8R2 register ******************/ N#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ N N/***************** Bit definition for DAC_DHR12RD register ******************/ N#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ N#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ N N/***************** Bit definition for DAC_DHR12LD register ******************/ N#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ N#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ N N/****************** Bit definition for DAC_DHR8RD register ******************/ N#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ N#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ N N/******************* Bit definition for DAC_DOR1 register *******************/ N#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ N N/******************* Bit definition for DAC_DOR2 register *******************/ N#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ N N/******************** Bit definition for DAC_SR register ********************/ N#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ N#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ N N/******************************************************************************/ N/* */ N/* CEC */ N/* */ N/******************************************************************************/ N/******************** Bit definition for CEC_CFGR register ******************/ N#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ N#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ N#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ N#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ N N/******************** Bit definition for CEC_OAR register ******************/ N#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ N#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ N N/******************** Bit definition for CEC_PRES register ******************/ N#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ N N/******************** Bit definition for CEC_ESR register ******************/ N#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ N#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ N#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ N#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ N#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ N#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ N#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ N N/******************** Bit definition for CEC_CSR register ******************/ N#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ N#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ N#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ N#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ N#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ N#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ N#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ N#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ N N/******************** Bit definition for CEC_TXD register ******************/ N#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ N N/******************** Bit definition for CEC_RXD register ******************/ N#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ N N/******************************************************************************/ N/* */ N/* TIM */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for TIM_CR1 register ********************/ N#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ N#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ N#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ N#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ N#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ N N#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ N#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ N#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ N N#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ N N#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ N#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N/******************* Bit definition for TIM_CR2 register ********************/ N#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ N#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ N#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ N N#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ N#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ N N#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ N#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ N#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ N#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ N#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ N#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ N#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ N#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ N N/******************* Bit definition for TIM_SMCR register *******************/ N#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ N#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ N N#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ N#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ N N#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ N N#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ N#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ N#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ N#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ N N#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ N#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ N#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ N N/******************* Bit definition for TIM_DIER register *******************/ N#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ N#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ N#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ N#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ N#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ N#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ N#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ N#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ N#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ N#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ N#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ N#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ N#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ N#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ N#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ N N/******************** Bit definition for TIM_SR register ********************/ N#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ N#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ N#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ N#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ N#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ N#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ N#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ N#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ N#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ N#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ N#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ N#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ N N/******************* Bit definition for TIM_EGR register ********************/ N#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ N#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ N#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ N#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ N#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ N#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ N#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ N#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ N N/****************** Bit definition for TIM_CCMR1 register *******************/ N#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ N#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ N N#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ N#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ N N#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ N#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ N N#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ N N#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ N#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ N#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ N N#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ N#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ N#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ N N#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ N N/*----------------------------------------------------------------------------*/ N N#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ N#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ N#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ N N#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ N#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ N#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ N N#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ N#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ N#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ N#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ N#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ N N/****************** Bit definition for TIM_CCMR2 register *******************/ N#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ N#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ N N#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ N#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ N N#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ N#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ N N#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ N N#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ N#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ N#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ N N#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ N#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ N#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ N N#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ N N/*----------------------------------------------------------------------------*/ N N#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ N#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ N#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ N N#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ N#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ N#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ N N#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ N#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ N N#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ N#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ N#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ N#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ N N/******************* Bit definition for TIM_CCER register *******************/ N#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ N#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ N#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ N#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ N#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ N#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ N#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ N#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ N#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ N#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ N#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ N#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ N#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ N#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ N#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ N N/******************* Bit definition for TIM_CNT register ********************/ N#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ N N/******************* Bit definition for TIM_PSC register ********************/ N#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ N N/******************* Bit definition for TIM_ARR register ********************/ N#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ N N/******************* Bit definition for TIM_RCR register ********************/ N#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ N N/******************* Bit definition for TIM_CCR1 register *******************/ N#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ N N/******************* Bit definition for TIM_CCR2 register *******************/ N#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ N N/******************* Bit definition for TIM_CCR3 register *******************/ N#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ N N/******************* Bit definition for TIM_CCR4 register *******************/ N#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ N N/******************* Bit definition for TIM_BDTR register *******************/ N#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ N#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ N#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ N#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ N#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ N#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ N N#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ N#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ N#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ N#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ N#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ N#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ N#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ N N/******************* Bit definition for TIM_DCR register ********************/ N#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ N#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ N#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ N N#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ N#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ N#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ N#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ N#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ N N/******************* Bit definition for TIM_DMAR register *******************/ N#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ N N/******************************************************************************/ N/* */ N/* Real-Time Clock */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for RTC_CRH register ********************/ N#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ N#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ N#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ N N/******************* Bit definition for RTC_CRL register ********************/ N#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ N#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ N#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ N#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ N#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ N#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ N N/******************* Bit definition for RTC_PRLH register *******************/ N#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ N N/******************* Bit definition for RTC_PRLL register *******************/ N#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ N N/******************* Bit definition for RTC_DIVH register *******************/ N#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ N N/******************* Bit definition for RTC_DIVL register *******************/ N#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ N N/******************* Bit definition for RTC_CNTH register *******************/ N#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ N N/******************* Bit definition for RTC_CNTL register *******************/ N#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ N N/******************* Bit definition for RTC_ALRH register *******************/ N#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ N N/******************* Bit definition for RTC_ALRL register *******************/ N#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ N N/******************************************************************************/ N/* */ N/* Independent WATCHDOG */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for IWDG_KR register ********************/ N#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ N N/******************* Bit definition for IWDG_PR register ********************/ N#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ N#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ N#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ N#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ N N/******************* Bit definition for IWDG_RLR register *******************/ N#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ N N/******************* Bit definition for IWDG_SR register ********************/ N#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ N#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ N N/******************************************************************************/ N/* */ N/* Window WATCHDOG */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for WWDG_CR register ********************/ N#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ N#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ N#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ N#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ N#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ N#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ N#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ N#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ N N#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ N N/******************* Bit definition for WWDG_CFR register *******************/ N#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ N#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ N#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ N#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ N#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ N N#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ N#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ N#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ N N#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ N N/******************* Bit definition for WWDG_SR register ********************/ N#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ N N/******************************************************************************/ N/* */ N/* Flexible Static Memory Controller */ N/* */ N/******************************************************************************/ N N/****************** Bit definition for FSMC_BCR1 register *******************/ N#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ N#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ N N#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ N#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ N#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ N#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ N#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ N#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ N#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ N#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ N#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ N#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ N#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ N#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ N N/****************** Bit definition for FSMC_BCR2 register *******************/ N#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ N#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ N N#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ N#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ N#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ N#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ N#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ N#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ N#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ N#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ N#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ N#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ N#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ N#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ N N/****************** Bit definition for FSMC_BCR3 register *******************/ N#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ N#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ N N#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ N#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ N#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ N#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ N#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ N#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ N#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ N#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ N#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ N#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ N#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ N#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ N N/****************** Bit definition for FSMC_BCR4 register *******************/ N#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ N#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ N N#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ N#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ N#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ N N#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ N#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ N#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ N#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ N#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ N#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ N#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ N#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ N#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ N#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ N#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ N N/****************** Bit definition for FSMC_BTR1 register ******************/ N#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ N#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N N#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_BTR2 register *******************/ N#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ N#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N N#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/******************* Bit definition for FSMC_BTR3 register *******************/ N#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ N#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N N#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_BTR4 register *******************/ N#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ N#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N N#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_BWTR1 register ******************/ N#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_BWTR2 register ******************/ N#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ N#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_BWTR3 register ******************/ N#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_BWTR4 register ******************/ N#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ N#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N N#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ N#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ N N#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ N#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N N#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ N#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ N#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ N#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ N#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ N N#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ N#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N N#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ N#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ N#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ N N/****************** Bit definition for FSMC_PCR2 register *******************/ N#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ N#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ N#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ N N#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ N#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ N N#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ N#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ N#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ N#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ N#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ N N#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ N#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ N#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ N#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ N#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ N N#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ N#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ N#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ N#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ N N/****************** Bit definition for FSMC_PCR3 register *******************/ N#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ N#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ N#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ N N#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ N#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ N N#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ N#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ N#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ N#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ N#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ N N#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ N#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ N#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ N#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ N#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ N N#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ N#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ N#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ N#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ N N/****************** Bit definition for FSMC_PCR4 register *******************/ N#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ N#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ N#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ N N#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ N#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N N#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ N N#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ N#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ N#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ N#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ N#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ N N#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ N#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ N#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ N#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ N#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ N N#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ N#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ N#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ N#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ N N/******************* Bit definition for FSMC_SR2 register *******************/ N#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ N#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ N#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ N#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ N#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ N#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ N#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ N N/******************* Bit definition for FSMC_SR3 register *******************/ N#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ N#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ N#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ N#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ N#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ N#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ N#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ N N/******************* Bit definition for FSMC_SR4 register *******************/ N#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ N#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ N#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ N#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ N#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ N#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ N#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ N N/****************** Bit definition for FSMC_PMEM2 register ******************/ N#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ N#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ N#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ N#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ N#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_PMEM3 register ******************/ N#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ N#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ N#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ N#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ N#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_PMEM4 register ******************/ N#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ N#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ N#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ N#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ N#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_PATT2 register ******************/ N#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ N#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ N#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ N#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ N#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_PATT3 register ******************/ N#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ N#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ N#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ N#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ N#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_PATT4 register ******************/ N#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ N#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ N#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ N#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ N#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_PIO4 register *******************/ N#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ N#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ N#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ N#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ N#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ N#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ N#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ N#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ N#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ N N#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ N#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ N#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ N#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ N#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ N#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ N#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ N#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ N#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ N N#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ N#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N N#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ N#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ N#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ N#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ N#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ N#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ N#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ N#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ N#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ N N/****************** Bit definition for FSMC_ECCR2 register ******************/ N#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ N N/****************** Bit definition for FSMC_ECCR3 register ******************/ N#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ N N/******************************************************************************/ N/* */ N/* SD host Interface */ N/* */ N/******************************************************************************/ N N/****************** Bit definition for SDIO_POWER register ******************/ N#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ N#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ N#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ N N/****************** Bit definition for SDIO_CLKCR register ******************/ N#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ N#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ N#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ N#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ N N#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ N#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ N#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ N N#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ N#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ N N/******************* Bit definition for SDIO_ARG register *******************/ N#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ N N/******************* Bit definition for SDIO_CMD register *******************/ N#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ N N#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ N#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ N#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ N N#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ N#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ N#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ N#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ N#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ N#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ N#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ N N/***************** Bit definition for SDIO_RESPCMD register *****************/ N#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ N N/****************** Bit definition for SDIO_RESP0 register ******************/ N#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ N N/****************** Bit definition for SDIO_RESP1 register ******************/ N#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ N N/****************** Bit definition for SDIO_RESP2 register ******************/ N#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ N N/****************** Bit definition for SDIO_RESP3 register ******************/ N#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ N N/****************** Bit definition for SDIO_RESP4 register ******************/ N#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ N N/****************** Bit definition for SDIO_DTIMER register *****************/ N#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ N N/****************** Bit definition for SDIO_DLEN register *******************/ N#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ N N/****************** Bit definition for SDIO_DCTRL register ******************/ N#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ N#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ N#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ N#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ N N#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ N#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ N#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ N#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ N N#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ N#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ N#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ N#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ N N/****************** Bit definition for SDIO_DCOUNT register *****************/ N#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ N N/****************** Bit definition for SDIO_STA register ********************/ N#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ N#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ N#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ N#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ N#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ N#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ N#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ N#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ N#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ N#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ N#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ N#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ N#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ N#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ N#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ N#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ N#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ N#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ N#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ N#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ N#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ N#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ N#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ N#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ N N/******************* Bit definition for SDIO_ICR register *******************/ N#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ N#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ N#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ N#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ N#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ N#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ N#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ N#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ N#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ N#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ N#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ N#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ N#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ N N/****************** Bit definition for SDIO_MASK register *******************/ N#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ N#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ N#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ N#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ N#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ N#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ N#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ N#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ N#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ N#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ N#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ N#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ N#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ N#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ N#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ N#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ N#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ N#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ N#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ N#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ N#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ N#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ N#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ N#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ N N/***************** Bit definition for SDIO_FIFOCNT register *****************/ N#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ N N/****************** Bit definition for SDIO_FIFO register *******************/ N#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ N N/******************************************************************************/ N/* */ N/* USB Device FS */ N/* */ N/******************************************************************************/ N N/*!< Endpoint-specific registers */ N/******************* Bit definition for USB_EP0R register *******************/ N#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP1R register *******************/ N#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP2R register *******************/ N#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP3R register *******************/ N#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP4R register *******************/ N#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP5R register *******************/ N#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP6R register *******************/ N#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/******************* Bit definition for USB_EP7R register *******************/ N#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ N N#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ N#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ N#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ N#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ N N#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ N#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ N#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ N N#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ N N#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ N#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ N#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ N N/*!< Common registers */ N/******************* Bit definition for USB_CNTR register *******************/ N#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ N#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ N#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ N#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ N#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ N#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ N#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ N#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ N#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ N#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ N#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ N#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ N#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ N N/******************* Bit definition for USB_ISTR register *******************/ N#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ N#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ N#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ N#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ N#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ N#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ N#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ N#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ N#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ N#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ N N/******************* Bit definition for USB_FNR register ********************/ N#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ N#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ N#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ N#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ N#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ N N/****************** Bit definition for USB_DADDR register *******************/ N#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ N#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ N#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ N#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ N#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ N#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ N#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ N#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ N N#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ N N/****************** Bit definition for USB_BTABLE register ******************/ N#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ N N/*!< Buffer descriptor table */ N/***************** Bit definition for USB_ADDR0_TX register *****************/ N#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ N N/***************** Bit definition for USB_ADDR1_TX register *****************/ N#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ N N/***************** Bit definition for USB_ADDR2_TX register *****************/ N#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ N N/***************** Bit definition for USB_ADDR3_TX register *****************/ N#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ N N/***************** Bit definition for USB_ADDR4_TX register *****************/ N#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ N N/***************** Bit definition for USB_ADDR5_TX register *****************/ N#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ N N/***************** Bit definition for USB_ADDR6_TX register *****************/ N#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ N N/***************** Bit definition for USB_ADDR7_TX register *****************/ N#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ N N/*----------------------------------------------------------------------------*/ N N/***************** Bit definition for USB_COUNT0_TX register ****************/ N#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ N N/***************** Bit definition for USB_COUNT1_TX register ****************/ N#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ N N/***************** Bit definition for USB_COUNT2_TX register ****************/ N#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ N N/***************** Bit definition for USB_COUNT3_TX register ****************/ N#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ N N/***************** Bit definition for USB_COUNT4_TX register ****************/ N#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ N N/***************** Bit definition for USB_COUNT5_TX register ****************/ N#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ N N/***************** Bit definition for USB_COUNT6_TX register ****************/ N#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ N N/***************** Bit definition for USB_COUNT7_TX register ****************/ N#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ N N/*----------------------------------------------------------------------------*/ N N/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ N#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ N N/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ N#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ N N/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ N#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ N N/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ N#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ N N/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ N#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ N N/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ N#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ N N/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ N#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ N N/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ N#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ N N/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ N#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ N N/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ N#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ N N/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ N#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ N N/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ N#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ N N/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ N#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ N N/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ N#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ N N/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ N#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ N N/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ N#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ N N/*----------------------------------------------------------------------------*/ N N/***************** Bit definition for USB_ADDR0_RX register *****************/ N#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ N N/***************** Bit definition for USB_ADDR1_RX register *****************/ N#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ N N/***************** Bit definition for USB_ADDR2_RX register *****************/ N#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ N N/***************** Bit definition for USB_ADDR3_RX register *****************/ N#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ N N/***************** Bit definition for USB_ADDR4_RX register *****************/ N#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ N N/***************** Bit definition for USB_ADDR5_RX register *****************/ N#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ N N/***************** Bit definition for USB_ADDR6_RX register *****************/ N#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ N N/***************** Bit definition for USB_ADDR7_RX register *****************/ N#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ N N/*----------------------------------------------------------------------------*/ N N/***************** Bit definition for USB_COUNT0_RX register ****************/ N#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT1_RX register ****************/ N#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT2_RX register ****************/ N#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT3_RX register ****************/ N#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT4_RX register ****************/ N#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT5_RX register ****************/ N#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT6_RX register ****************/ N#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/***************** Bit definition for USB_COUNT7_RX register ****************/ N#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ N N#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ N#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ N#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ N#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ N#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ N#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ N N#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ N N/*----------------------------------------------------------------------------*/ N N/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ N#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ N#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ N#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ N#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ N#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ N#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ N#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ N#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ N#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ N#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ N#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ N#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ N#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ N#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ N#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ N#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ N N#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ N#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ N#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ N#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ N#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ N#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ N N#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ N N/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ N#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ N N#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ N#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ N#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ N#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ N#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ N#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ N N#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ N N/******************************************************************************/ N/* */ N/* Controller Area Network */ N/* */ N/******************************************************************************/ N N/*!< CAN control and status registers */ N/******************* Bit definition for CAN_MCR register ********************/ N#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ N#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ N#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ N#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ N#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ N#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ N#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ N#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ N#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ N N/******************* Bit definition for CAN_MSR register ********************/ N#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ N#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ N#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ N#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ N#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ N#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ N#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ N#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ N#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ N N/******************* Bit definition for CAN_TSR register ********************/ N#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ N#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ N#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ N#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ N#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ N#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ N#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ N#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ N#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ N#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ N#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ N#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ N#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ N#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ N#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ N#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ N N#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ N#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ N#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ N#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ N N#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ N#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ N#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ N#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ N N/******************* Bit definition for CAN_RF0R register *******************/ N#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ N#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ N#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ N#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ N N/******************* Bit definition for CAN_RF1R register *******************/ N#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ N#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ N#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ N#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ N N/******************** Bit definition for CAN_IER register *******************/ N#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ N#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ N#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ N#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ N#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ N#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ N#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ N#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ N#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ N#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ N#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ N#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ N#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ N#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ N N/******************** Bit definition for CAN_ESR register *******************/ N#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ N#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ N#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ N N#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ N#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ N#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ N#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ N N#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ N#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ N N/******************* Bit definition for CAN_BTR register ********************/ N#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ N#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ N#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ N#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ N#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ N#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ N N/*!< Mailbox registers */ N/****************** Bit definition for CAN_TI0R register ********************/ N#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ N#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ N#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ N#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ N#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ N N/****************** Bit definition for CAN_TDT0R register *******************/ N#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ N#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ N#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ N N/****************** Bit definition for CAN_TDL0R register *******************/ N#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ N#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ N#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ N#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ N N/****************** Bit definition for CAN_TDH0R register *******************/ N#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ N#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ N#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ N#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ N N/******************* Bit definition for CAN_TI1R register *******************/ N#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ N#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ N#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ N#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ N#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ N N/******************* Bit definition for CAN_TDT1R register ******************/ N#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ N#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ N#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ N N/******************* Bit definition for CAN_TDL1R register ******************/ N#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ N#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ N#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ N#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ N N/******************* Bit definition for CAN_TDH1R register ******************/ N#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ N#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ N#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ N#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ N N/******************* Bit definition for CAN_TI2R register *******************/ N#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ N#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ N#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ N#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ N#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ N N/******************* Bit definition for CAN_TDT2R register ******************/ N#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ N#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ N#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ N N/******************* Bit definition for CAN_TDL2R register ******************/ N#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ N#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ N#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ N#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ N N/******************* Bit definition for CAN_TDH2R register ******************/ N#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ N#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ N#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ N#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ N N/******************* Bit definition for CAN_RI0R register *******************/ N#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ N#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ N#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ N#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ N N/******************* Bit definition for CAN_RDT0R register ******************/ N#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ N#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ N#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ N N/******************* Bit definition for CAN_RDL0R register ******************/ N#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ N#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ N#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ N#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ N N/******************* Bit definition for CAN_RDH0R register ******************/ N#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ N#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ N#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ N#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ N N/******************* Bit definition for CAN_RI1R register *******************/ N#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ N#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ N#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ N#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ N N/******************* Bit definition for CAN_RDT1R register ******************/ N#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ N#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ N#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ N N/******************* Bit definition for CAN_RDL1R register ******************/ N#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ N#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ N#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ N#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ N N/******************* Bit definition for CAN_RDH1R register ******************/ N#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ N#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ N#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ N#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ N N/*!< CAN filter registers */ N/******************* Bit definition for CAN_FMR register ********************/ N#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ N N/******************* Bit definition for CAN_FM1R register *******************/ N#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ N#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ N#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ N#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ N#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ N#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ N#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ N#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ N#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ N#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ N#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ N#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ N#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ N#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ N#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ N N/******************* Bit definition for CAN_FS1R register *******************/ N#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ N#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ N#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ N#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ N#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ N#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ N#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ N#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ N#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ N#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ N#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ N#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ N#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ N#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ N#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ N N/****************** Bit definition for CAN_FFA1R register *******************/ N#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ N#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ N#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ N#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ N#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ N#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ N#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ N#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ N#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ N#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ N#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ N#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ N#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ N#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ N#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ N N/******************* Bit definition for CAN_FA1R register *******************/ N#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ N#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ N#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ N#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ N#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ N#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ N#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ N#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ N#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ N#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ N#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ N#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ N#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ N#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ N#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ N N/******************* Bit definition for CAN_F0R1 register *******************/ N#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F1R1 register *******************/ N#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F2R1 register *******************/ N#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F3R1 register *******************/ N#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F4R1 register *******************/ N#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F5R1 register *******************/ N#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F6R1 register *******************/ N#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F7R1 register *******************/ N#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F8R1 register *******************/ N#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F9R1 register *******************/ N#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F10R1 register ******************/ N#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F11R1 register ******************/ N#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F12R1 register ******************/ N#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F13R1 register ******************/ N#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F0R2 register *******************/ N#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F1R2 register *******************/ N#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F2R2 register *******************/ N#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F3R2 register *******************/ N#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F4R2 register *******************/ N#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F5R2 register *******************/ N#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F6R2 register *******************/ N#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F7R2 register *******************/ N#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F8R2 register *******************/ N#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F9R2 register *******************/ N#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F10R2 register ******************/ N#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F11R2 register ******************/ N#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F12R2 register ******************/ N#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************* Bit definition for CAN_F13R2 register ******************/ N#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ N#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ N#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ N#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ N#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ N#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ N#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ N#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ N#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ N#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ N#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ N#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ N#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ N#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ N#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ N#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ N#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ N#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ N#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ N#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ N#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ N#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ N#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ N#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ N#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ N#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ N#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ N#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ N#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ N#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ N#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ N#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ N N/******************************************************************************/ N/* */ N/* Serial Peripheral Interface */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for SPI_CR1 register ********************/ N#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ N#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ N#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ N N#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ N#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ N#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ N#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ N N#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ N#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ N#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ N#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ N#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ N#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ N#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ N#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ N#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ N#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ N N/******************* Bit definition for SPI_CR2 register ********************/ N#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ N#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ N#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ N#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ N#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ N#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ N N/******************** Bit definition for SPI_SR register ********************/ N#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ N#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ N#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ N#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ N#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ N#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ N#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ N#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ N N/******************** Bit definition for SPI_DR register ********************/ N#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ N N/******************* Bit definition for SPI_CRCPR register ******************/ N#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ N N/****************** Bit definition for SPI_RXCRCR register ******************/ N#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ N N/****************** Bit definition for SPI_TXCRCR register ******************/ N#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ N N/****************** Bit definition for SPI_I2SCFGR register *****************/ N#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ N N#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ N#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ N#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ N N#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ N N#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ N#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ N#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ N N#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ N N#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ N#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ N#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ N N#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ N#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ N N/****************** Bit definition for SPI_I2SPR register *******************/ N#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ N#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ N#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ N N/******************************************************************************/ N/* */ N/* Inter-integrated Circuit Interface */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for I2C_CR1 register ********************/ N#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ N#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ N#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ N#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ N#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ N#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ N#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ N#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ N#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ N#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ N#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ N#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ N#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ N#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ N N/******************* Bit definition for I2C_CR2 register ********************/ N#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ N#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ N#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ N#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ N N#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ N#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ N#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ N#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ N#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ N N/******************* Bit definition for I2C_OAR1 register *******************/ N#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ N#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ N N#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ N#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ N#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ N#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ N#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ N#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ N#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ N N#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ N N/******************* Bit definition for I2C_OAR2 register *******************/ N#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ N#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ N N/******************** Bit definition for I2C_DR register ********************/ N#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ N N/******************* Bit definition for I2C_SR1 register ********************/ N#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ N#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ N#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ N#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ N#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ N#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ N#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ N#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ N#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ N#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ N#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ N#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ N#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ N#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ N N/******************* Bit definition for I2C_SR2 register ********************/ N#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ N#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ N#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ N#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ N#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ N#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ N#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ N#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ N N/******************* Bit definition for I2C_CCR register ********************/ N#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ N#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ N#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ N N/****************** Bit definition for I2C_TRISE register *******************/ N#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ N N/******************************************************************************/ N/* */ N/* Universal Synchronous Asynchronous Receiver Transmitter */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for USART_SR register *******************/ N#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ N#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ N#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ N#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ N#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ N#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ N#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ N#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ N#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ N#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ N N/******************* Bit definition for USART_DR register *******************/ N#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ N N/****************** Bit definition for USART_BRR register *******************/ N#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ N#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ N N/****************** Bit definition for USART_CR1 register *******************/ N#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ N#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ N#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ N#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ N#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ N#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ N#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ N#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ N#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ N#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ N#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ N#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ N#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ N#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ N#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ N N/****************** Bit definition for USART_CR2 register *******************/ N#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ N#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ N#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ N#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ N#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ N#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ N#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ N N#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ N#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ N#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ N N#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ N N/****************** Bit definition for USART_CR3 register *******************/ N#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ N#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ N#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ N#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ N#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ N#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ N#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ N#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ N#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ N#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ N#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ N#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ N N/****************** Bit definition for USART_GTPR register ******************/ N#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ N#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ N#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ N#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ N#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ N#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ N#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ N#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ N#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ N N#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ N N/******************************************************************************/ N/* */ N/* Debug MCU */ N/* */ N/******************************************************************************/ N N/**************** Bit definition for DBGMCU_IDCODE register *****************/ N#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ N N#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ N#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ N#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ N#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ N#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ N#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ N#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ N#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ N#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ N#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ N#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ N#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ N#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ N#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ N#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ N#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ N#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ N N/****************** Bit definition for DBGMCU_CR register *******************/ N#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ N#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ N#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ N#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ N N#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ N#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ N#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ N N#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ N#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ N#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ N#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ N#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ N#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ N N/******************************************************************************/ N/* */ N/* FLASH and Option Bytes Registers */ N/* */ N/******************************************************************************/ N N/******************* Bit definition for FLASH_ACR register ******************/ N#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ N#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ N#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ N#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ N N#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ N#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ N#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ N N/****************** Bit definition for FLASH_KEYR register ******************/ N#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ N N/***************** Bit definition for FLASH_OPTKEYR register ****************/ N#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ N N/****************** Bit definition for FLASH_SR register *******************/ N#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ N#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ N#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ N#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ N N/******************* Bit definition for FLASH_CR register *******************/ N#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ N#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ N#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ N#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ N#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ N#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ N#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ N#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ N#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ N#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ N N/******************* Bit definition for FLASH_AR register *******************/ N#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ N N/****************** Bit definition for FLASH_OBR register *******************/ N#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ N#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ N N#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ N#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ N#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ N#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ N#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ N N/****************** Bit definition for FLASH_WRPR register ******************/ N#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ N N/*----------------------------------------------------------------------------*/ N N/****************** Bit definition for FLASH_RDP register *******************/ N#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ N#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ N N/****************** Bit definition for FLASH_USER register ******************/ N#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ N#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ N N/****************** Bit definition for FLASH_Data0 register *****************/ N#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ N#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ N N/****************** Bit definition for FLASH_Data1 register *****************/ N#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ N#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ N N/****************** Bit definition for FLASH_WRP0 register ******************/ N#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ N#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ N N/****************** Bit definition for FLASH_WRP1 register ******************/ N#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ N#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ N N/****************** Bit definition for FLASH_WRP2 register ******************/ N#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ N#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ N N/****************** Bit definition for FLASH_WRP3 register ******************/ N#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ N#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ N N#ifdef STM32F10X_CL S/******************************************************************************/ S/* Ethernet MAC Registers bits definitions */ S/******************************************************************************/ S/* Bit definition for Ethernet MAC Control Register register */ S#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ S#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ S#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ S #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ S #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ S #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ S #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ S #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ S #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ S #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ S #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ S#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ S#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ S#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ S#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ S#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ S#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ S#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ S#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ S#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling S a transmission attempt during retries after a collision: 0 =< r <2^k */ S #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ S #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ S #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ S #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ S#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ S#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ S#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ S S/* Bit definition for Ethernet MAC Frame Filter Register */ S#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ S#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ S#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ S#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ S#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ S #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ S #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ S #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ S#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ S#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ S#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ S#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ S#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ S#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ S S/* Bit definition for Ethernet MAC Hash Table High Register */ S#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ S S/* Bit definition for Ethernet MAC Hash Table Low Register */ S#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ S S/* Bit definition for Ethernet MAC MII Address Register */ S#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ S#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ S#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ S #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ S #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ S #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ S#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ S#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ S S/* Bit definition for Ethernet MAC MII Data Register */ S#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ S S/* Bit definition for Ethernet MAC Flow Control Register */ S#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ S#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ S#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ S #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ S #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ S #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ S #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ S#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ S#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ S#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ S#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ S S/* Bit definition for Ethernet MAC VLAN Tag Register */ S#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ S#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ S S/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ S#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ S/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. S Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ S/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask S Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask S Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask S Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask S Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - S RSVD - Filter1 Command - RSVD - Filter0 Command S Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset S Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 S Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ S S/* Bit definition for Ethernet MAC PMT Control and Status Register */ S#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ S#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ S#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ S#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ S#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ S#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ S#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ S S/* Bit definition for Ethernet MAC Status Register */ S#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ S#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ S#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ S#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ S#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ S S/* Bit definition for Ethernet MAC Interrupt Mask Register */ S#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ S#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ S S/* Bit definition for Ethernet MAC Address0 High Register */ S#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ S S/* Bit definition for Ethernet MAC Address0 Low Register */ S#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ S S/* Bit definition for Ethernet MAC Address1 High Register */ S#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ S#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ S#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ S #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ S #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ S #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ S #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ S #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ S #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ S#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ S S/* Bit definition for Ethernet MAC Address1 Low Register */ S#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ S S/* Bit definition for Ethernet MAC Address2 High Register */ S#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ S#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ S#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ S #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ S #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ S #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ S #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ S #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ S #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ S#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ S S/* Bit definition for Ethernet MAC Address2 Low Register */ S#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ S S/* Bit definition for Ethernet MAC Address3 High Register */ S#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ S#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ S#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ S #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ S #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ S #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ S #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ S #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ S #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ S#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ S S/* Bit definition for Ethernet MAC Address3 Low Register */ S#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ S S/******************************************************************************/ S/* Ethernet MMC Registers bits definition */ S/******************************************************************************/ S S/* Bit definition for Ethernet MMC Contol Register */ S#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ S#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ S#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ S#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ S S/* Bit definition for Ethernet MMC Receive Interrupt Register */ S#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ S#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ S#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Transmit Interrupt Register */ S#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ S#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ S#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ S#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ S#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ S#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ S#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ S#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ S#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ S#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ S S/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ S#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ S S/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ S#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ S S/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ S#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ S S/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ S#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ S S/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ S#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ S S/******************************************************************************/ S/* Ethernet PTP Registers bits definition */ S/******************************************************************************/ S S/* Bit definition for Ethernet PTP Time Stamp Contol Register */ S#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ S#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ S#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ S#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ S#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ S#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ S S/* Bit definition for Ethernet PTP Sub-Second Increment Register */ S#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ S S/* Bit definition for Ethernet PTP Time Stamp High Register */ S#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ S S/* Bit definition for Ethernet PTP Time Stamp Low Register */ S#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ S#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ S S/* Bit definition for Ethernet PTP Time Stamp High Update Register */ S#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ S S/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ S#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ S#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ S S/* Bit definition for Ethernet PTP Time Stamp Addend Register */ S#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ S S/* Bit definition for Ethernet PTP Target Time High Register */ S#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ S S/* Bit definition for Ethernet PTP Target Time Low Register */ S#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ S S/******************************************************************************/ S/* Ethernet DMA Registers bits definition */ S/******************************************************************************/ S S/* Bit definition for Ethernet DMA Bus Mode Register */ S#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ S#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ S#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ S#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ S #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ S #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ S #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ S #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ S #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ S #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ S #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ S #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ S #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ S #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ S #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ S #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ S#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ S#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ S#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ S #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ S #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ S #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ S #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ S #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ S #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ S #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ S #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ S #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ S #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ S #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ S #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ S#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ S#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ S#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ S S/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ S#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ S S/* Bit definition for Ethernet DMA Receive Poll Demand Register */ S#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ S S/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ S#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ S S/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ S#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ S S/* Bit definition for Ethernet DMA Status Register */ S#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ S#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ S#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ S#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ S /* combination with EBS[2:0] for GetFlagStatus function */ S #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ S #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ S #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ S#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ S #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ S #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ S #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ S #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ S #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ S #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ S#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ S #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ S #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ S #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ S #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ S #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ S #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ S#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ S#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ S#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ S#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ S#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ S#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ S#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ S#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ S#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ S#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ S#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ S#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ S#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ S#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ S#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ S S/* Bit definition for Ethernet DMA Operation Mode Register */ S#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ S#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ S#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ S#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ S#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ S#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ S #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ S #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ S #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ S #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ S #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ S #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ S #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ S #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ S#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ S#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ S#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ S#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ S #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ S #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ S #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ S #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ S#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ S#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ S S/* Bit definition for Ethernet DMA Interrupt Enable Register */ S#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ S#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ S#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ S#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ S#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ S#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ S#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ S#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ S#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ S#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ S#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ S#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ S#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ S#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ S#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ S S/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ S#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ S#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ S#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ S#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ S S/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ S#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ S S/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ S#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ S S/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ S#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ S S/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ S#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ N#endif /* STM32F10X_CL */ N N/** N * @} N */ N N /** N * @} N */ N N#ifdef USE_STDPERIPH_DRIVER N #include "stm32f10x_conf.h" L 1 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 1 N/** N ****************************************************************************** N * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h N * @author MCD Application Team N * @version V3.5.0 N * @date 08-April-2011 N * @brief Library configuration file. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_CONF_H N#define __STM32F10x_CONF_H N N/* Includes ------------------------------------------------------------------*/ N/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ N#include "stm32f10x_adc.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_adc.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the ADC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_ADC_H N#define __STM32F10x_ADC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" L 1 "..\..\template\Libraries\CMSIS\stm32f10x.h" 1 N/** N ****************************************************************************** N * @file stm32f10x.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. N * This file contains all the peripheral register's definitions, bits N * definitions and memory mapping for STM32F10x Connectivity line, N * High density, High density value line, Medium density, N * Medium density Value line, Low density, Low density Value line N * and XL-density devices. N * N * The file is the unique include file that the application programmer N * is using in the C source code, usually in main.c. This file contains: N * - Configuration section that allows to select: N * - The device used in the target application N * - To use or not the peripheral抯 drivers in application code(i.e. N * code will be based on direct access to peripheral抯 registers N * rather than drivers API), this option is controlled by N * "#define USE_STDPERIPH_DRIVER" N * - To change few application-specific parameters such as the HSE N * crystal frequency N * - Data structures and the address mapping for all peripherals N * - Peripheral's registers declarations and bits definition N * - Macros to access peripheral抯 registers hardware N * N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/** @addtogroup CMSIS N * @{ N */ N N/** @addtogroup stm32f10x N * @{ N */ N N#ifndef __STM32F10x_H S#define __STM32F10x_H S S#ifdef __cplusplus S extern "C" { S#endif S S/** @addtogroup Library_configuration_section S * @{ S */ S S/* Uncomment the line below according to the target STM32 device used in your S application S */ S S#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) S /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ S /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ S /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ S /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ S /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ S /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ S /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ S /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ S#endif S/* Tip: To avoid modifying this file each time you need to switch between these S devices, you can define the device in your toolchain compiler preprocessor. S S - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers S where the Flash memory density ranges between 16 and 32 Kbytes. S - Low-density value line devices are STM32F100xx microcontrollers where the Flash S memory density ranges between 16 and 32 Kbytes. S - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers S where the Flash memory density ranges between 64 and 128 Kbytes. S - Medium-density value line devices are STM32F100xx microcontrollers where the S Flash memory density ranges between 64 and 128 Kbytes. S - High-density devices are STM32F101xx and STM32F103xx microcontrollers where S the Flash memory density ranges between 256 and 512 Kbytes. S - High-density value line devices are STM32F100xx microcontrollers where the S Flash memory density ranges between 256 and 512 Kbytes. S - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where S the Flash memory density ranges between 512 and 1024 Kbytes. S - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. S */ S S#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) S #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" S#endif S S#if !defined USE_STDPERIPH_DRIVER S/** S * @brief Comment the line below if you will not use the peripherals drivers. S In this case, these drivers will not be included and the application code will S be based on direct access to peripherals registers S */ S /*#define USE_STDPERIPH_DRIVER*/ S#endif S S/** S * @brief In the following line adjust the value of External High Speed oscillator (HSE) S used in your application S S Tip: To avoid modifying this file each time you need to use different HSE, you S can define the HSE value in your toolchain compiler preprocessor. S */ S#if !defined HSE_VALUE S #ifdef STM32F10X_CL S #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ S #else S #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ S #endif /* STM32F10X_CL */ S#endif /* HSE_VALUE */ S S S/** S * @brief In the following line adjust the External High Speed oscillator (HSE) Startup S Timeout value S */ S#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ S S#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ S S/** S * @brief STM32F10x Standard Peripheral Library version number S */ S#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ S#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ S#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ S#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ S#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ S |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ S |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ S |(__STM32F10X_STDPERIPH_VERSION_RC)) X#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24) |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16) |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8) |(__STM32F10X_STDPERIPH_VERSION_RC)) S S/** S * @} S */ S S/** @addtogroup Configuration_section_for_CMSIS S * @{ S */ S S/** S * @brief Configuration of the Cortex-M3 Processor and Core Peripherals S */ S#ifdef STM32F10X_XL S #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ S#else S #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ S#endif /* STM32F10X_XL */ S#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ S#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ S S/** S * @brief STM32F10x Interrupt Number Definition, according to the selected device S * in @ref Library_configuration_section S */ Stypedef enum IRQn S{ S/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ S NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ S MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ S BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ S UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ S SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ S DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ S PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ S SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ S S/****** STM32 specific Interrupt Numbers *********************************************************/ S WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ S PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ S TAMPER_IRQn = 2, /*!< Tamper Interrupt */ S RTC_IRQn = 3, /*!< RTC global Interrupt */ S FLASH_IRQn = 4, /*!< FLASH global Interrupt */ S RCC_IRQn = 5, /*!< RCC global Interrupt */ S EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ S EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ S EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ S EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ S EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ S DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ S DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ S DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ S DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ S DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ S DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ S DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ S S#ifdef STM32F10X_LD S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ S#endif /* STM32F10X_LD */ S S#ifdef STM32F10X_LD_VL S ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ S TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ S TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ S TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ S TIM7_IRQn = 55 /*!< TIM7 Interrupt */ S#endif /* STM32F10X_LD_VL */ S S#ifdef STM32F10X_MD S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ S#endif /* STM32F10X_MD */ S S#ifdef STM32F10X_MD_VL S ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ S TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ S TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ S TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ S TIM7_IRQn = 55 /*!< TIM7 Interrupt */ S#endif /* STM32F10X_MD_VL */ S S#ifdef STM32F10X_HD S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ S TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ S TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ S TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ S TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ S ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ S FSMC_IRQn = 48, /*!< FSMC global Interrupt */ S SDIO_IRQn = 49, /*!< SDIO global Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ S#endif /* STM32F10X_HD */ S S#ifdef STM32F10X_HD_VL S ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ S TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ S TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ S TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ S TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ S TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ S DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is S mapped at position 60 only if the MISC_REMAP bit in S the AFIO_MAPR2 register is set) */ S#endif /* STM32F10X_HD_VL */ S S#ifdef STM32F10X_XL S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ S TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ S TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ S TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ S TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ S TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ S TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ S ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ S FSMC_IRQn = 48, /*!< FSMC global Interrupt */ S SDIO_IRQn = 49, /*!< SDIO global Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ S#endif /* STM32F10X_XL */ S S#ifdef STM32F10X_CL S ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ S CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ S CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ S USART1_IRQn = 37, /*!< USART1 global Interrupt */ S USART2_IRQn = 38, /*!< USART2 global Interrupt */ S USART3_IRQn = 39, /*!< USART3 global Interrupt */ S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ S OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ S UART4_IRQn = 52, /*!< UART4 global Interrupt */ S UART5_IRQn = 53, /*!< UART5 global Interrupt */ S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ S DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ S DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ S ETH_IRQn = 61, /*!< Ethernet global Interrupt */ S ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ S CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ S CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ S CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ S CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ S OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ S#endif /* STM32F10X_CL */ S} IRQn_Type; S S/** S * @} S */ S S#include "core_cm3.h" S#include "system_stm32f10x.h" S#include S S/** @addtogroup Exported_types S * @{ S */ S S/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ Stypedef int32_t s32; Stypedef int16_t s16; Stypedef int8_t s8; S Stypedef const int32_t sc32; /*!< Read Only */ Stypedef const int16_t sc16; /*!< Read Only */ Stypedef const int8_t sc8; /*!< Read Only */ S Stypedef __IO int32_t vs32; Stypedef __IO int16_t vs16; Stypedef __IO int8_t vs8; S Stypedef __I int32_t vsc32; /*!< Read Only */ Stypedef __I int16_t vsc16; /*!< Read Only */ Stypedef __I int8_t vsc8; /*!< Read Only */ S Stypedef uint32_t u32; Stypedef uint16_t u16; Stypedef uint8_t u8; S Stypedef const uint32_t uc32; /*!< Read Only */ Stypedef const uint16_t uc16; /*!< Read Only */ Stypedef const uint8_t uc8; /*!< Read Only */ S Stypedef __IO uint32_t vu32; Stypedef __IO uint16_t vu16; Stypedef __IO uint8_t vu8; S Stypedef __I uint32_t vuc32; /*!< Read Only */ Stypedef __I uint16_t vuc16; /*!< Read Only */ Stypedef __I uint8_t vuc8; /*!< Read Only */ S Stypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; S Stypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; S#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) S Stypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; S S/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ S#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT S#define HSE_Value HSE_VALUE S#define HSI_Value HSI_VALUE S/** S * @} S */ S S/** @addtogroup Peripheral_registers_structures S * @{ S */ S S/** S * @brief Analog to Digital Converter S */ S Stypedef struct S{ S __IO uint32_t SR; S __IO uint32_t CR1; S __IO uint32_t CR2; S __IO uint32_t SMPR1; S __IO uint32_t SMPR2; S __IO uint32_t JOFR1; S __IO uint32_t JOFR2; S __IO uint32_t JOFR3; S __IO uint32_t JOFR4; S __IO uint32_t HTR; S __IO uint32_t LTR; S __IO uint32_t SQR1; S __IO uint32_t SQR2; S __IO uint32_t SQR3; S __IO uint32_t JSQR; S __IO uint32_t JDR1; S __IO uint32_t JDR2; S __IO uint32_t JDR3; S __IO uint32_t JDR4; S __IO uint32_t DR; S} ADC_TypeDef; S S/** S * @brief Backup Registers S */ S Stypedef struct S{ S uint32_t RESERVED0; S __IO uint16_t DR1; S uint16_t RESERVED1; S __IO uint16_t DR2; S uint16_t RESERVED2; S __IO uint16_t DR3; S uint16_t RESERVED3; S __IO uint16_t DR4; S uint16_t RESERVED4; S __IO uint16_t DR5; S uint16_t RESERVED5; S __IO uint16_t DR6; S uint16_t RESERVED6; S __IO uint16_t DR7; S uint16_t RESERVED7; S __IO uint16_t DR8; S uint16_t RESERVED8; S __IO uint16_t DR9; S uint16_t RESERVED9; S __IO uint16_t DR10; S uint16_t RESERVED10; S __IO uint16_t RTCCR; S uint16_t RESERVED11; S __IO uint16_t CR; S uint16_t RESERVED12; S __IO uint16_t CSR; S uint16_t RESERVED13[5]; S __IO uint16_t DR11; S uint16_t RESERVED14; S __IO uint16_t DR12; S uint16_t RESERVED15; S __IO uint16_t DR13; S uint16_t RESERVED16; S __IO uint16_t DR14; S uint16_t RESERVED17; S __IO uint16_t DR15; S uint16_t RESERVED18; S __IO uint16_t DR16; S uint16_t RESERVED19; S __IO uint16_t DR17; S uint16_t RESERVED20; S __IO uint16_t DR18; S uint16_t RESERVED21; S __IO uint16_t DR19; S uint16_t RESERVED22; S __IO uint16_t DR20; S uint16_t RESERVED23; S __IO uint16_t DR21; S uint16_t RESERVED24; S __IO uint16_t DR22; S uint16_t RESERVED25; S __IO uint16_t DR23; S uint16_t RESERVED26; S __IO uint16_t DR24; S uint16_t RESERVED27; S __IO uint16_t DR25; S uint16_t RESERVED28; S __IO uint16_t DR26; S uint16_t RESERVED29; S __IO uint16_t DR27; S uint16_t RESERVED30; S __IO uint16_t DR28; S uint16_t RESERVED31; S __IO uint16_t DR29; S uint16_t RESERVED32; S __IO uint16_t DR30; S uint16_t RESERVED33; S __IO uint16_t DR31; S uint16_t RESERVED34; S __IO uint16_t DR32; S uint16_t RESERVED35; S __IO uint16_t DR33; S uint16_t RESERVED36; S __IO uint16_t DR34; S uint16_t RESERVED37; S __IO uint16_t DR35; S uint16_t RESERVED38; S __IO uint16_t DR36; S uint16_t RESERVED39; S __IO uint16_t DR37; S uint16_t RESERVED40; S __IO uint16_t DR38; S uint16_t RESERVED41; S __IO uint16_t DR39; S uint16_t RESERVED42; S __IO uint16_t DR40; S uint16_t RESERVED43; S __IO uint16_t DR41; S uint16_t RESERVED44; S __IO uint16_t DR42; S uint16_t RESERVED45; S} BKP_TypeDef; S S/** S * @brief Controller Area Network TxMailBox S */ S Stypedef struct S{ S __IO uint32_t TIR; S __IO uint32_t TDTR; S __IO uint32_t TDLR; S __IO uint32_t TDHR; S} CAN_TxMailBox_TypeDef; S S/** S * @brief Controller Area Network FIFOMailBox S */ S Stypedef struct S{ S __IO uint32_t RIR; S __IO uint32_t RDTR; S __IO uint32_t RDLR; S __IO uint32_t RDHR; S} CAN_FIFOMailBox_TypeDef; S S/** S * @brief Controller Area Network FilterRegister S */ S Stypedef struct S{ S __IO uint32_t FR1; S __IO uint32_t FR2; S} CAN_FilterRegister_TypeDef; S S/** S * @brief Controller Area Network S */ S Stypedef struct S{ S __IO uint32_t MCR; S __IO uint32_t MSR; S __IO uint32_t TSR; S __IO uint32_t RF0R; S __IO uint32_t RF1R; S __IO uint32_t IER; S __IO uint32_t ESR; S __IO uint32_t BTR; S uint32_t RESERVED0[88]; S CAN_TxMailBox_TypeDef sTxMailBox[3]; S CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; S uint32_t RESERVED1[12]; S __IO uint32_t FMR; S __IO uint32_t FM1R; S uint32_t RESERVED2; S __IO uint32_t FS1R; S uint32_t RESERVED3; S __IO uint32_t FFA1R; S uint32_t RESERVED4; S __IO uint32_t FA1R; S uint32_t RESERVED5[8]; S#ifndef STM32F10X_CL S CAN_FilterRegister_TypeDef sFilterRegister[14]; S#else S CAN_FilterRegister_TypeDef sFilterRegister[28]; S#endif /* STM32F10X_CL */ S} CAN_TypeDef; S S/** S * @brief Consumer Electronics Control (CEC) S */ Stypedef struct S{ S __IO uint32_t CFGR; S __IO uint32_t OAR; S __IO uint32_t PRES; S __IO uint32_t ESR; S __IO uint32_t CSR; S __IO uint32_t TXD; S __IO uint32_t RXD; S} CEC_TypeDef; S S/** S * @brief CRC calculation unit S */ S Stypedef struct S{ S __IO uint32_t DR; S __IO uint8_t IDR; S uint8_t RESERVED0; S uint16_t RESERVED1; S __IO uint32_t CR; S} CRC_TypeDef; S S/** S * @brief Digital to Analog Converter S */ S Stypedef struct S{ S __IO uint32_t CR; S __IO uint32_t SWTRIGR; S __IO uint32_t DHR12R1; S __IO uint32_t DHR12L1; S __IO uint32_t DHR8R1; S __IO uint32_t DHR12R2; S __IO uint32_t DHR12L2; S __IO uint32_t DHR8R2; S __IO uint32_t DHR12RD; S __IO uint32_t DHR12LD; S __IO uint32_t DHR8RD; S __IO uint32_t DOR1; S __IO uint32_t DOR2; S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S __IO uint32_t SR; S#endif S} DAC_TypeDef; S S/** S * @brief Debug MCU S */ S Stypedef struct S{ S __IO uint32_t IDCODE; S __IO uint32_t CR; S}DBGMCU_TypeDef; S S/** S * @brief DMA Controller S */ S Stypedef struct S{ S __IO uint32_t CCR; S __IO uint32_t CNDTR; S __IO uint32_t CPAR; S __IO uint32_t CMAR; S} DMA_Channel_TypeDef; S Stypedef struct S{ S __IO uint32_t ISR; S __IO uint32_t IFCR; S} DMA_TypeDef; S S/** S * @brief Ethernet MAC S */ S Stypedef struct S{ S __IO uint32_t MACCR; S __IO uint32_t MACFFR; S __IO uint32_t MACHTHR; S __IO uint32_t MACHTLR; S __IO uint32_t MACMIIAR; S __IO uint32_t MACMIIDR; S __IO uint32_t MACFCR; S __IO uint32_t MACVLANTR; /* 8 */ S uint32_t RESERVED0[2]; S __IO uint32_t MACRWUFFR; /* 11 */ S __IO uint32_t MACPMTCSR; S uint32_t RESERVED1[2]; S __IO uint32_t MACSR; /* 15 */ S __IO uint32_t MACIMR; S __IO uint32_t MACA0HR; S __IO uint32_t MACA0LR; S __IO uint32_t MACA1HR; S __IO uint32_t MACA1LR; S __IO uint32_t MACA2HR; S __IO uint32_t MACA2LR; S __IO uint32_t MACA3HR; S __IO uint32_t MACA3LR; /* 24 */ S uint32_t RESERVED2[40]; S __IO uint32_t MMCCR; /* 65 */ S __IO uint32_t MMCRIR; S __IO uint32_t MMCTIR; S __IO uint32_t MMCRIMR; S __IO uint32_t MMCTIMR; /* 69 */ S uint32_t RESERVED3[14]; S __IO uint32_t MMCTGFSCCR; /* 84 */ S __IO uint32_t MMCTGFMSCCR; S uint32_t RESERVED4[5]; S __IO uint32_t MMCTGFCR; S uint32_t RESERVED5[10]; S __IO uint32_t MMCRFCECR; S __IO uint32_t MMCRFAECR; S uint32_t RESERVED6[10]; S __IO uint32_t MMCRGUFCR; S uint32_t RESERVED7[334]; S __IO uint32_t PTPTSCR; S __IO uint32_t PTPSSIR; S __IO uint32_t PTPTSHR; S __IO uint32_t PTPTSLR; S __IO uint32_t PTPTSHUR; S __IO uint32_t PTPTSLUR; S __IO uint32_t PTPTSAR; S __IO uint32_t PTPTTHR; S __IO uint32_t PTPTTLR; S uint32_t RESERVED8[567]; S __IO uint32_t DMABMR; S __IO uint32_t DMATPDR; S __IO uint32_t DMARPDR; S __IO uint32_t DMARDLAR; S __IO uint32_t DMATDLAR; S __IO uint32_t DMASR; S __IO uint32_t DMAOMR; S __IO uint32_t DMAIER; S __IO uint32_t DMAMFBOCR; S uint32_t RESERVED9[9]; S __IO uint32_t DMACHTDR; S __IO uint32_t DMACHRDR; S __IO uint32_t DMACHTBAR; S __IO uint32_t DMACHRBAR; S} ETH_TypeDef; S S/** S * @brief External Interrupt/Event Controller S */ S Stypedef struct S{ S __IO uint32_t IMR; S __IO uint32_t EMR; S __IO uint32_t RTSR; S __IO uint32_t FTSR; S __IO uint32_t SWIER; S __IO uint32_t PR; S} EXTI_TypeDef; S S/** S * @brief FLASH Registers S */ S Stypedef struct S{ S __IO uint32_t ACR; S __IO uint32_t KEYR; S __IO uint32_t OPTKEYR; S __IO uint32_t SR; S __IO uint32_t CR; S __IO uint32_t AR; S __IO uint32_t RESERVED; S __IO uint32_t OBR; S __IO uint32_t WRPR; S#ifdef STM32F10X_XL S uint32_t RESERVED1[8]; S __IO uint32_t KEYR2; S uint32_t RESERVED2; S __IO uint32_t SR2; S __IO uint32_t CR2; S __IO uint32_t AR2; S#endif /* STM32F10X_XL */ S} FLASH_TypeDef; S S/** S * @brief Option Bytes Registers S */ S Stypedef struct S{ S __IO uint16_t RDP; S __IO uint16_t USER; S __IO uint16_t Data0; S __IO uint16_t Data1; S __IO uint16_t WRP0; S __IO uint16_t WRP1; S __IO uint16_t WRP2; S __IO uint16_t WRP3; S} OB_TypeDef; S S/** S * @brief Flexible Static Memory Controller S */ S Stypedef struct S{ S __IO uint32_t BTCR[8]; S} FSMC_Bank1_TypeDef; S S/** S * @brief Flexible Static Memory Controller Bank1E S */ S Stypedef struct S{ S __IO uint32_t BWTR[7]; S} FSMC_Bank1E_TypeDef; S S/** S * @brief Flexible Static Memory Controller Bank2 S */ S Stypedef struct S{ S __IO uint32_t PCR2; S __IO uint32_t SR2; S __IO uint32_t PMEM2; S __IO uint32_t PATT2; S uint32_t RESERVED0; S __IO uint32_t ECCR2; S} FSMC_Bank2_TypeDef; S S/** S * @brief Flexible Static Memory Controller Bank3 S */ S Stypedef struct S{ S __IO uint32_t PCR3; S __IO uint32_t SR3; S __IO uint32_t PMEM3; S __IO uint32_t PATT3; S uint32_t RESERVED0; S __IO uint32_t ECCR3; S} FSMC_Bank3_TypeDef; S S/** S * @brief Flexible Static Memory Controller Bank4 S */ S Stypedef struct S{ S __IO uint32_t PCR4; S __IO uint32_t SR4; S __IO uint32_t PMEM4; S __IO uint32_t PATT4; S __IO uint32_t PIO4; S} FSMC_Bank4_TypeDef; S S/** S * @brief General Purpose I/O S */ S Stypedef struct S{ S __IO uint32_t CRL; S __IO uint32_t CRH; S __IO uint32_t IDR; S __IO uint32_t ODR; S __IO uint32_t BSRR; S __IO uint32_t BRR; S __IO uint32_t LCKR; S} GPIO_TypeDef; S S/** S * @brief Alternate Function I/O S */ S Stypedef struct S{ S __IO uint32_t EVCR; S __IO uint32_t MAPR; S __IO uint32_t EXTICR[4]; S uint32_t RESERVED0; S __IO uint32_t MAPR2; S} AFIO_TypeDef; S/** S * @brief Inter Integrated Circuit Interface S */ S Stypedef struct S{ S __IO uint16_t CR1; S uint16_t RESERVED0; S __IO uint16_t CR2; S uint16_t RESERVED1; S __IO uint16_t OAR1; S uint16_t RESERVED2; S __IO uint16_t OAR2; S uint16_t RESERVED3; S __IO uint16_t DR; S uint16_t RESERVED4; S __IO uint16_t SR1; S uint16_t RESERVED5; S __IO uint16_t SR2; S uint16_t RESERVED6; S __IO uint16_t CCR; S uint16_t RESERVED7; S __IO uint16_t TRISE; S uint16_t RESERVED8; S} I2C_TypeDef; S S/** S * @brief Independent WATCHDOG S */ S Stypedef struct S{ S __IO uint32_t KR; S __IO uint32_t PR; S __IO uint32_t RLR; S __IO uint32_t SR; S} IWDG_TypeDef; S S/** S * @brief Power Control S */ S Stypedef struct S{ S __IO uint32_t CR; S __IO uint32_t CSR; S} PWR_TypeDef; S S/** S * @brief Reset and Clock Control S */ S Stypedef struct S{ S __IO uint32_t CR; S __IO uint32_t CFGR; S __IO uint32_t CIR; S __IO uint32_t APB2RSTR; S __IO uint32_t APB1RSTR; S __IO uint32_t AHBENR; S __IO uint32_t APB2ENR; S __IO uint32_t APB1ENR; S __IO uint32_t BDCR; S __IO uint32_t CSR; S S#ifdef STM32F10X_CL S __IO uint32_t AHBRSTR; S __IO uint32_t CFGR2; S#endif /* STM32F10X_CL */ S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S uint32_t RESERVED0; S __IO uint32_t CFGR2; S#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ S} RCC_TypeDef; S S/** S * @brief Real-Time Clock S */ S Stypedef struct S{ S __IO uint16_t CRH; S uint16_t RESERVED0; S __IO uint16_t CRL; S uint16_t RESERVED1; S __IO uint16_t PRLH; S uint16_t RESERVED2; S __IO uint16_t PRLL; S uint16_t RESERVED3; S __IO uint16_t DIVH; S uint16_t RESERVED4; S __IO uint16_t DIVL; S uint16_t RESERVED5; S __IO uint16_t CNTH; S uint16_t RESERVED6; S __IO uint16_t CNTL; S uint16_t RESERVED7; S __IO uint16_t ALRH; S uint16_t RESERVED8; S __IO uint16_t ALRL; S uint16_t RESERVED9; S} RTC_TypeDef; S S/** S * @brief SD host Interface S */ S Stypedef struct S{ S __IO uint32_t POWER; S __IO uint32_t CLKCR; S __IO uint32_t ARG; S __IO uint32_t CMD; S __I uint32_t RESPCMD; S __I uint32_t RESP1; S __I uint32_t RESP2; S __I uint32_t RESP3; S __I uint32_t RESP4; S __IO uint32_t DTIMER; S __IO uint32_t DLEN; S __IO uint32_t DCTRL; S __I uint32_t DCOUNT; S __I uint32_t STA; S __IO uint32_t ICR; S __IO uint32_t MASK; S uint32_t RESERVED0[2]; S __I uint32_t FIFOCNT; S uint32_t RESERVED1[13]; S __IO uint32_t FIFO; S} SDIO_TypeDef; S S/** S * @brief Serial Peripheral Interface S */ S Stypedef struct S{ S __IO uint16_t CR1; S uint16_t RESERVED0; S __IO uint16_t CR2; S uint16_t RESERVED1; S __IO uint16_t SR; S uint16_t RESERVED2; S __IO uint16_t DR; S uint16_t RESERVED3; S __IO uint16_t CRCPR; S uint16_t RESERVED4; S __IO uint16_t RXCRCR; S uint16_t RESERVED5; S __IO uint16_t TXCRCR; S uint16_t RESERVED6; S __IO uint16_t I2SCFGR; S uint16_t RESERVED7; S __IO uint16_t I2SPR; S uint16_t RESERVED8; S} SPI_TypeDef; S S/** S * @brief TIM S */ S Stypedef struct S{ S __IO uint16_t CR1; S uint16_t RESERVED0; S __IO uint16_t CR2; S uint16_t RESERVED1; S __IO uint16_t SMCR; S uint16_t RESERVED2; S __IO uint16_t DIER; S uint16_t RESERVED3; S __IO uint16_t SR; S uint16_t RESERVED4; S __IO uint16_t EGR; S uint16_t RESERVED5; S __IO uint16_t CCMR1; S uint16_t RESERVED6; S __IO uint16_t CCMR2; S uint16_t RESERVED7; S __IO uint16_t CCER; S uint16_t RESERVED8; S __IO uint16_t CNT; S uint16_t RESERVED9; S __IO uint16_t PSC; S uint16_t RESERVED10; S __IO uint16_t ARR; S uint16_t RESERVED11; S __IO uint16_t RCR; S uint16_t RESERVED12; S __IO uint16_t CCR1; S uint16_t RESERVED13; S __IO uint16_t CCR2; S uint16_t RESERVED14; S __IO uint16_t CCR3; S uint16_t RESERVED15; S __IO uint16_t CCR4; S uint16_t RESERVED16; S __IO uint16_t BDTR; S uint16_t RESERVED17; S __IO uint16_t DCR; S uint16_t RESERVED18; S __IO uint16_t DMAR; S uint16_t RESERVED19; S} TIM_TypeDef; S S/** S * @brief Universal Synchronous Asynchronous Receiver Transmitter S */ S Stypedef struct S{ S __IO uint16_t SR; S uint16_t RESERVED0; S __IO uint16_t DR; S uint16_t RESERVED1; S __IO uint16_t BRR; S uint16_t RESERVED2; S __IO uint16_t CR1; S uint16_t RESERVED3; S __IO uint16_t CR2; S uint16_t RESERVED4; S __IO uint16_t CR3; S uint16_t RESERVED5; S __IO uint16_t GTPR; S uint16_t RESERVED6; S} USART_TypeDef; S S/** S * @brief Window WATCHDOG S */ S Stypedef struct S{ S __IO uint32_t CR; S __IO uint32_t CFR; S __IO uint32_t SR; S} WWDG_TypeDef; S S/** S * @} S */ S S/** @addtogroup Peripheral_memory_map S * @{ S */ S S S#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ S#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ S#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ S S#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ S#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ S S#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ S S/*!< Peripheral memory map */ S#define APB1PERIPH_BASE PERIPH_BASE S#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) S#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) S S#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) S#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) S#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) S#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) S#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) S#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) S#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) S#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) S#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) S#define RTC_BASE (APB1PERIPH_BASE + 0x2800) S#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) S#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) S#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) S#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) S#define USART2_BASE (APB1PERIPH_BASE + 0x4400) S#define USART3_BASE (APB1PERIPH_BASE + 0x4800) S#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) S#define UART5_BASE (APB1PERIPH_BASE + 0x5000) S#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) S#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) S#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) S#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) S#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) S#define PWR_BASE (APB1PERIPH_BASE + 0x7000) S#define DAC_BASE (APB1PERIPH_BASE + 0x7400) S#define CEC_BASE (APB1PERIPH_BASE + 0x7800) S S#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) S#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) S#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) S#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) S#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) S#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) S#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) S#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) S#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) S#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) S#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) S#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) S#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) S#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) S#define USART1_BASE (APB2PERIPH_BASE + 0x3800) S#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) S#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) S#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) S#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) S#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) S#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) S#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) S S#define SDIO_BASE (PERIPH_BASE + 0x18000) S S#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) S#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) S#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) S#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) S#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) S#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) S#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) S#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) S#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) S#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) S#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) S#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) S#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) S#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) S#define RCC_BASE (AHBPERIPH_BASE + 0x1000) S#define CRC_BASE (AHBPERIPH_BASE + 0x3000) S S#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ S#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ S S#define ETH_BASE (AHBPERIPH_BASE + 0x8000) S#define ETH_MAC_BASE (ETH_BASE) S#define ETH_MMC_BASE (ETH_BASE + 0x0100) S#define ETH_PTP_BASE (ETH_BASE + 0x0700) S#define ETH_DMA_BASE (ETH_BASE + 0x1000) S S#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ S#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ S#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ S#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ S#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ S S#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ S S/** S * @} S */ S S/** @addtogroup Peripheral_declaration S * @{ S */ S S#define TIM2 ((TIM_TypeDef *) TIM2_BASE) S#define TIM3 ((TIM_TypeDef *) TIM3_BASE) S#define TIM4 ((TIM_TypeDef *) TIM4_BASE) S#define TIM5 ((TIM_TypeDef *) TIM5_BASE) S#define TIM6 ((TIM_TypeDef *) TIM6_BASE) S#define TIM7 ((TIM_TypeDef *) TIM7_BASE) S#define TIM12 ((TIM_TypeDef *) TIM12_BASE) S#define TIM13 ((TIM_TypeDef *) TIM13_BASE) S#define TIM14 ((TIM_TypeDef *) TIM14_BASE) S#define RTC ((RTC_TypeDef *) RTC_BASE) S#define WWDG ((WWDG_TypeDef *) WWDG_BASE) S#define IWDG ((IWDG_TypeDef *) IWDG_BASE) S#define SPI2 ((SPI_TypeDef *) SPI2_BASE) S#define SPI3 ((SPI_TypeDef *) SPI3_BASE) S#define USART2 ((USART_TypeDef *) USART2_BASE) S#define USART3 ((USART_TypeDef *) USART3_BASE) S#define UART4 ((USART_TypeDef *) UART4_BASE) S#define UART5 ((USART_TypeDef *) UART5_BASE) S#define I2C1 ((I2C_TypeDef *) I2C1_BASE) S#define I2C2 ((I2C_TypeDef *) I2C2_BASE) S#define CAN1 ((CAN_TypeDef *) CAN1_BASE) S#define CAN2 ((CAN_TypeDef *) CAN2_BASE) S#define BKP ((BKP_TypeDef *) BKP_BASE) S#define PWR ((PWR_TypeDef *) PWR_BASE) S#define DAC ((DAC_TypeDef *) DAC_BASE) S#define CEC ((CEC_TypeDef *) CEC_BASE) S#define AFIO ((AFIO_TypeDef *) AFIO_BASE) S#define EXTI ((EXTI_TypeDef *) EXTI_BASE) S#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) S#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) S#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) S#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) S#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) S#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) S#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) S#define ADC1 ((ADC_TypeDef *) ADC1_BASE) S#define ADC2 ((ADC_TypeDef *) ADC2_BASE) S#define TIM1 ((TIM_TypeDef *) TIM1_BASE) S#define SPI1 ((SPI_TypeDef *) SPI1_BASE) S#define TIM8 ((TIM_TypeDef *) TIM8_BASE) S#define USART1 ((USART_TypeDef *) USART1_BASE) S#define ADC3 ((ADC_TypeDef *) ADC3_BASE) S#define TIM15 ((TIM_TypeDef *) TIM15_BASE) S#define TIM16 ((TIM_TypeDef *) TIM16_BASE) S#define TIM17 ((TIM_TypeDef *) TIM17_BASE) S#define TIM9 ((TIM_TypeDef *) TIM9_BASE) S#define TIM10 ((TIM_TypeDef *) TIM10_BASE) S#define TIM11 ((TIM_TypeDef *) TIM11_BASE) S#define SDIO ((SDIO_TypeDef *) SDIO_BASE) S#define DMA1 ((DMA_TypeDef *) DMA1_BASE) S#define DMA2 ((DMA_TypeDef *) DMA2_BASE) S#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) S#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) S#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) S#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) S#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) S#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) S#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) S#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) S#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) S#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) S#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) S#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) S#define RCC ((RCC_TypeDef *) RCC_BASE) S#define CRC ((CRC_TypeDef *) CRC_BASE) S#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) S#define OB ((OB_TypeDef *) OB_BASE) S#define ETH ((ETH_TypeDef *) ETH_BASE) S#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) S#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) S#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) S#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) S#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) S#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) S S/** S * @} S */ S S/** @addtogroup Exported_constants S * @{ S */ S S /** @addtogroup Peripheral_Registers_Bits_Definition S * @{ S */ S S/******************************************************************************/ S/* Peripheral Registers_Bits_Definition */ S/******************************************************************************/ S S/******************************************************************************/ S/* */ S/* CRC calculation unit */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for CRC_DR register *********************/ S#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ S S S/******************* Bit definition for CRC_IDR register ********************/ S#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ S S S/******************** Bit definition for CRC_CR register ********************/ S#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ S S/******************************************************************************/ S/* */ S/* Power Control */ S/* */ S/******************************************************************************/ S S/******************** Bit definition for PWR_CR register ********************/ S#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ S#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ S#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ S#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ S#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ S S#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ S#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ S#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ S#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ S S/*!< PVD level configuration */ S#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ S#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ S#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ S#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ S#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ S#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ S#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ S#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ S S#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ S S S/******************* Bit definition for PWR_CSR register ********************/ S#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ S#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ S#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ S#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ S S/******************************************************************************/ S/* */ S/* Backup registers */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for BKP_DR1 register ********************/ S#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR2 register ********************/ S#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR3 register ********************/ S#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR4 register ********************/ S#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR5 register ********************/ S#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR6 register ********************/ S#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR7 register ********************/ S#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR8 register ********************/ S#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR9 register ********************/ S#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR10 register *******************/ S#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR11 register *******************/ S#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR12 register *******************/ S#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR13 register *******************/ S#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR14 register *******************/ S#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR15 register *******************/ S#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR16 register *******************/ S#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR17 register *******************/ S#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/****************** Bit definition for BKP_DR18 register ********************/ S#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR19 register *******************/ S#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR20 register *******************/ S#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR21 register *******************/ S#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR22 register *******************/ S#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR23 register *******************/ S#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR24 register *******************/ S#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR25 register *******************/ S#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR26 register *******************/ S#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR27 register *******************/ S#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR28 register *******************/ S#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR29 register *******************/ S#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR30 register *******************/ S#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR31 register *******************/ S#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR32 register *******************/ S#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR33 register *******************/ S#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR34 register *******************/ S#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR35 register *******************/ S#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR36 register *******************/ S#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR37 register *******************/ S#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR38 register *******************/ S#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR39 register *******************/ S#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR40 register *******************/ S#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR41 register *******************/ S#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/******************* Bit definition for BKP_DR42 register *******************/ S#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ S S/****************** Bit definition for BKP_RTCCR register *******************/ S#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ S#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ S#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ S#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ S S/******************** Bit definition for BKP_CR register ********************/ S#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ S#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ S S/******************* Bit definition for BKP_CSR register ********************/ S#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ S#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ S#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ S#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ S#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ S S/******************************************************************************/ S/* */ S/* Reset and Clock Control */ S/* */ S/******************************************************************************/ S S/******************** Bit definition for RCC_CR register ********************/ S#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ S#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ S#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ S#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ S#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ S#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ S#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ S#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ S#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ S#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ S S#ifdef STM32F10X_CL S #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ S #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ S #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ S #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ S#endif /* STM32F10X_CL */ S S/******************* Bit definition for RCC_CFGR register *******************/ S/*!< SW configuration */ S#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ S#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S S#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ S#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ S#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ S S/*!< SWS configuration */ S#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ S#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ S#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ S#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ S S/*!< HPRE configuration */ S#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ S#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ S#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ S#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ S#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ S#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ S#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ S#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ S#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ S#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ S S/*!< PPRE1 configuration */ S#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ S#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S S#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ S#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ S#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ S#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ S#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ S S/*!< PPRE2 configuration */ S#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ S#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ S#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ S#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ S S#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ S#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ S#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ S#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ S#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ S S/*!< ADCPPRE configuration */ S#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ S#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ S#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ S S#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ S#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ S#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ S#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ S S#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ S S#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ S S/*!< PLLMUL configuration */ S#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ S#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ S#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ S#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ S#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ S S#ifdef STM32F10X_CL S #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ S #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ S S #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ S #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ S S #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ S #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ S #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ S #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ S #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ S #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ S #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ S S #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ S S/*!< MCO configuration */ S #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ S #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ S #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ S #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ S #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ S #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ S #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ S #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ S #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ S #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ S#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ S #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ S S #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ S #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ S S #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ S #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ S #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ S #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ S #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ S #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ S #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ S #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ S #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ S #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ S #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ S #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ S #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ S #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ S #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ S S/*!< MCO configuration */ S #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ S #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S S #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ S #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ S #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ S #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ S #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ S#else S #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ S #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ S S #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ S #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ S S #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ S #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ S #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ S #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ S #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ S #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ S #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ S #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ S #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ S #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ S #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ S #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ S #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ S #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ S #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ S #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ S S/*!< MCO configuration */ S #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ S #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S S #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ S #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ S #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ S #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ S #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ S#endif /* STM32F10X_CL */ S S/*!<****************** Bit definition for RCC_CIR register ********************/ S#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ S#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ S#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ S#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ S#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ S#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ S#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ S#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ S#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ S#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ S#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ S#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ S#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ S#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ S#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ S#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ S#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ S S#ifdef STM32F10X_CL S #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ S #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ S #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ S #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ S #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ S #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ S#endif /* STM32F10X_CL */ S S/***************** Bit definition for RCC_APB2RSTR register *****************/ S#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ S#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ S#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ S#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ S#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ S#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ S S#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) S#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ S#endif S S#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ S#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ S#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ S#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ S#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ S#endif S S#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) S #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ S#endif /* STM32F10X_LD && STM32F10X_LD_VL */ S S#if defined (STM32F10X_HD) || defined (STM32F10X_XL) S #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ S #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ S #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ S #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ S#endif S S#if defined (STM32F10X_HD_VL) S #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ S #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ S#endif S S#ifdef STM32F10X_XL S #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ S #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ S #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ S#endif /* STM32F10X_XL */ S S/***************** Bit definition for RCC_APB1RSTR register *****************/ S#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ S#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ S#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ S#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ S#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ S S#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) S#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ S#endif S S#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ S#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ S S#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) S #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ S #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ S #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ S #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ S#endif /* STM32F10X_LD && STM32F10X_LD_VL */ S S#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) S #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ S#endif S S#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) S #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ S #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ S #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ S #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ S #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ S #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ S #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ S#endif S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ S #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ S #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ S #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ S#endif S S#if defined (STM32F10X_HD_VL) S #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ S #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ S #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ S #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ S #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ S #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ S #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ S#endif S S#ifdef STM32F10X_CL S #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ S#endif /* STM32F10X_CL */ S S#ifdef STM32F10X_XL S #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ S #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ S #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ S#endif /* STM32F10X_XL */ S S/****************** Bit definition for RCC_AHBENR register ******************/ S#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ S#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ S#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ S#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ S S#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) S #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ S#endif S S#if defined (STM32F10X_HD) || defined (STM32F10X_XL) S #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ S #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ S#endif S S#if defined (STM32F10X_HD_VL) S #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ S#endif S S#ifdef STM32F10X_CL S #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ S #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ S #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ S #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ S#endif /* STM32F10X_CL */ S S/****************** Bit definition for RCC_APB2ENR register *****************/ S#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ S#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ S#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ S#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ S#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ S#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ S S#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) S#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ S#endif S S#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ S#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ S#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ S#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ S#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ S#endif S S#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) S #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ S#endif /* STM32F10X_LD && STM32F10X_LD_VL */ S S#if defined (STM32F10X_HD) || defined (STM32F10X_XL) S #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ S #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ S #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ S #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ S#endif S S#if defined (STM32F10X_HD_VL) S #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ S #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ S#endif S S#ifdef STM32F10X_XL S #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ S #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ S #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ S#endif S S/***************** Bit definition for RCC_APB1ENR register ******************/ S#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ S#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ S#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ S#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ S#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ S S#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) S#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ S#endif S S#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ S#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ S S#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) S #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ S #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ S #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ S #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ S#endif /* STM32F10X_LD && STM32F10X_LD_VL */ S S#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) S #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ S#endif S S#if defined (STM32F10X_HD) || defined (STM32F10X_CL) S #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ S #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ S #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ S #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ S #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ S #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ S #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ S#endif S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ S #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ S #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ S #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ S#endif S S#ifdef STM32F10X_HD_VL S #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ S #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ S #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ S #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ S #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ S #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ S #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ S#endif /* STM32F10X_HD_VL */ S S#ifdef STM32F10X_CL S #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ S#endif /* STM32F10X_CL */ S S#ifdef STM32F10X_XL S #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ S #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ S #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ S#endif /* STM32F10X_XL */ S S/******************* Bit definition for RCC_BDCR register *******************/ S#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ S#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ S#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ S S#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ S#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S S/*!< RTC congiguration */ S#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ S#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ S#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ S#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ S S#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ S#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ S S/******************* Bit definition for RCC_CSR register ********************/ S#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ S#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ S#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ S#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ S#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ S#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ S#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ S#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ S#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ S S#ifdef STM32F10X_CL S/******************* Bit definition for RCC_AHBRSTR register ****************/ S #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ S #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ S S/******************* Bit definition for RCC_CFGR2 register ******************/ S/*!< PREDIV1 configuration */ S #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ S #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ S #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ S #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ S #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ S #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ S #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ S #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ S #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ S #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ S #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ S #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ S #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ S #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ S #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ S #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ S #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ S S/*!< PREDIV2 configuration */ S #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ S #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ S #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ S #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ S #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ S #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ S #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ S #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ S #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ S #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ S #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ S #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ S #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ S #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ S #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ S #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ S #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ S S/*!< PLL2MUL configuration */ S #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ S #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ S #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ S #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ S #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ S #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ S #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ S #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ S #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ S #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ S S/*!< PLL3MUL configuration */ S #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ S #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ S #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ S S #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ S #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ S #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ S #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ S #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ S #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ S #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ S #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ S #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ S S #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ S #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ S #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ S #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ S #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ S#endif /* STM32F10X_CL */ S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S/******************* Bit definition for RCC_CFGR2 register ******************/ S/*!< PREDIV1 configuration */ S #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ S #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ S #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ S #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ S #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ S #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ S #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ S #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ S #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ S #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ S #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ S #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ S #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ S #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ S #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ S #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ S #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ S#endif S S/******************************************************************************/ S/* */ S/* General Purpose and Alternate Function I/O */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for GPIO_CRL register *******************/ S#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ S S#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ S#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S S#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ S#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ S#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S S#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ S#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S S#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ S#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S S#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ S#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S S#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ S#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S S#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ S#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ S S#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ S#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ S#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S S#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ S#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S S#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ S#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ S#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ S S#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ S#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ S#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ S S#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ S#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ S#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ S S#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ S#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S S#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ S#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ S#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ S S/******************* Bit definition for GPIO_CRH register *******************/ S#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ S S#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ S#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S S#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ S#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ S#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S S#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ S#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S S#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ S#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S S#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ S#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S S#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ S#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S S#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ S#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ S S#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ S#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ S#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S S#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ S#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S S#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ S#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ S#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ S S#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ S#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ S#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ S S#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ S#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ S#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ S S#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ S#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S S#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ S#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ S#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ S S/*!<****************** Bit definition for GPIO_IDR register *******************/ S#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ S#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ S#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ S#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ S#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ S#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ S#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ S#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ S#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ S#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ S#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ S#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ S#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ S#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ S#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ S#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ S S/******************* Bit definition for GPIO_ODR register *******************/ S#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ S#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ S#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ S#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ S#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ S#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ S#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ S#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ S#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ S#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ S#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ S#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ S#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ S#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ S#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ S#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ S S/****************** Bit definition for GPIO_BSRR register *******************/ S#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ S#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ S#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ S#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ S#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ S#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ S#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ S#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ S#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ S#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ S#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ S#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ S#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ S#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ S#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ S#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ S S#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ S#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ S#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ S#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ S#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ S#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ S#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ S#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ S#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ S#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ S#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ S#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ S#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ S#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ S#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ S#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ S S/******************* Bit definition for GPIO_BRR register *******************/ S#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ S#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ S#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ S#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ S#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ S#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ S#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ S#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ S#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ S#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ S#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ S#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ S#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ S#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ S#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ S#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ S S/****************** Bit definition for GPIO_LCKR register *******************/ S#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ S#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ S#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ S#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ S#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ S#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ S#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ S#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ S#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ S#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ S#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ S#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ S#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ S#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ S#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ S#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ S#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ S S/*----------------------------------------------------------------------------*/ S S/****************** Bit definition for AFIO_EVCR register *******************/ S#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ S#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ S#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ S#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ S#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ S S/*!< PIN configuration */ S#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ S#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ S#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ S#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ S#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ S#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ S#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ S#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ S#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ S#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ S#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ S#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ S#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ S#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ S#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ S#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ S S#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ S#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ S#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ S#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ S S/*!< PORT configuration */ S#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ S#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ S#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ S#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ S#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ S S#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ S S/****************** Bit definition for AFIO_MAPR register *******************/ S#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ S#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ S#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ S#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ S S#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ S#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S/* USART3_REMAP configuration */ S#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ S#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ S#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ S S#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ S#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S S/*!< TIM1_REMAP configuration */ S#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ S#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ S#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ S S#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ S#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S S/*!< TIM2_REMAP configuration */ S#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ S#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ S#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ S#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ S S#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ S#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S S/*!< TIM3_REMAP configuration */ S#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ S#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ S#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ S S#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ S S#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ S#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ S#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ S S/*!< CAN_REMAP configuration */ S#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ S#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ S#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ S S#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ S#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ S#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ S#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ S#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ S#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ S S/*!< SWJ_CFG configuration */ S#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ S#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S S#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ S#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ S#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ S#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ S S#ifdef STM32F10X_CL S/*!< ETH_REMAP configuration */ S #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ S S/*!< CAN2_REMAP configuration */ S #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ S S/*!< MII_RMII_SEL configuration */ S #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ S S/*!< SPI3_REMAP configuration */ S #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ S S/*!< TIM2ITR1_IREMAP configuration */ S #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ S S/*!< PTP_PPS_REMAP configuration */ S #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ S#endif S S/***************** Bit definition for AFIO_EXTICR1 register *****************/ S#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ S#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ S#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ S#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ S S/*!< EXTI0 configuration */ S#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ S#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ S#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ S#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ S#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ S#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ S#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ S S/*!< EXTI1 configuration */ S#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ S#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ S#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ S#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ S#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ S#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ S#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ S S/*!< EXTI2 configuration */ S#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ S#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ S#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ S#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ S#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ S#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ S#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ S S/*!< EXTI3 configuration */ S#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ S#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ S#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ S#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ S#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ S#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ S#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ S S/***************** Bit definition for AFIO_EXTICR2 register *****************/ S#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ S#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ S#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ S#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ S S/*!< EXTI4 configuration */ S#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ S#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ S#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ S#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ S#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ S#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ S#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ S S/* EXTI5 configuration */ S#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ S#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ S#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ S#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ S#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ S#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ S#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ S S/*!< EXTI6 configuration */ S#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ S#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ S#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ S#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ S#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ S#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ S#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ S S/*!< EXTI7 configuration */ S#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ S#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ S#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ S#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ S#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ S#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ S#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ S S/***************** Bit definition for AFIO_EXTICR3 register *****************/ S#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ S#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ S#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ S#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ S S/*!< EXTI8 configuration */ S#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ S#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ S#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ S#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ S#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ S#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ S#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ S S/*!< EXTI9 configuration */ S#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ S#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ S#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ S#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ S#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ S#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ S#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ S S/*!< EXTI10 configuration */ S#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ S#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ S#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ S#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ S#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ S#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ S#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ S S/*!< EXTI11 configuration */ S#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ S#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ S#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ S#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ S#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ S#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ S#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ S S/***************** Bit definition for AFIO_EXTICR4 register *****************/ S#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ S#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ S#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ S#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ S S/* EXTI12 configuration */ S#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ S#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ S#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ S#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ S#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ S#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ S#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ S S/* EXTI13 configuration */ S#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ S#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ S#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ S#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ S#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ S#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ S#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ S S/*!< EXTI14 configuration */ S#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ S#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ S#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ S#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ S#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ S#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ S#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ S S/*!< EXTI15 configuration */ S#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ S#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ S#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ S#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ S#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ S#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ S#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ S S#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) S/****************** Bit definition for AFIO_MAPR2 register ******************/ S#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ S#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ S#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ S#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ S#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ S#endif S S#ifdef STM32F10X_HD_VL S#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ S#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ S#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ S#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ S#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ S#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ S#endif S S#ifdef STM32F10X_XL S/****************** Bit definition for AFIO_MAPR2 register ******************/ S#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ S#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ S#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ S#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ S#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ S#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ S#endif S S/******************************************************************************/ S/* */ S/* SystemTick */ S/* */ S/******************************************************************************/ S S/***************** Bit definition for SysTick_CTRL register *****************/ S#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ S#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ S#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ S#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ S S/***************** Bit definition for SysTick_LOAD register *****************/ S#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ S S/***************** Bit definition for SysTick_VAL register ******************/ S#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ S S/***************** Bit definition for SysTick_CALIB register ****************/ S#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ S#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ S#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ S S/******************************************************************************/ S/* */ S/* Nested Vectored Interrupt Controller */ S/* */ S/******************************************************************************/ S S/****************** Bit definition for NVIC_ISER register *******************/ S#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ S#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ S#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ S#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ S#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ S#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ S#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ S#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ S#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ S#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ S#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ S#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ S#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ S#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ S#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ S#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ S#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ S#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ S#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ S#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ S#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ S#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ S#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ S#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ S#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ S#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ S#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ S#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ S#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ S#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ S#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ S#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ S#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ S S/****************** Bit definition for NVIC_ICER register *******************/ S#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ S#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ S#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ S#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ S#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ S#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ S#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ S#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ S#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ S#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ S#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ S#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ S#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ S#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ S#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ S#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ S#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ S#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ S#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ S#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ S#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ S#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ S#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ S#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ S#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ S#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ S#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ S#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ S#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ S#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ S#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ S#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ S#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ S S/****************** Bit definition for NVIC_ISPR register *******************/ S#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ S#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ S#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ S#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ S#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ S#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ S#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ S#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ S#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ S#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ S#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ S#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ S#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ S#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ S#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ S#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ S#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ S#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ S#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ S#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ S#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ S#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ S#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ S#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ S#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ S#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ S#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ S#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ S#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ S#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ S#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ S#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ S#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ S S/****************** Bit definition for NVIC_ICPR register *******************/ S#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ S#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ S#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ S#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ S#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ S#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ S#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ S#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ S#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ S#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ S#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ S#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ S#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ S#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ S#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ S#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ S#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ S#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ S#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ S#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ S#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ S#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ S#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ S#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ S#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ S#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ S#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ S#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ S#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ S#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ S#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ S#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ S#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ S S/****************** Bit definition for NVIC_IABR register *******************/ S#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ S#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ S#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ S#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ S#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ S#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ S#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ S#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ S#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ S#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ S#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ S#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ S#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ S#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ S#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ S#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ S#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ S#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ S#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ S#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ S#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ S#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ S#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ S#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ S#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ S#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ S#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ S#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ S#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ S#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ S#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ S#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ S#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ S S/****************** Bit definition for NVIC_PRI0 register *******************/ S#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ S#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ S#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ S#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ S S/****************** Bit definition for NVIC_PRI1 register *******************/ S#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ S#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ S#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ S#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ S S/****************** Bit definition for NVIC_PRI2 register *******************/ S#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ S#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ S#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ S#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ S S/****************** Bit definition for NVIC_PRI3 register *******************/ S#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ S#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ S#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ S#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ S S/****************** Bit definition for NVIC_PRI4 register *******************/ S#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ S#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ S#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ S#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ S S/****************** Bit definition for NVIC_PRI5 register *******************/ S#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ S#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ S#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ S#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ S S/****************** Bit definition for NVIC_PRI6 register *******************/ S#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ S#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ S#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ S#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ S S/****************** Bit definition for NVIC_PRI7 register *******************/ S#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ S#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ S#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ S#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ S S/****************** Bit definition for SCB_CPUID register *******************/ S#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ S#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ S#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ S#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ S#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ S S/******************* Bit definition for SCB_ICSR register *******************/ S#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ S#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ S#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ S#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ S#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ S#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ S#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ S#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ S#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ S#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ S S/******************* Bit definition for SCB_VTOR register *******************/ S#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ S#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ S S/*!<***************** Bit definition for SCB_AIRCR register *******************/ S#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ S#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ S#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ S S#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ S#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S S/* prority group configuration */ S#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ S#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ S#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ S#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ S#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ S#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ S#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ S#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ S S#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ S#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ S S/******************* Bit definition for SCB_SCR register ********************/ S#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ S#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ S#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ S S/******************** Bit definition for SCB_CCR register *******************/ S#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ S#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ S#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ S#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ S#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ S#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ S S/******************* Bit definition for SCB_SHPR register ********************/ S#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ S#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ S#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ S#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ S S/****************** Bit definition for SCB_SHCSR register *******************/ S#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ S#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ S#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ S#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ S#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ S#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ S#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ S#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ S#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ S#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ S#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ S#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ S#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ S#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ S S/******************* Bit definition for SCB_CFSR register *******************/ S/*!< MFSR */ S#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ S#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ S#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ S#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ S#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ S/*!< BFSR */ S#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ S#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ S#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ S#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ S#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ S#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ S/*!< UFSR */ S#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ S#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ S#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ S#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ S#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ S#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ S S/******************* Bit definition for SCB_HFSR register *******************/ S#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ S#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ S#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ S S/******************* Bit definition for SCB_DFSR register *******************/ S#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ S#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ S#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ S#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ S#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ S S/******************* Bit definition for SCB_MMFAR register ******************/ S#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ S S/******************* Bit definition for SCB_BFAR register *******************/ S#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ S S/******************* Bit definition for SCB_afsr register *******************/ S#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ S S/******************************************************************************/ S/* */ S/* External Interrupt/Event Controller */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for EXTI_IMR register *******************/ S#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ S#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ S#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ S#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ S#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ S#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ S#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ S#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ S#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ S#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ S#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ S#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ S#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ S#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ S#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ S#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ S#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ S#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ S#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ S#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ S S/******************* Bit definition for EXTI_EMR register *******************/ S#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ S#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ S#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ S#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ S#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ S#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ S#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ S#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ S#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ S#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ S#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ S#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ S#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ S#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ S#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ S#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ S#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ S#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ S#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ S#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ S S/****************** Bit definition for EXTI_RTSR register *******************/ S#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ S#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ S#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ S#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ S#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ S#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ S#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ S#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ S#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ S#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ S#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ S#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ S#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ S#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ S#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ S#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ S#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ S#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ S#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ S#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ S S/****************** Bit definition for EXTI_FTSR register *******************/ S#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ S#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ S#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ S#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ S#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ S#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ S#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ S#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ S#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ S#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ S#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ S#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ S#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ S#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ S#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ S#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ S#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ S#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ S#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ S#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ S S/****************** Bit definition for EXTI_SWIER register ******************/ S#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ S#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ S#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ S#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ S#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ S#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ S#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ S#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ S#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ S#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ S#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ S#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ S#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ S#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ S#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ S#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ S#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ S#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ S#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ S#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ S S/******************* Bit definition for EXTI_PR register ********************/ S#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ S#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ S#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ S#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ S#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ S#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ S#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ S#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ S#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ S#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ S#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ S#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ S#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ S#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ S#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ S#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ S#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ S#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ S#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ S#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ S S/******************************************************************************/ S/* */ S/* DMA Controller */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for DMA_ISR register ********************/ S#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ S#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ S#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ S#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ S#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ S#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ S#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ S#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ S#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ S#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ S#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ S#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ S#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ S#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ S#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ S#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ S#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ S#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ S#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ S#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ S#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ S#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ S#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ S#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ S#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ S#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ S#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ S#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ S S/******************* Bit definition for DMA_IFCR register *******************/ S#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ S#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ S#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ S#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ S#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ S#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ S#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ S#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ S#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ S#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ S#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ S#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ S#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ S#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ S#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ S#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ S#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ S#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ S#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ S#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ S#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ S#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ S#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ S#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ S#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ S#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ S#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ S#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ S S/******************* Bit definition for DMA_CCR1 register *******************/ S#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ S#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ S#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ S S/******************* Bit definition for DMA_CCR2 register *******************/ S#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ S#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ S#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ S S/******************* Bit definition for DMA_CCR3 register *******************/ S#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ S#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ S#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ S S/*!<****************** Bit definition for DMA_CCR4 register *******************/ S#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ S#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ S#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ S S/****************** Bit definition for DMA_CCR5 register *******************/ S#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ S#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ S#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ S S/******************* Bit definition for DMA_CCR6 register *******************/ S#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ S#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ S#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ S S/******************* Bit definition for DMA_CCR7 register *******************/ S#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ S#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ S#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ S#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ S#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ S#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ S#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ S#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ S S#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ S#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ S#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ S#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ S S/****************** Bit definition for DMA_CNDTR1 register ******************/ S#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CNDTR2 register ******************/ S#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CNDTR3 register ******************/ S#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CNDTR4 register ******************/ S#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CNDTR5 register ******************/ S#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CNDTR6 register ******************/ S#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CNDTR7 register ******************/ S#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ S S/****************** Bit definition for DMA_CPAR1 register *******************/ S#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S/****************** Bit definition for DMA_CPAR2 register *******************/ S#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S/****************** Bit definition for DMA_CPAR3 register *******************/ S#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S S/****************** Bit definition for DMA_CPAR4 register *******************/ S#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S/****************** Bit definition for DMA_CPAR5 register *******************/ S#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S/****************** Bit definition for DMA_CPAR6 register *******************/ S#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S S/****************** Bit definition for DMA_CPAR7 register *******************/ S#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ S S/****************** Bit definition for DMA_CMAR1 register *******************/ S#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S/****************** Bit definition for DMA_CMAR2 register *******************/ S#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S/****************** Bit definition for DMA_CMAR3 register *******************/ S#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S S/****************** Bit definition for DMA_CMAR4 register *******************/ S#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S/****************** Bit definition for DMA_CMAR5 register *******************/ S#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S/****************** Bit definition for DMA_CMAR6 register *******************/ S#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S/****************** Bit definition for DMA_CMAR7 register *******************/ S#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ S S/******************************************************************************/ S/* */ S/* Analog to Digital Converter */ S/* */ S/******************************************************************************/ S S/******************** Bit definition for ADC_SR register ********************/ S#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ S#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ S#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ S#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ S#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ S S/******************* Bit definition for ADC_CR1 register ********************/ S#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ S#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S S#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ S#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ S#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ S#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ S#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ S#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ S#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ S#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ S S#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ S#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ S#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ S#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ S S#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ S#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S S#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ S#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ S S S/******************* Bit definition for ADC_CR2 register ********************/ S#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ S#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ S#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ S#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ S#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ S#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ S S#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ S#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ S S#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ S S#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ S#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ S#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ S#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ S S#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ S#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ S#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ S#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ S S/****************** Bit definition for ADC_SMPR1 register *******************/ S#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ S#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ S#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ S#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ S#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ S#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ S#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ S#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ S#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ S#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ S#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ S#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ S#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ S#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ S#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ S#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ S S#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ S#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ S#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ S#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ S S/****************** Bit definition for ADC_SMPR2 register *******************/ S#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ S#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ S#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ S#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ S#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ S#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ S#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ S#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ S#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ S#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ S#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ S#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ S#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ S#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ S#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ S#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ S#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ S#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ S#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ S#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ S#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ S#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S S#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ S#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ S#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ S#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ S S/****************** Bit definition for ADC_JOFR1 register *******************/ S#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ S S/****************** Bit definition for ADC_JOFR2 register *******************/ S#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ S S/****************** Bit definition for ADC_JOFR3 register *******************/ S#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ S S/****************** Bit definition for ADC_JOFR4 register *******************/ S#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ S S/******************* Bit definition for ADC_HTR register ********************/ S#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ S S/******************* Bit definition for ADC_LTR register ********************/ S#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ S S/******************* Bit definition for ADC_SQR1 register *******************/ S#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ S#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S S#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ S#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ S#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ S#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ S#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ S#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ S S#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ S#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ S#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ S#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ S#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ S#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ S#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ S S#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ S#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S/******************* Bit definition for ADC_SQR2 register *******************/ S#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ S#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S S#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ S#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ S#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ S#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ S#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ S#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ S S#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ S#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ S#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ S#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ S#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ S#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ S#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ S S#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ S#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ S S#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ S#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ S#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ S#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ S#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ S#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ S S/******************* Bit definition for ADC_SQR3 register *******************/ S#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ S#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S S#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ S#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ S#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ S#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ S#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ S#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ S S#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ S#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ S#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ S#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ S#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ S#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ S#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ S S#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ S#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ S S#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ S#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ S#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ S#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ S#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ S#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ S S/******************* Bit definition for ADC_JSQR register *******************/ S#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ S#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S S#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ S#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ S#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ S#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ S#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ S#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ S S#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ S#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ S#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ S#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ S#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ S#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ S#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ S S#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ S#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S S/******************* Bit definition for ADC_JDR1 register *******************/ S#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ S S/******************* Bit definition for ADC_JDR2 register *******************/ S#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ S S/******************* Bit definition for ADC_JDR3 register *******************/ S#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ S S/******************* Bit definition for ADC_JDR4 register *******************/ S#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ S S/******************** Bit definition for ADC_DR register ********************/ S#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ S#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ S S/******************************************************************************/ S/* */ S/* Digital to Analog Converter */ S/* */ S/******************************************************************************/ S S/******************** Bit definition for DAC_CR register ********************/ S#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ S#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ S#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ S S#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ S#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ S#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ S#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ S S#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ S#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S S#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ S#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ S#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ S#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ S#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ S S#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ S#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ S#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ S#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ S S#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ S#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ S#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ S S#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ S#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ S S/***************** Bit definition for DAC_SWTRIGR register ******************/ S#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ S#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ S S/***************** Bit definition for DAC_DHR12R1 register ******************/ S#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ S S/***************** Bit definition for DAC_DHR12L1 register ******************/ S#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ S S/****************** Bit definition for DAC_DHR8R1 register ******************/ S#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ S S/***************** Bit definition for DAC_DHR12R2 register ******************/ S#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ S S/***************** Bit definition for DAC_DHR12L2 register ******************/ S#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ S S/****************** Bit definition for DAC_DHR8R2 register ******************/ S#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ S S/***************** Bit definition for DAC_DHR12RD register ******************/ S#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ S#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ S S/***************** Bit definition for DAC_DHR12LD register ******************/ S#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ S#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ S S/****************** Bit definition for DAC_DHR8RD register ******************/ S#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ S#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ S S/******************* Bit definition for DAC_DOR1 register *******************/ S#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ S S/******************* Bit definition for DAC_DOR2 register *******************/ S#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ S S/******************** Bit definition for DAC_SR register ********************/ S#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ S#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ S S/******************************************************************************/ S/* */ S/* CEC */ S/* */ S/******************************************************************************/ S/******************** Bit definition for CEC_CFGR register ******************/ S#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ S#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ S#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ S#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ S S/******************** Bit definition for CEC_OAR register ******************/ S#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ S#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ S S/******************** Bit definition for CEC_PRES register ******************/ S#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ S S/******************** Bit definition for CEC_ESR register ******************/ S#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ S#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ S#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ S#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ S#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ S#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ S#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ S S/******************** Bit definition for CEC_CSR register ******************/ S#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ S#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ S#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ S#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ S#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ S#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ S#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ S#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ S S/******************** Bit definition for CEC_TXD register ******************/ S#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ S S/******************** Bit definition for CEC_RXD register ******************/ S#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ S S/******************************************************************************/ S/* */ S/* TIM */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for TIM_CR1 register ********************/ S#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ S#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ S#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ S#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ S#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ S S#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ S#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ S#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ S S#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ S S#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ S#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S/******************* Bit definition for TIM_CR2 register ********************/ S#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ S#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ S#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ S S#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ S#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ S S#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ S#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ S#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ S#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ S#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ S#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ S#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ S#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ S S/******************* Bit definition for TIM_SMCR register *******************/ S#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ S#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ S S#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ S#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ S S#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ S S#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ S#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ S#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ S#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ S S#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ S#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ S#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ S S/******************* Bit definition for TIM_DIER register *******************/ S#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ S#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ S#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ S#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ S#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ S#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ S#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ S#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ S#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ S#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ S#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ S#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ S#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ S#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ S#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ S S/******************** Bit definition for TIM_SR register ********************/ S#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ S#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ S#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ S#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ S#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ S#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ S#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ S#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ S#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ S#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ S#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ S#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ S S/******************* Bit definition for TIM_EGR register ********************/ S#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ S#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ S#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ S#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ S#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ S#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ S#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ S#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ S S/****************** Bit definition for TIM_CCMR1 register *******************/ S#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ S#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ S S#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ S#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ S S#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ S#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ S S#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ S S#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ S#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ S#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ S S#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ S#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ S#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ S S#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ S S/*----------------------------------------------------------------------------*/ S S#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ S#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ S#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ S S#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ S#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ S#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ S S#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ S#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ S#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ S#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ S#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ S S/****************** Bit definition for TIM_CCMR2 register *******************/ S#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ S#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ S S#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ S#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ S S#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ S#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ S S#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ S S#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ S#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ S#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ S S#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ S#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ S#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ S S#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ S S/*----------------------------------------------------------------------------*/ S S#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ S#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ S#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ S S#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ S#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ S#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ S S#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ S#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ S S#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ S#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ S#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ S#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ S S/******************* Bit definition for TIM_CCER register *******************/ S#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ S#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ S#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ S#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ S#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ S#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ S#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ S#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ S#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ S#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ S#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ S#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ S#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ S#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ S#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ S S/******************* Bit definition for TIM_CNT register ********************/ S#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ S S/******************* Bit definition for TIM_PSC register ********************/ S#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ S S/******************* Bit definition for TIM_ARR register ********************/ S#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ S S/******************* Bit definition for TIM_RCR register ********************/ S#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ S S/******************* Bit definition for TIM_CCR1 register *******************/ S#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ S S/******************* Bit definition for TIM_CCR2 register *******************/ S#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ S S/******************* Bit definition for TIM_CCR3 register *******************/ S#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ S S/******************* Bit definition for TIM_CCR4 register *******************/ S#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ S S/******************* Bit definition for TIM_BDTR register *******************/ S#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ S#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ S#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ S#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ S#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ S#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ S S#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ S#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ S#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ S#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ S#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ S#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ S#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ S S/******************* Bit definition for TIM_DCR register ********************/ S#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ S#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ S#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ S S#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ S#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ S#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ S#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ S#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ S S/******************* Bit definition for TIM_DMAR register *******************/ S#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ S S/******************************************************************************/ S/* */ S/* Real-Time Clock */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for RTC_CRH register ********************/ S#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ S#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ S#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ S S/******************* Bit definition for RTC_CRL register ********************/ S#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ S#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ S#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ S#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ S#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ S#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ S S/******************* Bit definition for RTC_PRLH register *******************/ S#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ S S/******************* Bit definition for RTC_PRLL register *******************/ S#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ S S/******************* Bit definition for RTC_DIVH register *******************/ S#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ S S/******************* Bit definition for RTC_DIVL register *******************/ S#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ S S/******************* Bit definition for RTC_CNTH register *******************/ S#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ S S/******************* Bit definition for RTC_CNTL register *******************/ S#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ S S/******************* Bit definition for RTC_ALRH register *******************/ S#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ S S/******************* Bit definition for RTC_ALRL register *******************/ S#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ S S/******************************************************************************/ S/* */ S/* Independent WATCHDOG */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for IWDG_KR register ********************/ S#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ S S/******************* Bit definition for IWDG_PR register ********************/ S#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ S#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ S#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ S#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ S S/******************* Bit definition for IWDG_RLR register *******************/ S#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ S S/******************* Bit definition for IWDG_SR register ********************/ S#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ S#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ S S/******************************************************************************/ S/* */ S/* Window WATCHDOG */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for WWDG_CR register ********************/ S#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ S#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ S#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ S#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ S#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ S#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ S#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ S#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ S S#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ S S/******************* Bit definition for WWDG_CFR register *******************/ S#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ S#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ S#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ S#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ S#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ S S#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ S#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ S#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ S S#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ S S/******************* Bit definition for WWDG_SR register ********************/ S#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ S S/******************************************************************************/ S/* */ S/* Flexible Static Memory Controller */ S/* */ S/******************************************************************************/ S S/****************** Bit definition for FSMC_BCR1 register *******************/ S#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ S#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ S S#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ S#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ S#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ S#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ S#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ S#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ S#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ S#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ S#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ S#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ S#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ S#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ S S/****************** Bit definition for FSMC_BCR2 register *******************/ S#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ S#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ S S#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ S#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ S#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ S#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ S#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ S#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ S#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ S#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ S#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ S#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ S#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ S#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ S S/****************** Bit definition for FSMC_BCR3 register *******************/ S#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ S#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ S S#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ S#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ S#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ S#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ S#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ S#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ S#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ S#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ S#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ S#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ S#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ S#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ S S/****************** Bit definition for FSMC_BCR4 register *******************/ S#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ S#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ S S#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ S#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ S#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ S S#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ S#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ S#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ S#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ S#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ S#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ S#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ S#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ S#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ S#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ S#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ S S/****************** Bit definition for FSMC_BTR1 register ******************/ S#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ S#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S S#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_BTR2 register *******************/ S#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ S#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S S#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/******************* Bit definition for FSMC_BTR3 register *******************/ S#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ S#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S S#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_BTR4 register *******************/ S#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ S#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S S#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_BWTR1 register ******************/ S#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_BWTR2 register ******************/ S#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ S#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_BWTR3 register ******************/ S#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_BWTR4 register ******************/ S#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ S#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S S#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ S#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ S S#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ S#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S S#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ S#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ S#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ S#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ S#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ S S#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ S#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S S#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ S#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ S#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ S S/****************** Bit definition for FSMC_PCR2 register *******************/ S#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ S#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ S#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ S S#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ S#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ S S#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ S#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ S#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ S#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ S#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ S S#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ S#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ S#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ S#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ S#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ S S#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ S#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ S#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ S#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ S S/****************** Bit definition for FSMC_PCR3 register *******************/ S#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ S#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ S#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ S S#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ S#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ S S#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ S#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ S#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ S#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ S#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ S S#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ S#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ S#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ S#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ S#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ S S#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ S#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ S#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ S#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ S S/****************** Bit definition for FSMC_PCR4 register *******************/ S#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ S#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ S#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ S S#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ S#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S S#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ S S#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ S#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ S#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ S#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ S#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ S S#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ S#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ S#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ S#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ S#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ S S#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ S#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ S#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ S#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ S S/******************* Bit definition for FSMC_SR2 register *******************/ S#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ S#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ S#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ S#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ S#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ S#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ S#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ S S/******************* Bit definition for FSMC_SR3 register *******************/ S#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ S#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ S#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ S#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ S#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ S#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ S#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ S S/******************* Bit definition for FSMC_SR4 register *******************/ S#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ S#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ S#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ S#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ S#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ S#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ S#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ S S/****************** Bit definition for FSMC_PMEM2 register ******************/ S#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ S#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ S#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ S#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ S#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_PMEM3 register ******************/ S#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ S#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ S#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ S#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ S#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_PMEM4 register ******************/ S#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ S#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ S#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ S#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ S#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_PATT2 register ******************/ S#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ S#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ S#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ S#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ S#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_PATT3 register ******************/ S#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ S#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ S#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ S#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ S#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_PATT4 register ******************/ S#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ S#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ S#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ S#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ S#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_PIO4 register *******************/ S#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ S#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ S#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ S#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ S#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ S#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ S#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ S#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ S#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ S S#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ S#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ S#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ S#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ S#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ S#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ S#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ S#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ S#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ S S#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ S#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S S#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ S#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ S#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ S#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ S#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ S#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ S#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ S#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ S#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ S S/****************** Bit definition for FSMC_ECCR2 register ******************/ S#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ S S/****************** Bit definition for FSMC_ECCR3 register ******************/ S#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ S S/******************************************************************************/ S/* */ S/* SD host Interface */ S/* */ S/******************************************************************************/ S S/****************** Bit definition for SDIO_POWER register ******************/ S#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ S#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ S#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ S S/****************** Bit definition for SDIO_CLKCR register ******************/ S#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ S#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ S#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ S#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ S S#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ S#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ S#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ S S#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ S#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ S S/******************* Bit definition for SDIO_ARG register *******************/ S#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ S S/******************* Bit definition for SDIO_CMD register *******************/ S#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ S S#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ S#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ S#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ S S#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ S#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ S#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ S#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ S#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ S#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ S#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ S S/***************** Bit definition for SDIO_RESPCMD register *****************/ S#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ S S/****************** Bit definition for SDIO_RESP0 register ******************/ S#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ S S/****************** Bit definition for SDIO_RESP1 register ******************/ S#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ S S/****************** Bit definition for SDIO_RESP2 register ******************/ S#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ S S/****************** Bit definition for SDIO_RESP3 register ******************/ S#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ S S/****************** Bit definition for SDIO_RESP4 register ******************/ S#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ S S/****************** Bit definition for SDIO_DTIMER register *****************/ S#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ S S/****************** Bit definition for SDIO_DLEN register *******************/ S#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ S S/****************** Bit definition for SDIO_DCTRL register ******************/ S#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ S#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ S#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ S#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ S S#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ S#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ S#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ S#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ S S#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ S#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ S#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ S#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ S S/****************** Bit definition for SDIO_DCOUNT register *****************/ S#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ S S/****************** Bit definition for SDIO_STA register ********************/ S#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ S#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ S#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ S#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ S#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ S#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ S#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ S#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ S#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ S#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ S#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ S#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ S#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ S#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ S#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ S#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ S#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ S#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ S#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ S#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ S#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ S#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ S#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ S#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ S S/******************* Bit definition for SDIO_ICR register *******************/ S#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ S#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ S#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ S#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ S#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ S#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ S#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ S#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ S#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ S#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ S#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ S#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ S#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ S S/****************** Bit definition for SDIO_MASK register *******************/ S#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ S#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ S#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ S#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ S#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ S#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ S#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ S#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ S#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ S#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ S#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ S#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ S#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ S#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ S#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ S#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ S#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ S#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ S#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ S#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ S#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ S#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ S#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ S#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ S S/***************** Bit definition for SDIO_FIFOCNT register *****************/ S#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ S S/****************** Bit definition for SDIO_FIFO register *******************/ S#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ S S/******************************************************************************/ S/* */ S/* USB Device FS */ S/* */ S/******************************************************************************/ S S/*!< Endpoint-specific registers */ S/******************* Bit definition for USB_EP0R register *******************/ S#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP1R register *******************/ S#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP2R register *******************/ S#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP3R register *******************/ S#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP4R register *******************/ S#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP5R register *******************/ S#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP6R register *******************/ S#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/******************* Bit definition for USB_EP7R register *******************/ S#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ S S#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ S#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ S#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ S#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ S S#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ S#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ S#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ S S#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ S S#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ S#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ S#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ S S/*!< Common registers */ S/******************* Bit definition for USB_CNTR register *******************/ S#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ S#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ S#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ S#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ S#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ S#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ S#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ S#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ S#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ S#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ S#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ S#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ S#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ S S/******************* Bit definition for USB_ISTR register *******************/ S#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ S#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ S#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ S#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ S#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ S#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ S#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ S#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ S#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ S#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ S S/******************* Bit definition for USB_FNR register ********************/ S#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ S#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ S#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ S#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ S#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ S S/****************** Bit definition for USB_DADDR register *******************/ S#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ S#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ S#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ S#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ S#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ S#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ S#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ S#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ S S#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ S S/****************** Bit definition for USB_BTABLE register ******************/ S#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ S S/*!< Buffer descriptor table */ S/***************** Bit definition for USB_ADDR0_TX register *****************/ S#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ S S/***************** Bit definition for USB_ADDR1_TX register *****************/ S#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ S S/***************** Bit definition for USB_ADDR2_TX register *****************/ S#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ S S/***************** Bit definition for USB_ADDR3_TX register *****************/ S#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ S S/***************** Bit definition for USB_ADDR4_TX register *****************/ S#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ S S/***************** Bit definition for USB_ADDR5_TX register *****************/ S#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ S S/***************** Bit definition for USB_ADDR6_TX register *****************/ S#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ S S/***************** Bit definition for USB_ADDR7_TX register *****************/ S#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ S S/*----------------------------------------------------------------------------*/ S S/***************** Bit definition for USB_COUNT0_TX register ****************/ S#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ S S/***************** Bit definition for USB_COUNT1_TX register ****************/ S#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ S S/***************** Bit definition for USB_COUNT2_TX register ****************/ S#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ S S/***************** Bit definition for USB_COUNT3_TX register ****************/ S#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ S S/***************** Bit definition for USB_COUNT4_TX register ****************/ S#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ S S/***************** Bit definition for USB_COUNT5_TX register ****************/ S#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ S S/***************** Bit definition for USB_COUNT6_TX register ****************/ S#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ S S/***************** Bit definition for USB_COUNT7_TX register ****************/ S#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ S S/*----------------------------------------------------------------------------*/ S S/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ S#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ S S/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ S#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ S S/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ S#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ S S/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ S#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ S S/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ S#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ S S/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ S#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ S S/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ S#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ S S/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ S#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ S S/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ S#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ S S/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ S#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ S S/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ S#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ S S/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ S#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ S S/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ S#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ S S/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ S#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ S S/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ S#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ S S/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ S#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ S S/*----------------------------------------------------------------------------*/ S S/***************** Bit definition for USB_ADDR0_RX register *****************/ S#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ S S/***************** Bit definition for USB_ADDR1_RX register *****************/ S#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ S S/***************** Bit definition for USB_ADDR2_RX register *****************/ S#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ S S/***************** Bit definition for USB_ADDR3_RX register *****************/ S#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ S S/***************** Bit definition for USB_ADDR4_RX register *****************/ S#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ S S/***************** Bit definition for USB_ADDR5_RX register *****************/ S#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ S S/***************** Bit definition for USB_ADDR6_RX register *****************/ S#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ S S/***************** Bit definition for USB_ADDR7_RX register *****************/ S#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ S S/*----------------------------------------------------------------------------*/ S S/***************** Bit definition for USB_COUNT0_RX register ****************/ S#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT1_RX register ****************/ S#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT2_RX register ****************/ S#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT3_RX register ****************/ S#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT4_RX register ****************/ S#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT5_RX register ****************/ S#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT6_RX register ****************/ S#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/***************** Bit definition for USB_COUNT7_RX register ****************/ S#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ S S#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ S#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ S#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ S#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ S#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ S#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ S S#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ S S/*----------------------------------------------------------------------------*/ S S/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ S#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ S#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ S#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ S#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ S#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ S#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ S#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ S#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ S#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ S#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ S#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ S#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ S#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ S#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ S#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ S#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ S S#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ S#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ S#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ S#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ S#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ S#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ S S#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ S S/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ S#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ S S#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ S#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ S#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ S#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ S#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ S#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ S S#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ S S/******************************************************************************/ S/* */ S/* Controller Area Network */ S/* */ S/******************************************************************************/ S S/*!< CAN control and status registers */ S/******************* Bit definition for CAN_MCR register ********************/ S#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ S#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ S#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ S#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ S#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ S#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ S#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ S#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ S#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ S S/******************* Bit definition for CAN_MSR register ********************/ S#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ S#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ S#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ S#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ S#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ S#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ S#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ S#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ S#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ S S/******************* Bit definition for CAN_TSR register ********************/ S#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ S#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ S#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ S#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ S#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ S#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ S#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ S#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ S#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ S#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ S#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ S#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ S#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ S#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ S#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ S#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ S S#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ S#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ S#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ S#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ S S#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ S#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ S#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ S#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ S S/******************* Bit definition for CAN_RF0R register *******************/ S#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ S#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ S#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ S#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ S S/******************* Bit definition for CAN_RF1R register *******************/ S#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ S#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ S#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ S#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ S S/******************** Bit definition for CAN_IER register *******************/ S#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ S#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ S#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ S#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ S#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ S#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ S#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ S#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ S#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ S#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ S#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ S#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ S#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ S#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ S S/******************** Bit definition for CAN_ESR register *******************/ S#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ S#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ S#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ S S#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ S#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ S#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ S#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ S S#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ S#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ S S/******************* Bit definition for CAN_BTR register ********************/ S#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ S#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ S#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ S#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ S#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ S#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ S S/*!< Mailbox registers */ S/****************** Bit definition for CAN_TI0R register ********************/ S#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ S#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ S#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ S#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ S#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ S S/****************** Bit definition for CAN_TDT0R register *******************/ S#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ S#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ S#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ S S/****************** Bit definition for CAN_TDL0R register *******************/ S#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ S#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ S#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ S#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ S S/****************** Bit definition for CAN_TDH0R register *******************/ S#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ S#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ S#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ S#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ S S/******************* Bit definition for CAN_TI1R register *******************/ S#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ S#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ S#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ S#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ S#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ S S/******************* Bit definition for CAN_TDT1R register ******************/ S#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ S#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ S#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ S S/******************* Bit definition for CAN_TDL1R register ******************/ S#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ S#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ S#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ S#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ S S/******************* Bit definition for CAN_TDH1R register ******************/ S#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ S#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ S#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ S#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ S S/******************* Bit definition for CAN_TI2R register *******************/ S#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ S#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ S#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ S#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ S#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ S S/******************* Bit definition for CAN_TDT2R register ******************/ S#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ S#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ S#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ S S/******************* Bit definition for CAN_TDL2R register ******************/ S#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ S#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ S#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ S#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ S S/******************* Bit definition for CAN_TDH2R register ******************/ S#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ S#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ S#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ S#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ S S/******************* Bit definition for CAN_RI0R register *******************/ S#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ S#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ S#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ S#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ S S/******************* Bit definition for CAN_RDT0R register ******************/ S#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ S#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ S#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ S S/******************* Bit definition for CAN_RDL0R register ******************/ S#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ S#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ S#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ S#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ S S/******************* Bit definition for CAN_RDH0R register ******************/ S#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ S#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ S#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ S#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ S S/******************* Bit definition for CAN_RI1R register *******************/ S#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ S#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ S#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ S#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ S S/******************* Bit definition for CAN_RDT1R register ******************/ S#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ S#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ S#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ S S/******************* Bit definition for CAN_RDL1R register ******************/ S#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ S#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ S#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ S#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ S S/******************* Bit definition for CAN_RDH1R register ******************/ S#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ S#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ S#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ S#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ S S/*!< CAN filter registers */ S/******************* Bit definition for CAN_FMR register ********************/ S#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ S S/******************* Bit definition for CAN_FM1R register *******************/ S#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ S#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ S#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ S#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ S#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ S#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ S#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ S#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ S#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ S#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ S#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ S#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ S#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ S#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ S#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ S S/******************* Bit definition for CAN_FS1R register *******************/ S#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ S#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ S#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ S#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ S#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ S#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ S#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ S#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ S#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ S#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ S#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ S#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ S#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ S#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ S#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ S S/****************** Bit definition for CAN_FFA1R register *******************/ S#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ S#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ S#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ S#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ S#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ S#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ S#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ S#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ S#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ S#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ S#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ S#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ S#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ S#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ S#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ S S/******************* Bit definition for CAN_FA1R register *******************/ S#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ S#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ S#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ S#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ S#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ S#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ S#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ S#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ S#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ S#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ S#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ S#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ S#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ S#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ S#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ S S/******************* Bit definition for CAN_F0R1 register *******************/ S#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F1R1 register *******************/ S#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F2R1 register *******************/ S#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F3R1 register *******************/ S#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F4R1 register *******************/ S#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F5R1 register *******************/ S#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F6R1 register *******************/ S#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F7R1 register *******************/ S#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F8R1 register *******************/ S#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F9R1 register *******************/ S#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F10R1 register ******************/ S#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F11R1 register ******************/ S#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F12R1 register ******************/ S#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F13R1 register ******************/ S#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F0R2 register *******************/ S#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F1R2 register *******************/ S#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F2R2 register *******************/ S#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F3R2 register *******************/ S#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F4R2 register *******************/ S#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F5R2 register *******************/ S#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F6R2 register *******************/ S#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F7R2 register *******************/ S#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F8R2 register *******************/ S#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F9R2 register *******************/ S#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F10R2 register ******************/ S#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F11R2 register ******************/ S#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F12R2 register ******************/ S#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************* Bit definition for CAN_F13R2 register ******************/ S#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ S#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ S#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ S#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ S#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ S#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ S#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ S#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ S#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ S#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ S#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ S#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ S#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ S#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ S#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ S#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ S#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ S#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ S#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ S#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ S#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ S#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ S#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ S#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ S#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ S#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ S#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ S#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ S#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ S#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ S#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ S#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ S S/******************************************************************************/ S/* */ S/* Serial Peripheral Interface */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for SPI_CR1 register ********************/ S#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ S#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ S#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ S S#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ S#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ S#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ S#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ S S#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ S#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ S#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ S#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ S#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ S#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ S#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ S#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ S#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ S#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ S S/******************* Bit definition for SPI_CR2 register ********************/ S#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ S#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ S#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ S#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ S#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ S#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ S S/******************** Bit definition for SPI_SR register ********************/ S#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ S#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ S#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ S#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ S#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ S#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ S#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ S#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ S S/******************** Bit definition for SPI_DR register ********************/ S#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ S S/******************* Bit definition for SPI_CRCPR register ******************/ S#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ S S/****************** Bit definition for SPI_RXCRCR register ******************/ S#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ S S/****************** Bit definition for SPI_TXCRCR register ******************/ S#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ S S/****************** Bit definition for SPI_I2SCFGR register *****************/ S#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ S S#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ S#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ S#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ S S#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ S S#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ S#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ S#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ S S#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ S S#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ S#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ S#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ S S#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ S#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ S S/****************** Bit definition for SPI_I2SPR register *******************/ S#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ S#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ S#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ S S/******************************************************************************/ S/* */ S/* Inter-integrated Circuit Interface */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for I2C_CR1 register ********************/ S#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ S#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ S#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ S#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ S#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ S#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ S#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ S#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ S#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ S#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ S#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ S#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ S#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ S#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ S S/******************* Bit definition for I2C_CR2 register ********************/ S#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ S#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ S#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ S#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ S S#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ S#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ S#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ S#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ S#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ S S/******************* Bit definition for I2C_OAR1 register *******************/ S#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ S#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ S S#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ S#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ S#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ S#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ S#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ S#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ S#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ S S#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ S S/******************* Bit definition for I2C_OAR2 register *******************/ S#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ S#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ S S/******************** Bit definition for I2C_DR register ********************/ S#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ S S/******************* Bit definition for I2C_SR1 register ********************/ S#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ S#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ S#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ S#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ S#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ S#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ S#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ S#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ S#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ S#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ S#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ S#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ S#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ S#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ S S/******************* Bit definition for I2C_SR2 register ********************/ S#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ S#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ S#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ S#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ S#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ S#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ S#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ S#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ S S/******************* Bit definition for I2C_CCR register ********************/ S#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ S#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ S#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ S S/****************** Bit definition for I2C_TRISE register *******************/ S#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ S S/******************************************************************************/ S/* */ S/* Universal Synchronous Asynchronous Receiver Transmitter */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for USART_SR register *******************/ S#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ S#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ S#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ S#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ S#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ S#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ S#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ S#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ S#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ S#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ S S/******************* Bit definition for USART_DR register *******************/ S#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ S S/****************** Bit definition for USART_BRR register *******************/ S#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ S#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ S S/****************** Bit definition for USART_CR1 register *******************/ S#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ S#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ S#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ S#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ S#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ S#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ S#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ S#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ S#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ S#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ S#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ S#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ S#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ S#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ S#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ S S/****************** Bit definition for USART_CR2 register *******************/ S#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ S#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ S#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ S#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ S#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ S#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ S#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ S S#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ S#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ S#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ S S#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ S S/****************** Bit definition for USART_CR3 register *******************/ S#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ S#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ S#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ S#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ S#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ S#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ S#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ S#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ S#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ S#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ S#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ S#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ S S/****************** Bit definition for USART_GTPR register ******************/ S#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ S#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ S#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ S#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ S#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ S#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ S#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ S#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ S#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ S S#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ S S/******************************************************************************/ S/* */ S/* Debug MCU */ S/* */ S/******************************************************************************/ S S/**************** Bit definition for DBGMCU_IDCODE register *****************/ S#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ S S#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ S#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ S#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ S#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ S#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ S#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ S#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ S#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ S#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ S#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ S#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ S#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ S#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ S#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ S#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ S#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ S#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ S S/****************** Bit definition for DBGMCU_CR register *******************/ S#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ S#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ S#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ S#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ S S#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ S#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ S#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ S S#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ S#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ S#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ S#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ S#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ S#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ S S/******************************************************************************/ S/* */ S/* FLASH and Option Bytes Registers */ S/* */ S/******************************************************************************/ S S/******************* Bit definition for FLASH_ACR register ******************/ S#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ S#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ S#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ S#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ S S#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ S#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ S#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ S S/****************** Bit definition for FLASH_KEYR register ******************/ S#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ S S/***************** Bit definition for FLASH_OPTKEYR register ****************/ S#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ S S/****************** Bit definition for FLASH_SR register *******************/ S#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ S#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ S#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ S#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ S S/******************* Bit definition for FLASH_CR register *******************/ S#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ S#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ S#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ S#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ S#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ S#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ S#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ S#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ S#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ S#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ S S/******************* Bit definition for FLASH_AR register *******************/ S#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ S S/****************** Bit definition for FLASH_OBR register *******************/ S#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ S#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ S S#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ S#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ S#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ S#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ S#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ S S/****************** Bit definition for FLASH_WRPR register ******************/ S#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ S S/*----------------------------------------------------------------------------*/ S S/****************** Bit definition for FLASH_RDP register *******************/ S#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ S#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ S S/****************** Bit definition for FLASH_USER register ******************/ S#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ S#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ S S/****************** Bit definition for FLASH_Data0 register *****************/ S#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ S#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ S S/****************** Bit definition for FLASH_Data1 register *****************/ S#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ S#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ S S/****************** Bit definition for FLASH_WRP0 register ******************/ S#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ S#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ S S/****************** Bit definition for FLASH_WRP1 register ******************/ S#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ S#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ S S/****************** Bit definition for FLASH_WRP2 register ******************/ S#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ S#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ S S/****************** Bit definition for FLASH_WRP3 register ******************/ S#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ S#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ S S#ifdef STM32F10X_CL S/******************************************************************************/ S/* Ethernet MAC Registers bits definitions */ S/******************************************************************************/ S/* Bit definition for Ethernet MAC Control Register register */ S#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ S#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ S#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ S #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ S #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ S #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ S #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ S #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ S #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ S #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ S #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ S#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ S#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ S#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ S#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ S#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ S#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ S#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ S#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ S#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling S a transmission attempt during retries after a collision: 0 =< r <2^k */ S #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ S #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ S #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ S #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ S#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ S#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ S#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ S S/* Bit definition for Ethernet MAC Frame Filter Register */ S#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ S#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ S#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ S#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ S#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ S #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ S #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ S #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ S#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ S#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ S#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ S#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ S#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ S#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ S S/* Bit definition for Ethernet MAC Hash Table High Register */ S#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ S S/* Bit definition for Ethernet MAC Hash Table Low Register */ S#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ S S/* Bit definition for Ethernet MAC MII Address Register */ S#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ S#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ S#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ S #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ S #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ S #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ S#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ S#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ S S/* Bit definition for Ethernet MAC MII Data Register */ S#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ S S/* Bit definition for Ethernet MAC Flow Control Register */ S#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ S#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ S#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ S #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ S #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ S #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ S #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ S#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ S#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ S#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ S#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ S S/* Bit definition for Ethernet MAC VLAN Tag Register */ S#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ S#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ S S/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ S#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ S/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. S Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ S/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask S Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask S Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask S Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask S Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - S RSVD - Filter1 Command - RSVD - Filter0 Command S Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset S Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 S Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ S S/* Bit definition for Ethernet MAC PMT Control and Status Register */ S#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ S#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ S#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ S#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ S#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ S#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ S#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ S S/* Bit definition for Ethernet MAC Status Register */ S#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ S#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ S#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ S#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ S#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ S S/* Bit definition for Ethernet MAC Interrupt Mask Register */ S#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ S#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ S S/* Bit definition for Ethernet MAC Address0 High Register */ S#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ S S/* Bit definition for Ethernet MAC Address0 Low Register */ S#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ S S/* Bit definition for Ethernet MAC Address1 High Register */ S#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ S#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ S#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ S #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ S #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ S #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ S #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ S #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ S #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ S#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ S S/* Bit definition for Ethernet MAC Address1 Low Register */ S#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ S S/* Bit definition for Ethernet MAC Address2 High Register */ S#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ S#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ S#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ S #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ S #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ S #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ S #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ S #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ S #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ S#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ S S/* Bit definition for Ethernet MAC Address2 Low Register */ S#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ S S/* Bit definition for Ethernet MAC Address3 High Register */ S#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ S#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ S#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ S #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ S #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ S #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ S #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ S #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ S #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ S#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ S S/* Bit definition for Ethernet MAC Address3 Low Register */ S#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ S S/******************************************************************************/ S/* Ethernet MMC Registers bits definition */ S/******************************************************************************/ S S/* Bit definition for Ethernet MMC Contol Register */ S#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ S#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ S#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ S#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ S S/* Bit definition for Ethernet MMC Receive Interrupt Register */ S#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ S#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ S#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Transmit Interrupt Register */ S#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ S#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ S#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ S#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ S#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ S#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ S#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ S#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ S#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ S S/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ S#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ S S/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ S#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ S S/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ S#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ S S/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ S#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ S S/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ S#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ S S/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ S#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ S S/******************************************************************************/ S/* Ethernet PTP Registers bits definition */ S/******************************************************************************/ S S/* Bit definition for Ethernet PTP Time Stamp Contol Register */ S#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ S#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ S#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ S#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ S#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ S#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ S S/* Bit definition for Ethernet PTP Sub-Second Increment Register */ S#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ S S/* Bit definition for Ethernet PTP Time Stamp High Register */ S#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ S S/* Bit definition for Ethernet PTP Time Stamp Low Register */ S#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ S#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ S S/* Bit definition for Ethernet PTP Time Stamp High Update Register */ S#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ S S/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ S#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ S#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ S S/* Bit definition for Ethernet PTP Time Stamp Addend Register */ S#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ S S/* Bit definition for Ethernet PTP Target Time High Register */ S#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ S S/* Bit definition for Ethernet PTP Target Time Low Register */ S#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ S S/******************************************************************************/ S/* Ethernet DMA Registers bits definition */ S/******************************************************************************/ S S/* Bit definition for Ethernet DMA Bus Mode Register */ S#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ S#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ S#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ S#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ S #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ S #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ S #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ S #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ S #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ S #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ S #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ S #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ S #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ S #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ S #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ S #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ S#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ S#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ S #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ S#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ S #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ S #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ S #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ S #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ S #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ S #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ S #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ S #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ S #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ S #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ S #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ S #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ S#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ S#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ S#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ S S/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ S#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ S S/* Bit definition for Ethernet DMA Receive Poll Demand Register */ S#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ S S/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ S#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ S S/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ S#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ S S/* Bit definition for Ethernet DMA Status Register */ S#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ S#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ S#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ S#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ S /* combination with EBS[2:0] for GetFlagStatus function */ S #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ S #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ S #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ S#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ S #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ S #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ S #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ S #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ S #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ S #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ S#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ S #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ S #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ S #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ S #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ S #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ S #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ S#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ S#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ S#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ S#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ S#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ S#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ S#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ S#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ S#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ S#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ S#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ S#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ S#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ S#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ S#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ S S/* Bit definition for Ethernet DMA Operation Mode Register */ S#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ S#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ S#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ S#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ S#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ S#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ S #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ S #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ S #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ S #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ S #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ S #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ S #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ S #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ S#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ S#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ S#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ S#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ S #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ S #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ S #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ S #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ S#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ S#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ S S/* Bit definition for Ethernet DMA Interrupt Enable Register */ S#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ S#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ S#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ S#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ S#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ S#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ S#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ S#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ S#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ S#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ S#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ S#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ S#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ S#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ S#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ S S/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ S#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ S#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ S#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ S#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ S S/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ S#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ S S/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ S#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ S S/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ S#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ S S/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ S#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ S#endif /* STM32F10X_CL */ S S/** S * @} S */ S S /** S * @} S */ S S#ifdef USE_STDPERIPH_DRIVER S #include "stm32f10x_conf.h" S#endif S S/** @addtogroup Exported_macro S * @{ S */ S S#define SET_BIT(REG, BIT) ((REG) |= (BIT)) S S#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) S S#define READ_BIT(REG, BIT) ((REG) & (BIT)) S S#define CLEAR_REG(REG) ((REG) = (0x0)) S S#define WRITE_REG(REG, VAL) ((REG) = (VAL)) S S#define READ_REG(REG) ((REG)) S S#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) S S/** S * @} S */ S S#ifdef __cplusplus S} S#endif S N#endif /* __STM32F10x_H */ N N/** N * @} N */ N N /** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 33 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h" 2 N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup ADC N * @{ N */ N N/** @defgroup ADC_Exported_Types N * @{ N */ N N/** N * @brief ADC Init structure definition N */ N Ntypedef struct N{ N uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or N dual mode. N This parameter can be a value of @ref ADC_mode */ N N FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in N Scan (multichannels) or Single (one channel) mode. N This parameter can be set to ENABLE or DISABLE */ N N FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in N Continuous or Single mode. N This parameter can be set to ENABLE or DISABLE. */ N N uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog N to digital conversion of regular channels. This parameter N can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ N N uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. N This parameter can be a value of @ref ADC_data_align */ N N uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted N using the sequencer for regular channel group. N This parameter must range from 1 to 16. */ N}ADC_InitTypeDef; N/** N * @} N */ N N/** @defgroup ADC_Exported_Constants N * @{ N */ N N#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ N ((PERIPH) == ADC2) || \ N ((PERIPH) == ADC3)) X#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2) || ((PERIPH) == ADC3)) N N#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ N ((PERIPH) == ADC3)) X#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC3)) N N/** @defgroup ADC_mode N * @{ N */ N N#define ADC_Mode_Independent ((uint32_t)0x00000000) N#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) N#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) N#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) N#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) N#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) N#define ADC_Mode_RegSimult ((uint32_t)0x00060000) N#define ADC_Mode_FastInterl ((uint32_t)0x00070000) N#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) N#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) N N#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ N ((MODE) == ADC_Mode_RegInjecSimult) || \ N ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ N ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ N ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ N ((MODE) == ADC_Mode_InjecSimult) || \ N ((MODE) == ADC_Mode_RegSimult) || \ N ((MODE) == ADC_Mode_FastInterl) || \ N ((MODE) == ADC_Mode_SlowInterl) || \ N ((MODE) == ADC_Mode_AlterTrig)) X#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || ((MODE) == ADC_Mode_RegInjecSimult) || ((MODE) == ADC_Mode_RegSimult_AlterTrig) || ((MODE) == ADC_Mode_InjecSimult_FastInterl) || ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || ((MODE) == ADC_Mode_InjecSimult) || ((MODE) == ADC_Mode_RegSimult) || ((MODE) == ADC_Mode_FastInterl) || ((MODE) == ADC_Mode_SlowInterl) || ((MODE) == ADC_Mode_AlterTrig)) N/** N * @} N */ N N/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion N * @{ N */ N N#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ N N#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ N#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ N N#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ N#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ N#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ N#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ N#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ N#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ N N#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ N ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ N ((REGTRIG) == ADC_ExternalTrigConv_None) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ N ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) X#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || ((REGTRIG) == ADC_ExternalTrigConv_None) || ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) N/** N * @} N */ N N/** @defgroup ADC_data_align N * @{ N */ N N#define ADC_DataAlign_Right ((uint32_t)0x00000000) N#define ADC_DataAlign_Left ((uint32_t)0x00000800) N#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ N ((ALIGN) == ADC_DataAlign_Left)) X#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || ((ALIGN) == ADC_DataAlign_Left)) N/** N * @} N */ N N/** @defgroup ADC_channels N * @{ N */ N N#define ADC_Channel_0 ((uint8_t)0x00) N#define ADC_Channel_1 ((uint8_t)0x01) N#define ADC_Channel_2 ((uint8_t)0x02) N#define ADC_Channel_3 ((uint8_t)0x03) N#define ADC_Channel_4 ((uint8_t)0x04) N#define ADC_Channel_5 ((uint8_t)0x05) N#define ADC_Channel_6 ((uint8_t)0x06) N#define ADC_Channel_7 ((uint8_t)0x07) N#define ADC_Channel_8 ((uint8_t)0x08) N#define ADC_Channel_9 ((uint8_t)0x09) N#define ADC_Channel_10 ((uint8_t)0x0A) N#define ADC_Channel_11 ((uint8_t)0x0B) N#define ADC_Channel_12 ((uint8_t)0x0C) N#define ADC_Channel_13 ((uint8_t)0x0D) N#define ADC_Channel_14 ((uint8_t)0x0E) N#define ADC_Channel_15 ((uint8_t)0x0F) N#define ADC_Channel_16 ((uint8_t)0x10) N#define ADC_Channel_17 ((uint8_t)0x11) N N#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) N#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) N N#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ N ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ N ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ N ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ N ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ N ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ N ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ N ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ N ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) X#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) N/** N * @} N */ N N/** @defgroup ADC_sampling_time N * @{ N */ N N#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) N#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) N#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) N#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) N#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) N#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) N#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) N#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) N#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ N ((TIME) == ADC_SampleTime_7Cycles5) || \ N ((TIME) == ADC_SampleTime_13Cycles5) || \ N ((TIME) == ADC_SampleTime_28Cycles5) || \ N ((TIME) == ADC_SampleTime_41Cycles5) || \ N ((TIME) == ADC_SampleTime_55Cycles5) || \ N ((TIME) == ADC_SampleTime_71Cycles5) || \ N ((TIME) == ADC_SampleTime_239Cycles5)) X#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || ((TIME) == ADC_SampleTime_7Cycles5) || ((TIME) == ADC_SampleTime_13Cycles5) || ((TIME) == ADC_SampleTime_28Cycles5) || ((TIME) == ADC_SampleTime_41Cycles5) || ((TIME) == ADC_SampleTime_55Cycles5) || ((TIME) == ADC_SampleTime_71Cycles5) || ((TIME) == ADC_SampleTime_239Cycles5)) N/** N * @} N */ N N/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion N * @{ N */ N N#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ N#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ N N#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ N#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ N#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ N N#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ N#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ N#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ N#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ N#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ N N#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ N ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) X#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) N/** N * @} N */ N N/** @defgroup ADC_injected_channel_selection N * @{ N */ N N#define ADC_InjectedChannel_1 ((uint8_t)0x14) N#define ADC_InjectedChannel_2 ((uint8_t)0x18) N#define ADC_InjectedChannel_3 ((uint8_t)0x1C) N#define ADC_InjectedChannel_4 ((uint8_t)0x20) N#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ N ((CHANNEL) == ADC_InjectedChannel_2) || \ N ((CHANNEL) == ADC_InjectedChannel_3) || \ N ((CHANNEL) == ADC_InjectedChannel_4)) X#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || ((CHANNEL) == ADC_InjectedChannel_2) || ((CHANNEL) == ADC_InjectedChannel_3) || ((CHANNEL) == ADC_InjectedChannel_4)) N/** N * @} N */ N N/** @defgroup ADC_analog_watchdog_selection N * @{ N */ N N#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) N#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) N#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) N#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) N#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) N#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) N#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) N N#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ N ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ N ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ N ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ N ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ N ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ N ((WATCHDOG) == ADC_AnalogWatchdog_None)) X#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_None)) N/** N * @} N */ N N/** @defgroup ADC_interrupts_definition N * @{ N */ N N#define ADC_IT_EOC ((uint16_t)0x0220) N#define ADC_IT_AWD ((uint16_t)0x0140) N#define ADC_IT_JEOC ((uint16_t)0x0480) N N#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) N N#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ N ((IT) == ADC_IT_JEOC)) X#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_JEOC)) N/** N * @} N */ N N/** @defgroup ADC_flags_definition N * @{ N */ N N#define ADC_FLAG_AWD ((uint8_t)0x01) N#define ADC_FLAG_EOC ((uint8_t)0x02) N#define ADC_FLAG_JEOC ((uint8_t)0x04) N#define ADC_FLAG_JSTRT ((uint8_t)0x08) N#define ADC_FLAG_STRT ((uint8_t)0x10) N#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) N#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ N ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ N ((FLAG) == ADC_FLAG_STRT)) X#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || ((FLAG) == ADC_FLAG_STRT)) N/** N * @} N */ N N/** @defgroup ADC_thresholds N * @{ N */ N N#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) N N/** N * @} N */ N N/** @defgroup ADC_injected_offset N * @{ N */ N N#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) N N/** N * @} N */ N N/** @defgroup ADC_injected_length N * @{ N */ N N#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) N N/** N * @} N */ N N/** @defgroup ADC_injected_rank N * @{ N */ N N#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) N N/** N * @} N */ N N N/** @defgroup ADC_regular_length N * @{ N */ N N#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) N/** N * @} N */ N N/** @defgroup ADC_regular_rank N * @{ N */ N N#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) N N/** N * @} N */ N N/** @defgroup ADC_regular_discontinuous_mode_number N * @{ N */ N N#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup ADC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup ADC_Exported_Functions N * @{ N */ N Nvoid ADC_DeInit(ADC_TypeDef* ADCx); Nvoid ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); Nvoid ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); Nvoid ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nvoid ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nvoid ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); Nvoid ADC_ResetCalibration(ADC_TypeDef* ADCx); NFlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); Nvoid ADC_StartCalibration(ADC_TypeDef* ADCx); NFlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); Nvoid ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); NFlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); Nvoid ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); Nvoid ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nvoid ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); Nvoid ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nuint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); Nuint32_t ADC_GetDualModeConversionValue(void); Nvoid ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nvoid ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nvoid ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); Nvoid ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); Nvoid ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); NFlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); Nvoid ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); Nvoid ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); Nvoid ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); Nuint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); Nvoid ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); Nvoid ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); Nvoid ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); Nvoid ADC_TempSensorVrefintCmd(FunctionalState NewState); NFlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); Nvoid ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); NITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); Nvoid ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_ADC_H */ N N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 29 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_bkp.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_bkp.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_bkp.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the BKP firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_BKP_H N#define __STM32F10x_BKP_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup BKP N * @{ N */ N N/** @defgroup BKP_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup BKP_Exported_Constants N * @{ N */ N N/** @defgroup Tamper_Pin_active_level N * @{ N */ N N#define BKP_TamperPinLevel_High ((uint16_t)0x0000) N#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) N#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ N ((LEVEL) == BKP_TamperPinLevel_Low)) X#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || ((LEVEL) == BKP_TamperPinLevel_Low)) N/** N * @} N */ N N/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin N * @{ N */ N N#define BKP_RTCOutputSource_None ((uint16_t)0x0000) N#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) N#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) N#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) N#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ N ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ N ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ N ((SOURCE) == BKP_RTCOutputSource_Second)) X#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || ((SOURCE) == BKP_RTCOutputSource_CalibClock) || ((SOURCE) == BKP_RTCOutputSource_Alarm) || ((SOURCE) == BKP_RTCOutputSource_Second)) N/** N * @} N */ N N/** @defgroup Data_Backup_Register N * @{ N */ N N#define BKP_DR1 ((uint16_t)0x0004) N#define BKP_DR2 ((uint16_t)0x0008) N#define BKP_DR3 ((uint16_t)0x000C) N#define BKP_DR4 ((uint16_t)0x0010) N#define BKP_DR5 ((uint16_t)0x0014) N#define BKP_DR6 ((uint16_t)0x0018) N#define BKP_DR7 ((uint16_t)0x001C) N#define BKP_DR8 ((uint16_t)0x0020) N#define BKP_DR9 ((uint16_t)0x0024) N#define BKP_DR10 ((uint16_t)0x0028) N#define BKP_DR11 ((uint16_t)0x0040) N#define BKP_DR12 ((uint16_t)0x0044) N#define BKP_DR13 ((uint16_t)0x0048) N#define BKP_DR14 ((uint16_t)0x004C) N#define BKP_DR15 ((uint16_t)0x0050) N#define BKP_DR16 ((uint16_t)0x0054) N#define BKP_DR17 ((uint16_t)0x0058) N#define BKP_DR18 ((uint16_t)0x005C) N#define BKP_DR19 ((uint16_t)0x0060) N#define BKP_DR20 ((uint16_t)0x0064) N#define BKP_DR21 ((uint16_t)0x0068) N#define BKP_DR22 ((uint16_t)0x006C) N#define BKP_DR23 ((uint16_t)0x0070) N#define BKP_DR24 ((uint16_t)0x0074) N#define BKP_DR25 ((uint16_t)0x0078) N#define BKP_DR26 ((uint16_t)0x007C) N#define BKP_DR27 ((uint16_t)0x0080) N#define BKP_DR28 ((uint16_t)0x0084) N#define BKP_DR29 ((uint16_t)0x0088) N#define BKP_DR30 ((uint16_t)0x008C) N#define BKP_DR31 ((uint16_t)0x0090) N#define BKP_DR32 ((uint16_t)0x0094) N#define BKP_DR33 ((uint16_t)0x0098) N#define BKP_DR34 ((uint16_t)0x009C) N#define BKP_DR35 ((uint16_t)0x00A0) N#define BKP_DR36 ((uint16_t)0x00A4) N#define BKP_DR37 ((uint16_t)0x00A8) N#define BKP_DR38 ((uint16_t)0x00AC) N#define BKP_DR39 ((uint16_t)0x00B0) N#define BKP_DR40 ((uint16_t)0x00B4) N#define BKP_DR41 ((uint16_t)0x00B8) N#define BKP_DR42 ((uint16_t)0x00BC) N N#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ N ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ N ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ N ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ N ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ N ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ N ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ N ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ N ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ N ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ N ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ N ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ N ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ N ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) X#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) N N#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup BKP_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup BKP_Exported_Functions N * @{ N */ N Nvoid BKP_DeInit(void); Nvoid BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); Nvoid BKP_TamperPinCmd(FunctionalState NewState); Nvoid BKP_ITConfig(FunctionalState NewState); Nvoid BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); Nvoid BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); Nvoid BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); Nuint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); NFlagStatus BKP_GetFlagStatus(void); Nvoid BKP_ClearFlag(void); NITStatus BKP_GetITStatus(void); Nvoid BKP_ClearITPendingBit(void); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_BKP_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 30 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_can.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_can.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_can.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the CAN firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_CAN_H N#define __STM32F10x_CAN_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup CAN N * @{ N */ N N/** @defgroup CAN_Exported_Types N * @{ N */ N N#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ N ((PERIPH) == CAN2)) X#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || ((PERIPH) == CAN2)) N N/** N * @brief CAN init structure definition N */ N Ntypedef struct N{ N uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. N It ranges from 1 to 1024. */ N N uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. N This parameter can be a value of N @ref CAN_operating_mode */ N N uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta N the CAN hardware is allowed to lengthen or N shorten a bit to perform resynchronization. N This parameter can be a value of N @ref CAN_synchronisation_jump_width */ N N uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit N Segment 1. This parameter can be a value of N @ref CAN_time_quantum_in_bit_segment_1 */ N N uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit N Segment 2. N This parameter can be a value of N @ref CAN_time_quantum_in_bit_segment_2 */ N N FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered N communication mode. This parameter can be set N either to ENABLE or DISABLE. */ N N FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off N management. This parameter can be set either N to ENABLE or DISABLE. */ N N FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. N This parameter can be set either to ENABLE or N DISABLE. */ N N FunctionalState CAN_NART; /*!< Enable or disable the no-automatic N retransmission mode. This parameter can be N set either to ENABLE or DISABLE. */ N N FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. N This parameter can be set either to ENABLE N or DISABLE. */ N N FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. N This parameter can be set either to ENABLE N or DISABLE. */ N} CAN_InitTypeDef; N N/** N * @brief CAN filter init structure definition N */ N Ntypedef struct N{ N uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit N configuration, first one for a 16-bit configuration). N This parameter can be a value between 0x0000 and 0xFFFF */ N N uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit N configuration, second one for a 16-bit configuration). N This parameter can be a value between 0x0000 and 0xFFFF */ N N uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, N according to the mode (MSBs for a 32-bit configuration, N first one for a 16-bit configuration). N This parameter can be a value between 0x0000 and 0xFFFF */ N N uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, N according to the mode (LSBs for a 32-bit configuration, N second one for a 16-bit configuration). N This parameter can be a value between 0x0000 and 0xFFFF */ N N uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. N This parameter can be a value of @ref CAN_filter_FIFO */ N N uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ N N uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. N This parameter can be a value of @ref CAN_filter_mode */ N N uint8_t CAN_FilterScale; /*!< Specifies the filter scale. N This parameter can be a value of @ref CAN_filter_scale */ N N FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. N This parameter can be set either to ENABLE or DISABLE. */ N} CAN_FilterInitTypeDef; N N/** N * @brief CAN Tx message structure definition N */ N Ntypedef struct N{ N uint32_t StdId; /*!< Specifies the standard identifier. N This parameter can be a value between 0 to 0x7FF. */ N N uint32_t ExtId; /*!< Specifies the extended identifier. N This parameter can be a value between 0 to 0x1FFFFFFF. */ N N uint8_t IDE; /*!< Specifies the type of identifier for the message that N will be transmitted. This parameter can be a value N of @ref CAN_identifier_type */ N N uint8_t RTR; /*!< Specifies the type of frame for the message that will N be transmitted. This parameter can be a value of N @ref CAN_remote_transmission_request */ N N uint8_t DLC; /*!< Specifies the length of the frame that will be N transmitted. This parameter can be a value between N 0 to 8 */ N N uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 N to 0xFF. */ N} CanTxMsg; N N/** N * @brief CAN Rx message structure definition N */ N Ntypedef struct N{ N uint32_t StdId; /*!< Specifies the standard identifier. N This parameter can be a value between 0 to 0x7FF. */ N N uint32_t ExtId; /*!< Specifies the extended identifier. N This parameter can be a value between 0 to 0x1FFFFFFF. */ N N uint8_t IDE; /*!< Specifies the type of identifier for the message that N will be received. This parameter can be a value of N @ref CAN_identifier_type */ N N uint8_t RTR; /*!< Specifies the type of frame for the received message. N This parameter can be a value of N @ref CAN_remote_transmission_request */ N N uint8_t DLC; /*!< Specifies the length of the frame that will be received. N This parameter can be a value between 0 to 8 */ N N uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to N 0xFF. */ N N uint8_t FMI; /*!< Specifies the index of the filter the message stored in N the mailbox passes through. This parameter can be a N value between 0 to 0xFF */ N} CanRxMsg; N N/** N * @} N */ N N/** @defgroup CAN_Exported_Constants N * @{ N */ N N/** @defgroup CAN_sleep_constants N * @{ N */ N N#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ N#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ N N/** N * @} N */ N N/** @defgroup CAN_Mode N * @{ N */ N N#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ N#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ N#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ N#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ N N#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ N ((MODE) == CAN_Mode_LoopBack)|| \ N ((MODE) == CAN_Mode_Silent) || \ N ((MODE) == CAN_Mode_Silent_LoopBack)) X#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) N/** N * @} N */ N N N/** N * @defgroup CAN_Operating_Mode N * @{ N */ N#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ N#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ N#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ N N N#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ N ((MODE) == CAN_OperatingMode_Normal)|| \ N ((MODE) == CAN_OperatingMode_Sleep)) X#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) || ((MODE) == CAN_OperatingMode_Normal)|| ((MODE) == CAN_OperatingMode_Sleep)) N/** N * @} N */ N N/** N * @defgroup CAN_Mode_Status N * @{ N */ N N#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ N#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ N N N/** N * @} N */ N N/** @defgroup CAN_synchronisation_jump_width N * @{ N */ N N#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ N#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ N#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ N#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ N N#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ N ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) X#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) N/** N * @} N */ N N/** @defgroup CAN_time_quantum_in_bit_segment_1 N * @{ N */ N N#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ N#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ N#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ N#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ N#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ N#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ N#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ N#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ N#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ N#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ N#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ N#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ N#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ N#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ N#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ N#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ N N#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) N/** N * @} N */ N N/** @defgroup CAN_time_quantum_in_bit_segment_2 N * @{ N */ N N#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ N#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ N#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ N#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ N#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ N#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ N#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ N#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ N N#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) N N/** N * @} N */ N N/** @defgroup CAN_clock_prescaler N * @{ N */ N N#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) N N/** N * @} N */ N N/** @defgroup CAN_filter_number N * @{ N */ N#ifndef STM32F10X_CL N #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) N#else S #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) N#endif /* STM32F10X_CL */ N/** N * @} N */ N N/** @defgroup CAN_filter_mode N * @{ N */ N N#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ N#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ N N#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ N ((MODE) == CAN_FilterMode_IdList)) X#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || ((MODE) == CAN_FilterMode_IdList)) N/** N * @} N */ N N/** @defgroup CAN_filter_scale N * @{ N */ N N#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ N#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ N N#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ N ((SCALE) == CAN_FilterScale_32bit)) X#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || ((SCALE) == CAN_FilterScale_32bit)) N N/** N * @} N */ N N/** @defgroup CAN_filter_FIFO N * @{ N */ N N#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ N#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ N#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ N ((FIFO) == CAN_FilterFIFO1)) X#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || ((FIFO) == CAN_FilterFIFO1)) N/** N * @} N */ N N/** @defgroup Start_bank_filter_for_slave_CAN N * @{ N */ N#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) N/** N * @} N */ N N/** @defgroup CAN_Tx N * @{ N */ N N#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) N#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) N#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) N#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) N N/** N * @} N */ N N/** @defgroup CAN_identifier_type N * @{ N */ N N#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ N#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ N#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ N ((IDTYPE) == CAN_Id_Extended)) X#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended)) N/** N * @} N */ N N/** @defgroup CAN_remote_transmission_request N * @{ N */ N N#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ N#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ N#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) N N/** N * @} N */ N N/** @defgroup CAN_transmit_constants N * @{ N */ N N#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ N#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ N#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ N#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ N N/** N * @} N */ N N/** @defgroup CAN_receive_FIFO_number_constants N * @{ N */ N N#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ N#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ N N#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) N N/** N * @} N */ N N/** @defgroup CAN_sleep_constants N * @{ N */ N N#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ N#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ N N/** N * @} N */ N N/** @defgroup CAN_wake_up_constants N * @{ N */ N N#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ N#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ N N/** N * @} N */ N N/** N * @defgroup CAN_Error_Code_constants N * @{ N */ N N#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ N#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ N#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ N#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ N#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ N#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ N#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ N#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ N N N/** N * @} N */ N N/** @defgroup CAN_flags N * @{ N */ N/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() N and CAN_ClearFlag() functions. */ N/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ N N/* Transmit Flags */ N#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ N#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ N#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ N N/* Receive Flags */ N#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ N#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ N#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ N#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ N#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ N#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ N N/* Operating Mode Flags */ N#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ N#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ N/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. N In this case the SLAK bit can be polled.*/ N N/* Error Flags */ N#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ N#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ N#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ N#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ N N#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ N ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ N ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ N ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ N ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ N ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ N ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ N ((FLAG) == CAN_FLAG_SLAK )) X#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_SLAK )) N N#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ N ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ N ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ N ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ N ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) X#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) N/** N * @} N */ N N N/** @defgroup CAN_interrupts N * @{ N */ N N N N#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ N N/* Receive Interrupts */ N#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ N#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ N#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ N#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ N#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ N#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ N N/* Operating Mode Interrupts */ N#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ N#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ N N/* Error Interrupts */ N#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ N#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ N#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ N#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ N#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ N N/* Flags named as Interrupts : kept only for FW compatibility */ N#define CAN_IT_RQCP0 CAN_IT_TME N#define CAN_IT_RQCP1 CAN_IT_TME N#define CAN_IT_RQCP2 CAN_IT_TME N N N#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ N ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ N ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ N ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ N ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ N ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ N ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) X#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) || ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) || ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) || ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) || ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) || ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) N N#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ N ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ N ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ N ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ N ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ N ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) X#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) || ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) || ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) || ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) || ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) N N/** N * @} N */ N N/** @defgroup CAN_Legacy N * @{ N */ N#define CANINITFAILED CAN_InitStatus_Failed N#define CANINITOK CAN_InitStatus_Success N#define CAN_FilterFIFO0 CAN_Filter_FIFO0 N#define CAN_FilterFIFO1 CAN_Filter_FIFO1 N#define CAN_ID_STD CAN_Id_Standard N#define CAN_ID_EXT CAN_Id_Extended N#define CAN_RTR_DATA CAN_RTR_Data N#define CAN_RTR_REMOTE CAN_RTR_Remote N#define CANTXFAILE CAN_TxStatus_Failed N#define CANTXOK CAN_TxStatus_Ok N#define CANTXPENDING CAN_TxStatus_Pending N#define CAN_NO_MB CAN_TxStatus_NoMailBox N#define CANSLEEPFAILED CAN_Sleep_Failed N#define CANSLEEPOK CAN_Sleep_Ok N#define CANWAKEUPFAILED CAN_WakeUp_Failed N#define CANWAKEUPOK CAN_WakeUp_Ok N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup CAN_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup CAN_Exported_Functions N * @{ N */ N/* Function used to set the CAN configuration to the default reset state *****/ Nvoid CAN_DeInit(CAN_TypeDef* CANx); N N/* Initialization and Configuration functions *********************************/ Nuint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); Nvoid CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); Nvoid CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); Nvoid CAN_SlaveStartBank(uint8_t CAN_BankNumber); Nvoid CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); Nvoid CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); N N/* Transmit functions *********************************************************/ Nuint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); Nuint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); Nvoid CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); N N/* Receive functions **********************************************************/ Nvoid CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); Nvoid CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); Nuint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); N N N/* Operation modes functions **************************************************/ Nuint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); Nuint8_t CAN_Sleep(CAN_TypeDef* CANx); Nuint8_t CAN_WakeUp(CAN_TypeDef* CANx); N N/* Error management functions *************************************************/ Nuint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); Nuint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); Nuint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); N N/* Interrupts and flags management functions **********************************/ Nvoid CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); NFlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); Nvoid CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); NITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); Nvoid CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_CAN_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 31 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_cec.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_cec.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_cec.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the CEC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_CEC_H N#define __STM32F10x_CEC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup CEC N * @{ N */ N N N/** @defgroup CEC_Exported_Types N * @{ N */ N N/** N * @brief CEC Init structure definition N */ Ntypedef struct N{ N uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. N This parameter can be a value of @ref CEC_BitTiming_Mode */ N uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. N This parameter can be a value of @ref CEC_BitPeriod_Mode */ N}CEC_InitTypeDef; N N/** N * @} N */ N N/** @defgroup CEC_Exported_Constants N * @{ N */ N N/** @defgroup CEC_BitTiming_Mode N * @{ N */ N#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ N#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ N N#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ N ((MODE) == CEC_BitTimingErrFreeMode)) X#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || ((MODE) == CEC_BitTimingErrFreeMode)) N/** N * @} N */ N N/** @defgroup CEC_BitPeriod_Mode N * @{ N */ N#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ N#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ N N#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ N ((MODE) == CEC_BitPeriodFlexibleMode)) X#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || ((MODE) == CEC_BitPeriodFlexibleMode)) N/** N * @} N */ N N N/** @defgroup CEC_interrupts_definition N * @{ N */ N#define CEC_IT_TERR CEC_CSR_TERR N#define CEC_IT_TBTRF CEC_CSR_TBTRF N#define CEC_IT_RERR CEC_CSR_RERR N#define CEC_IT_RBTF CEC_CSR_RBTF N#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ N ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) X#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) N/** N * @} N */ N N N/** @defgroup CEC_Own_Address N * @{ N */ N#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) N/** N * @} N */ N N/** @defgroup CEC_Prescaler N * @{ N */ N#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) N N/** N * @} N */ N N/** @defgroup CEC_flags_definition N * @{ N */ N N/** N * @brief ESR register flags N */ N#define CEC_FLAG_BTE ((uint32_t)0x10010000) N#define CEC_FLAG_BPE ((uint32_t)0x10020000) N#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) N#define CEC_FLAG_SBE ((uint32_t)0x10080000) N#define CEC_FLAG_ACKE ((uint32_t)0x10100000) N#define CEC_FLAG_LINE ((uint32_t)0x10200000) N#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) N N/** N * @brief CSR register flags N */ N#define CEC_FLAG_TEOM ((uint32_t)0x00000002) N#define CEC_FLAG_TERR ((uint32_t)0x00000004) N#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) N#define CEC_FLAG_RSOM ((uint32_t)0x00000010) N#define CEC_FLAG_REOM ((uint32_t)0x00000020) N#define CEC_FLAG_RERR ((uint32_t)0x00000040) N#define CEC_FLAG_RBTF ((uint32_t)0x00000080) N N#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) N N#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ N ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ N ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ N ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ N ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ N ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ N ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) X#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup CEC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup CEC_Exported_Functions N * @{ N */ Nvoid CEC_DeInit(void); Nvoid CEC_Init(CEC_InitTypeDef* CEC_InitStruct); Nvoid CEC_Cmd(FunctionalState NewState); Nvoid CEC_ITConfig(FunctionalState NewState); Nvoid CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); Nvoid CEC_SetPrescaler(uint16_t CEC_Prescaler); Nvoid CEC_SendDataByte(uint8_t Data); Nuint8_t CEC_ReceiveDataByte(void); Nvoid CEC_StartOfMessage(void); Nvoid CEC_EndOfMessageCmd(FunctionalState NewState); NFlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); Nvoid CEC_ClearFlag(uint32_t CEC_FLAG); NITStatus CEC_GetITStatus(uint8_t CEC_IT); Nvoid CEC_ClearITPendingBit(uint16_t CEC_IT); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_CEC_H */ N N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 32 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_crc.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_crc.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_crc.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the CRC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_CRC_H N#define __STM32F10x_CRC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup CRC N * @{ N */ N N/** @defgroup CRC_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup CRC_Exported_Constants N * @{ N */ N N/** N * @} N */ N N/** @defgroup CRC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup CRC_Exported_Functions N * @{ N */ N Nvoid CRC_ResetDR(void); Nuint32_t CRC_CalcCRC(uint32_t Data); Nuint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); Nuint32_t CRC_GetCRC(void); Nvoid CRC_SetIDRegister(uint8_t IDValue); Nuint8_t CRC_GetIDRegister(void); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_CRC_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 33 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_dac.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dac.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_dac.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the DAC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_DAC_H N#define __STM32F10x_DAC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup DAC N * @{ N */ N N/** @defgroup DAC_Exported_Types N * @{ N */ N N/** N * @brief DAC Init structure definition N */ N Ntypedef struct N{ N uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. N This parameter can be a value of @ref DAC_trigger_selection */ N N uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves N are generated, or whether no wave is generated. N This parameter can be a value of @ref DAC_wave_generation */ N N uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or N the maximum amplitude triangle generation for the DAC channel. N This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ N N uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. N This parameter can be a value of @ref DAC_output_buffer */ N}DAC_InitTypeDef; N N/** N * @} N */ N N/** @defgroup DAC_Exported_Constants N * @{ N */ N N/** @defgroup DAC_trigger_selection N * @{ N */ N N#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register N has been loaded, and not by external trigger */ N#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ N#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel N only in High-density devices*/ N#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel N only in Connectivity line, Medium-density and Low-density Value Line devices */ N#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ N#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ N#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel N only in Medium-density and Low-density Value Line devices*/ N#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ N#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ N#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ N#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ N N#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ N ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ N ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ N ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ N ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ N ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ N ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ N ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ N ((TRIGGER) == DAC_Trigger_Software)) X#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || ((TRIGGER) == DAC_Trigger_T6_TRGO) || ((TRIGGER) == DAC_Trigger_T8_TRGO) || ((TRIGGER) == DAC_Trigger_T7_TRGO) || ((TRIGGER) == DAC_Trigger_T5_TRGO) || ((TRIGGER) == DAC_Trigger_T2_TRGO) || ((TRIGGER) == DAC_Trigger_T4_TRGO) || ((TRIGGER) == DAC_Trigger_Ext_IT9) || ((TRIGGER) == DAC_Trigger_Software)) N N/** N * @} N */ N N/** @defgroup DAC_wave_generation N * @{ N */ N N#define DAC_WaveGeneration_None ((uint32_t)0x00000000) N#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) N#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) N#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ N ((WAVE) == DAC_WaveGeneration_Noise) || \ N ((WAVE) == DAC_WaveGeneration_Triangle)) X#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || ((WAVE) == DAC_WaveGeneration_Noise) || ((WAVE) == DAC_WaveGeneration_Triangle)) N/** N * @} N */ N N/** @defgroup DAC_lfsrunmask_triangleamplitude N * @{ N */ N N#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ N#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ N#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ N#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ N#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ N#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ N#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ N#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ N#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ N#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ N#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ N#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ N#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ N#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ N#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ N N#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ N ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ N ((VALUE) == DAC_TriangleAmplitude_1) || \ N ((VALUE) == DAC_TriangleAmplitude_3) || \ N ((VALUE) == DAC_TriangleAmplitude_7) || \ N ((VALUE) == DAC_TriangleAmplitude_15) || \ N ((VALUE) == DAC_TriangleAmplitude_31) || \ N ((VALUE) == DAC_TriangleAmplitude_63) || \ N ((VALUE) == DAC_TriangleAmplitude_127) || \ N ((VALUE) == DAC_TriangleAmplitude_255) || \ N ((VALUE) == DAC_TriangleAmplitude_511) || \ N ((VALUE) == DAC_TriangleAmplitude_1023) || \ N ((VALUE) == DAC_TriangleAmplitude_2047) || \ N ((VALUE) == DAC_TriangleAmplitude_4095)) X#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || ((VALUE) == DAC_LFSRUnmask_Bits1_0) || ((VALUE) == DAC_LFSRUnmask_Bits2_0) || ((VALUE) == DAC_LFSRUnmask_Bits3_0) || ((VALUE) == DAC_LFSRUnmask_Bits4_0) || ((VALUE) == DAC_LFSRUnmask_Bits5_0) || ((VALUE) == DAC_LFSRUnmask_Bits6_0) || ((VALUE) == DAC_LFSRUnmask_Bits7_0) || ((VALUE) == DAC_LFSRUnmask_Bits8_0) || ((VALUE) == DAC_LFSRUnmask_Bits9_0) || ((VALUE) == DAC_LFSRUnmask_Bits10_0) || ((VALUE) == DAC_LFSRUnmask_Bits11_0) || ((VALUE) == DAC_TriangleAmplitude_1) || ((VALUE) == DAC_TriangleAmplitude_3) || ((VALUE) == DAC_TriangleAmplitude_7) || ((VALUE) == DAC_TriangleAmplitude_15) || ((VALUE) == DAC_TriangleAmplitude_31) || ((VALUE) == DAC_TriangleAmplitude_63) || ((VALUE) == DAC_TriangleAmplitude_127) || ((VALUE) == DAC_TriangleAmplitude_255) || ((VALUE) == DAC_TriangleAmplitude_511) || ((VALUE) == DAC_TriangleAmplitude_1023) || ((VALUE) == DAC_TriangleAmplitude_2047) || ((VALUE) == DAC_TriangleAmplitude_4095)) N/** N * @} N */ N N/** @defgroup DAC_output_buffer N * @{ N */ N N#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) N#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) N#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ N ((STATE) == DAC_OutputBuffer_Disable)) X#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || ((STATE) == DAC_OutputBuffer_Disable)) N/** N * @} N */ N N/** @defgroup DAC_Channel_selection N * @{ N */ N N#define DAC_Channel_1 ((uint32_t)0x00000000) N#define DAC_Channel_2 ((uint32_t)0x00000010) N#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ N ((CHANNEL) == DAC_Channel_2)) X#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || ((CHANNEL) == DAC_Channel_2)) N/** N * @} N */ N N/** @defgroup DAC_data_alignment N * @{ N */ N N#define DAC_Align_12b_R ((uint32_t)0x00000000) N#define DAC_Align_12b_L ((uint32_t)0x00000004) N#define DAC_Align_8b_R ((uint32_t)0x00000008) N#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ N ((ALIGN) == DAC_Align_12b_L) || \ N ((ALIGN) == DAC_Align_8b_R)) X#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || ((ALIGN) == DAC_Align_12b_L) || ((ALIGN) == DAC_Align_8b_R)) N/** N * @} N */ N N/** @defgroup DAC_wave_generation N * @{ N */ N N#define DAC_Wave_Noise ((uint32_t)0x00000040) N#define DAC_Wave_Triangle ((uint32_t)0x00000080) N#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ N ((WAVE) == DAC_Wave_Triangle)) X#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || ((WAVE) == DAC_Wave_Triangle)) N/** N * @} N */ N N/** @defgroup DAC_data N * @{ N */ N N#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) N/** N * @} N */ N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L S/** @defgroup DAC_interrupts_definition S * @{ S */ S S#define DAC_IT_DMAUDR ((uint32_t)0x00002000) S#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) S S/** S * @} S */ S S/** @defgroup DAC_flags_definition S * @{ S */ S S#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) S#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) S S/** S * @} S */ N#endif N N/** N * @} N */ N N/** @defgroup DAC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup DAC_Exported_Functions N * @{ N */ N Nvoid DAC_DeInit(void); Nvoid DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); Nvoid DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); Nvoid DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L Svoid DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); N#endif Nvoid DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); Nvoid DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); Nvoid DAC_DualSoftwareTriggerCmd(FunctionalState NewState); Nvoid DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); Nvoid DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); Nvoid DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); Nvoid DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); Nuint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#if 0L || 0L || 0L SFlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); Svoid DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); SITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); Svoid DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); N#endif N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_DAC_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 34 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_dbgmcu.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dbgmcu.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_dbgmcu.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the DBGMCU N * firmware library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_DBGMCU_H N#define __STM32F10x_DBGMCU_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup DBGMCU N * @{ N */ N N/** @defgroup DBGMCU_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup DBGMCU_Exported_Constants N * @{ N */ N N#define DBGMCU_SLEEP ((uint32_t)0x00000001) N#define DBGMCU_STOP ((uint32_t)0x00000002) N#define DBGMCU_STANDBY ((uint32_t)0x00000004) N#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) N#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) N#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) N#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) N#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) N#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) N#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) N#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) N#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) N#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) N#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) N#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) N#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) N#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) N#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) N#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) N#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) N#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) N#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) N#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) N#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) N#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) N#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) N N#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) N/** N * @} N */ N N/** @defgroup DBGMCU_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup DBGMCU_Exported_Functions N * @{ N */ N Nuint32_t DBGMCU_GetREVID(void); Nuint32_t DBGMCU_GetDEVID(void); Nvoid DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_DBGMCU_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 35 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_dma.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_dma.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_dma.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the DMA firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_DMA_H N#define __STM32F10x_DMA_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup DMA N * @{ N */ N N/** @defgroup DMA_Exported_Types N * @{ N */ N N/** N * @brief DMA Init structure definition N */ N Ntypedef struct N{ N uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ N N uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ N N uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. N This parameter can be a value of @ref DMA_data_transfer_direction */ N N uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. N The data unit is equal to the configuration set in DMA_PeripheralDataSize N or DMA_MemoryDataSize members depending in the transfer direction. */ N N uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. N This parameter can be a value of @ref DMA_peripheral_incremented_mode */ N N uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. N This parameter can be a value of @ref DMA_memory_incremented_mode */ N N uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. N This parameter can be a value of @ref DMA_peripheral_data_size */ N N uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. N This parameter can be a value of @ref DMA_memory_data_size */ N N uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. N This parameter can be a value of @ref DMA_circular_normal_mode. N @note: The circular buffer mode cannot be used if the memory-to-memory N data transfer is configured on the selected Channel */ N N uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. N This parameter can be a value of @ref DMA_priority_level */ N N uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. N This parameter can be a value of @ref DMA_memory_to_memory */ N}DMA_InitTypeDef; N N/** N * @} N */ N N/** @defgroup DMA_Exported_Constants N * @{ N */ N N#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ N ((PERIPH) == DMA1_Channel2) || \ N ((PERIPH) == DMA1_Channel3) || \ N ((PERIPH) == DMA1_Channel4) || \ N ((PERIPH) == DMA1_Channel5) || \ N ((PERIPH) == DMA1_Channel6) || \ N ((PERIPH) == DMA1_Channel7) || \ N ((PERIPH) == DMA2_Channel1) || \ N ((PERIPH) == DMA2_Channel2) || \ N ((PERIPH) == DMA2_Channel3) || \ N ((PERIPH) == DMA2_Channel4) || \ N ((PERIPH) == DMA2_Channel5)) X#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || ((PERIPH) == DMA1_Channel2) || ((PERIPH) == DMA1_Channel3) || ((PERIPH) == DMA1_Channel4) || ((PERIPH) == DMA1_Channel5) || ((PERIPH) == DMA1_Channel6) || ((PERIPH) == DMA1_Channel7) || ((PERIPH) == DMA2_Channel1) || ((PERIPH) == DMA2_Channel2) || ((PERIPH) == DMA2_Channel3) || ((PERIPH) == DMA2_Channel4) || ((PERIPH) == DMA2_Channel5)) N N/** @defgroup DMA_data_transfer_direction N * @{ N */ N N#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) N#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) N#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ N ((DIR) == DMA_DIR_PeripheralSRC)) X#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || ((DIR) == DMA_DIR_PeripheralSRC)) N/** N * @} N */ N N/** @defgroup DMA_peripheral_incremented_mode N * @{ N */ N N#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) N#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) N#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ N ((STATE) == DMA_PeripheralInc_Disable)) X#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || ((STATE) == DMA_PeripheralInc_Disable)) N/** N * @} N */ N N/** @defgroup DMA_memory_incremented_mode N * @{ N */ N N#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) N#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) N#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ N ((STATE) == DMA_MemoryInc_Disable)) X#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || ((STATE) == DMA_MemoryInc_Disable)) N/** N * @} N */ N N/** @defgroup DMA_peripheral_data_size N * @{ N */ N N#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) N#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) N#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) N#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ N ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ N ((SIZE) == DMA_PeripheralDataSize_Word)) X#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || ((SIZE) == DMA_PeripheralDataSize_HalfWord) || ((SIZE) == DMA_PeripheralDataSize_Word)) N/** N * @} N */ N N/** @defgroup DMA_memory_data_size N * @{ N */ N N#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) N#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) N#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) N#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ N ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ N ((SIZE) == DMA_MemoryDataSize_Word)) X#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) || ((SIZE) == DMA_MemoryDataSize_Word)) N/** N * @} N */ N N/** @defgroup DMA_circular_normal_mode N * @{ N */ N N#define DMA_Mode_Circular ((uint32_t)0x00000020) N#define DMA_Mode_Normal ((uint32_t)0x00000000) N#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) N/** N * @} N */ N N/** @defgroup DMA_priority_level N * @{ N */ N N#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) N#define DMA_Priority_High ((uint32_t)0x00002000) N#define DMA_Priority_Medium ((uint32_t)0x00001000) N#define DMA_Priority_Low ((uint32_t)0x00000000) N#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ N ((PRIORITY) == DMA_Priority_High) || \ N ((PRIORITY) == DMA_Priority_Medium) || \ N ((PRIORITY) == DMA_Priority_Low)) X#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || ((PRIORITY) == DMA_Priority_High) || ((PRIORITY) == DMA_Priority_Medium) || ((PRIORITY) == DMA_Priority_Low)) N/** N * @} N */ N N/** @defgroup DMA_memory_to_memory N * @{ N */ N N#define DMA_M2M_Enable ((uint32_t)0x00004000) N#define DMA_M2M_Disable ((uint32_t)0x00000000) N#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) N N/** N * @} N */ N N/** @defgroup DMA_interrupts_definition N * @{ N */ N N#define DMA_IT_TC ((uint32_t)0x00000002) N#define DMA_IT_HT ((uint32_t)0x00000004) N#define DMA_IT_TE ((uint32_t)0x00000008) N#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) N N#define DMA1_IT_GL1 ((uint32_t)0x00000001) N#define DMA1_IT_TC1 ((uint32_t)0x00000002) N#define DMA1_IT_HT1 ((uint32_t)0x00000004) N#define DMA1_IT_TE1 ((uint32_t)0x00000008) N#define DMA1_IT_GL2 ((uint32_t)0x00000010) N#define DMA1_IT_TC2 ((uint32_t)0x00000020) N#define DMA1_IT_HT2 ((uint32_t)0x00000040) N#define DMA1_IT_TE2 ((uint32_t)0x00000080) N#define DMA1_IT_GL3 ((uint32_t)0x00000100) N#define DMA1_IT_TC3 ((uint32_t)0x00000200) N#define DMA1_IT_HT3 ((uint32_t)0x00000400) N#define DMA1_IT_TE3 ((uint32_t)0x00000800) N#define DMA1_IT_GL4 ((uint32_t)0x00001000) N#define DMA1_IT_TC4 ((uint32_t)0x00002000) N#define DMA1_IT_HT4 ((uint32_t)0x00004000) N#define DMA1_IT_TE4 ((uint32_t)0x00008000) N#define DMA1_IT_GL5 ((uint32_t)0x00010000) N#define DMA1_IT_TC5 ((uint32_t)0x00020000) N#define DMA1_IT_HT5 ((uint32_t)0x00040000) N#define DMA1_IT_TE5 ((uint32_t)0x00080000) N#define DMA1_IT_GL6 ((uint32_t)0x00100000) N#define DMA1_IT_TC6 ((uint32_t)0x00200000) N#define DMA1_IT_HT6 ((uint32_t)0x00400000) N#define DMA1_IT_TE6 ((uint32_t)0x00800000) N#define DMA1_IT_GL7 ((uint32_t)0x01000000) N#define DMA1_IT_TC7 ((uint32_t)0x02000000) N#define DMA1_IT_HT7 ((uint32_t)0x04000000) N#define DMA1_IT_TE7 ((uint32_t)0x08000000) N N#define DMA2_IT_GL1 ((uint32_t)0x10000001) N#define DMA2_IT_TC1 ((uint32_t)0x10000002) N#define DMA2_IT_HT1 ((uint32_t)0x10000004) N#define DMA2_IT_TE1 ((uint32_t)0x10000008) N#define DMA2_IT_GL2 ((uint32_t)0x10000010) N#define DMA2_IT_TC2 ((uint32_t)0x10000020) N#define DMA2_IT_HT2 ((uint32_t)0x10000040) N#define DMA2_IT_TE2 ((uint32_t)0x10000080) N#define DMA2_IT_GL3 ((uint32_t)0x10000100) N#define DMA2_IT_TC3 ((uint32_t)0x10000200) N#define DMA2_IT_HT3 ((uint32_t)0x10000400) N#define DMA2_IT_TE3 ((uint32_t)0x10000800) N#define DMA2_IT_GL4 ((uint32_t)0x10001000) N#define DMA2_IT_TC4 ((uint32_t)0x10002000) N#define DMA2_IT_HT4 ((uint32_t)0x10004000) N#define DMA2_IT_TE4 ((uint32_t)0x10008000) N#define DMA2_IT_GL5 ((uint32_t)0x10010000) N#define DMA2_IT_TC5 ((uint32_t)0x10020000) N#define DMA2_IT_HT5 ((uint32_t)0x10040000) N#define DMA2_IT_TE5 ((uint32_t)0x10080000) N N#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) N N#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ N ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ N ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ N ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ N ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ N ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ N ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ N ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ N ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ N ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ N ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ N ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ N ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ N ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ N ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ N ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ N ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ N ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ N ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ N ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ N ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ N ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ N ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ N ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) X#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) N N/** N * @} N */ N N/** @defgroup DMA_flags_definition N * @{ N */ N#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) N#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) N#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) N#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) N#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) N#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) N#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) N#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) N#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) N#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) N#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) N#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) N#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) N#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) N#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) N#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) N#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) N#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) N#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) N#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) N#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) N#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) N#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) N#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) N#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) N#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) N#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) N#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) N N#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) N#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) N#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) N#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) N#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) N#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) N#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) N#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) N#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) N#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) N#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) N#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) N#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) N#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) N#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) N#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) N#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) N#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) N#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) N#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) N N#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) N N#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ N ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ N ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ N ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ N ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ N ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ N ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ N ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ N ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ N ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ N ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ N ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ N ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ N ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ N ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ N ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ N ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ N ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ N ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ N ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ N ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ N ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ N ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ N ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) X#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) N/** N * @} N */ N N/** @defgroup DMA_Buffer_Size N * @{ N */ N N#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup DMA_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup DMA_Exported_Functions N * @{ N */ N Nvoid DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); Nvoid DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); Nvoid DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); Nvoid DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); Nvoid DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); Nvoid DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); Nuint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); NFlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); Nvoid DMA_ClearFlag(uint32_t DMAy_FLAG); NITStatus DMA_GetITStatus(uint32_t DMAy_IT); Nvoid DMA_ClearITPendingBit(uint32_t DMAy_IT); N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_DMA_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 36 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_exti.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_exti.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the EXTI firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_EXTI_H N#define __STM32F10x_EXTI_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup EXTI N * @{ N */ N N/** @defgroup EXTI_Exported_Types N * @{ N */ N N/** N * @brief EXTI mode enumeration N */ N Ntypedef enum N{ N EXTI_Mode_Interrupt = 0x00, N EXTI_Mode_Event = 0x04 N}EXTIMode_TypeDef; N N#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) N N/** N * @brief EXTI Trigger enumeration N */ N Ntypedef enum N{ N EXTI_Trigger_Rising = 0x08, N EXTI_Trigger_Falling = 0x0C, N EXTI_Trigger_Rising_Falling = 0x10 N}EXTITrigger_TypeDef; N N#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ N ((TRIGGER) == EXTI_Trigger_Falling) || \ N ((TRIGGER) == EXTI_Trigger_Rising_Falling)) X#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) || ((TRIGGER) == EXTI_Trigger_Rising_Falling)) N/** N * @brief EXTI Init Structure definition N */ N Ntypedef struct N{ N uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. N This parameter can be any combination of @ref EXTI_Lines */ N N EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. N This parameter can be a value of @ref EXTIMode_TypeDef */ N N EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. N This parameter can be a value of @ref EXTIMode_TypeDef */ N N FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. N This parameter can be set either to ENABLE or DISABLE */ N}EXTI_InitTypeDef; N N/** N * @} N */ N N/** @defgroup EXTI_Exported_Constants N * @{ N */ N N/** @defgroup EXTI_Lines N * @{ N */ N N#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ N#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ N#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ N#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ N#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ N#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ N#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ N#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ N#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ N#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ N#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ N#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ N#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ N#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ N#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ N#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ N#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ N#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ N#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS N Wakeup from suspend event */ N#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ N N#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) N#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ N ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ N ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ N ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ N ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ N ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ N ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ N ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ N ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ N ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) X#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) N N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup EXTI_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup EXTI_Exported_Functions N * @{ N */ N Nvoid EXTI_DeInit(void); Nvoid EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); Nvoid EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); Nvoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); NFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); Nvoid EXTI_ClearFlag(uint32_t EXTI_Line); NITStatus EXTI_GetITStatus(uint32_t EXTI_Line); Nvoid EXTI_ClearITPendingBit(uint32_t EXTI_Line); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_EXTI_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 37 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_flash.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_flash.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the FLASH N * firmware library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_FLASH_H N#define __STM32F10x_FLASH_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup FLASH N * @{ N */ N N/** @defgroup FLASH_Exported_Types N * @{ N */ N N/** N * @brief FLASH Status N */ N Ntypedef enum N{ N FLASH_BUSY = 1, N FLASH_ERROR_PG, N FLASH_ERROR_WRP, N FLASH_COMPLETE, N FLASH_TIMEOUT N}FLASH_Status; N N/** N * @} N */ N N/** @defgroup FLASH_Exported_Constants N * @{ N */ N N/** @defgroup Flash_Latency N * @{ N */ N N#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ N#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ N#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ N#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ N ((LATENCY) == FLASH_Latency_1) || \ N ((LATENCY) == FLASH_Latency_2)) X#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || ((LATENCY) == FLASH_Latency_1) || ((LATENCY) == FLASH_Latency_2)) N/** N * @} N */ N N/** @defgroup Half_Cycle_Enable_Disable N * @{ N */ N N#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ N#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ N#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ N ((STATE) == FLASH_HalfCycleAccess_Disable)) X#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || ((STATE) == FLASH_HalfCycleAccess_Disable)) N/** N * @} N */ N N/** @defgroup Prefetch_Buffer_Enable_Disable N * @{ N */ N N#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ N#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ N#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ N ((STATE) == FLASH_PrefetchBuffer_Disable)) X#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || ((STATE) == FLASH_PrefetchBuffer_Disable)) N/** N * @} N */ N N/** @defgroup Option_Bytes_Write_Protection N * @{ N */ N N/* Values to be used with STM32 Low and Medium density devices */ N#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ N#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ N#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ N#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ N#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ N#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ N#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ N#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ N N/* Values to be used with STM32 Medium-density devices */ N#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ N#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ N#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ N#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ N#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ N#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ N#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ N#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ N#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ N#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ N#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ N#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ N#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ N#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ N#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ N#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ N#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ N#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ N#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ N#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ N#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ N#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ N#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ N#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ N N/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ N#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 0 to 1 */ N#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 2 to 3 */ N#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 4 to 5 */ N#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 6 to 7 */ N#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 8 to 9 */ N#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 10 to 11 */ N#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 12 to 13 */ N#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 14 to 15 */ N#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 16 to 17 */ N#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 18 to 19 */ N#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 20 to 21 */ N#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 22 to 23 */ N#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 24 to 25 */ N#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 26 to 27 */ N#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 28 to 29 */ N#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 30 to 31 */ N#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 32 to 33 */ N#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 34 to 35 */ N#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 36 to 37 */ N#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 38 to 39 */ N#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 40 to 41 */ N#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 42 to 43 */ N#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 44 to 45 */ N#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 46 to 47 */ N#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 48 to 49 */ N#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 50 to 51 */ N#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 52 to 53 */ N#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 54 to 55 */ N#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 56 to 57 */ N#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 58 to 59 */ N#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: N Write protection of page 60 to 61 */ N#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ N#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ N#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ N N#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ N N#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) N N#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) N N#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) N N/** N * @} N */ N N/** @defgroup Option_Bytes_IWatchdog N * @{ N */ N N#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ N#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ N#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) N N/** N * @} N */ N N/** @defgroup Option_Bytes_nRST_STOP N * @{ N */ N N#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ N#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ N#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) N N/** N * @} N */ N N/** @defgroup Option_Bytes_nRST_STDBY N * @{ N */ N N#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ N#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ N#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) N N#ifdef STM32F10X_XL S/** S * @} S */ S/** @defgroup FLASH_Boot S * @{ S */ S#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position S and this parameter is selected the device will boot from Bank1(Default) */ S#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position S and this parameter is selected the device will boot from Bank 2 or Bank 1, S depending on the activation of the bank */ S#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) N#endif N/** N * @} N */ N/** @defgroup FLASH_Interrupts N * @{ N */ N#ifdef STM32F10X_XL S#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ S#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ S S#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ S#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ S S#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ S#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ S#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) N#else N#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ N#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ N#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ N#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ N N#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) N#endif N N/** N * @} N */ N N/** @defgroup FLASH_Flags N * @{ N */ N#ifdef STM32F10X_XL S#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ S#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ S#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ S#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ S S#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ S#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ S#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ S#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ S S#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ S#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ S#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ S#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ S#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ S S#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) S#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ S ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ S ((FLAG) == FLASH_FLAG_OPTERR)|| \ S ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ S ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ S ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ S ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) X#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || ((FLAG) == FLASH_FLAG_OPTERR)|| ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) N#else N#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ N#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ N#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ N#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ N#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ N N#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ N#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ N#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ N#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ N N#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) N#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ N ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ N ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ N ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ N ((FLAG) == FLASH_FLAG_OPTERR)) X#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || ((FLAG) == FLASH_FLAG_OPTERR)) N#endif N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup FLASH_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup FLASH_Exported_Functions N * @{ N */ N N/*------------ Functions used for all STM32F10x devices -----*/ Nvoid FLASH_SetLatency(uint32_t FLASH_Latency); Nvoid FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); Nvoid FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); Nvoid FLASH_Unlock(void); Nvoid FLASH_Lock(void); NFLASH_Status FLASH_ErasePage(uint32_t Page_Address); NFLASH_Status FLASH_EraseAllPages(void); NFLASH_Status FLASH_EraseOptionBytes(void); NFLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); NFLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); NFLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); NFLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); NFLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); NFLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); Nuint32_t FLASH_GetUserOptionByte(void); Nuint32_t FLASH_GetWriteProtectionOptionByte(void); NFlagStatus FLASH_GetReadOutProtectionStatus(void); NFlagStatus FLASH_GetPrefetchBufferStatus(void); Nvoid FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); NFlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); Nvoid FLASH_ClearFlag(uint32_t FLASH_FLAG); NFLASH_Status FLASH_GetStatus(void); NFLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); N N/*------------ New function used for all STM32F10x devices -----*/ Nvoid FLASH_UnlockBank1(void); Nvoid FLASH_LockBank1(void); NFLASH_Status FLASH_EraseAllBank1Pages(void); NFLASH_Status FLASH_GetBank1Status(void); NFLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); N N#ifdef STM32F10X_XL S/*---- New Functions used only with STM32F10x_XL density devices -----*/ Svoid FLASH_UnlockBank2(void); Svoid FLASH_LockBank2(void); SFLASH_Status FLASH_EraseAllBank2Pages(void); SFLASH_Status FLASH_GetBank2Status(void); SFLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); SFLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); N#endif N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_FLASH_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 38 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_fsmc.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_fsmc.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_fsmc.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the FSMC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_FSMC_H N#define __STM32F10x_FSMC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup FSMC N * @{ N */ N N/** @defgroup FSMC_Exported_Types N * @{ N */ N N/** N * @brief Timing parameters For NOR/SRAM Banks N */ N Ntypedef struct N{ N uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure N the duration of the address setup time. N This parameter can be a value between 0 and 0xF. N @note: It is not used with synchronous NOR Flash memories. */ N N uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure N the duration of the address hold time. N This parameter can be a value between 0 and 0xF. N @note: It is not used with synchronous NOR Flash memories.*/ N N uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure N the duration of the data setup time. N This parameter can be a value between 0 and 0xFF. N @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ N N uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure N the duration of the bus turnaround. N This parameter can be a value between 0 and 0xF. N @note: It is only used for multiplexed NOR Flash memories. */ N N uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. N This parameter can be a value between 1 and 0xF. N @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ N N uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue N to the memory before getting the first data. N The value of this parameter depends on the memory type as shown below: N - It must be set to 0 in case of a CRAM N - It is don't care in asynchronous NOR, SRAM or ROM accesses N - It may assume a value between 0 and 0xF in NOR Flash memories N with synchronous burst mode enable */ N N uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. N This parameter can be a value of @ref FSMC_Access_Mode */ N}FSMC_NORSRAMTimingInitTypeDef; N N/** N * @brief FSMC NOR/SRAM Init structure definition N */ N Ntypedef struct N{ N uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. N This parameter can be a value of @ref FSMC_NORSRAM_Bank */ N N uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are N multiplexed on the databus or not. N This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ N N uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to N the corresponding memory bank. N This parameter can be a value of @ref FSMC_Memory_Type */ N N uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. N This parameter can be a value of @ref FSMC_Data_Width */ N N uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, N valid only with synchronous burst Flash memories. N This parameter can be a value of @ref FSMC_Burst_Access_Mode */ N N uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, N valid only with asynchronous Flash memories. N This parameter can be a value of @ref FSMC_AsynchronousWait */ N N uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing N the Flash memory in burst mode. N This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ N N uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash N memory, valid only when accessing Flash memories in burst mode. N This parameter can be a value of @ref FSMC_Wrap_Mode */ N N uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one N clock cycle before the wait state or during the wait state, N valid only when accessing memories in burst mode. N This parameter can be a value of @ref FSMC_Wait_Timing */ N N uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. N This parameter can be a value of @ref FSMC_Write_Operation */ N N uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait N signal, valid for Flash memory access in burst mode. N This parameter can be a value of @ref FSMC_Wait_Signal */ N N uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. N This parameter can be a value of @ref FSMC_Extended_Mode */ N N uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. N This parameter can be a value of @ref FSMC_Write_Burst */ N N FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ N N FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ N}FSMC_NORSRAMInitTypeDef; N N/** N * @brief Timing parameters For FSMC NAND and PCCARD Banks N */ N Ntypedef struct N{ N uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before N the command assertion for NAND-Flash read or write access N to common/Attribute or I/O memory space (depending on N the memory space timing to be configured). N This parameter can be a value between 0 and 0xFF.*/ N N uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the N command for NAND-Flash read or write access to N common/Attribute or I/O memory space (depending on the N memory space timing to be configured). N This parameter can be a number between 0x00 and 0xFF */ N N uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address N (and data for write access) after the command deassertion N for NAND-Flash read or write access to common/Attribute N or I/O memory space (depending on the memory space timing N to be configured). N This parameter can be a number between 0x00 and 0xFF */ N N uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the N databus is kept in HiZ after the start of a NAND-Flash N write access to common/Attribute or I/O memory space (depending N on the memory space timing to be configured). N This parameter can be a number between 0x00 and 0xFF */ N}FSMC_NAND_PCCARDTimingInitTypeDef; N N/** N * @brief FSMC NAND Init structure definition N */ N Ntypedef struct N{ N uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. N This parameter can be a value of @ref FSMC_NAND_Bank */ N N uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. N This parameter can be any value of @ref FSMC_Wait_feature */ N N uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. N This parameter can be any value of @ref FSMC_Data_Width */ N N uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. N This parameter can be any value of @ref FSMC_ECC */ N N uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. N This parameter can be any value of @ref FSMC_ECC_Page_Size */ N N uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the N delay between CLE low and RE low. N This parameter can be a value between 0 and 0xFF. */ N N uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the N delay between ALE low and RE low. N This parameter can be a number between 0x0 and 0xFF */ N N FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ N N FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ N}FSMC_NANDInitTypeDef; N N/** N * @brief FSMC PCCARD Init structure definition N */ N Ntypedef struct N{ N uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. N This parameter can be any value of @ref FSMC_Wait_feature */ N N uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the N delay between CLE low and RE low. N This parameter can be a value between 0 and 0xFF. */ N N uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the N delay between ALE low and RE low. N This parameter can be a number between 0x0 and 0xFF */ N N N FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ N N FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ N N FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ N}FSMC_PCCARDInitTypeDef; N N/** N * @} N */ N N/** @defgroup FSMC_Exported_Constants N * @{ N */ N N/** @defgroup FSMC_NORSRAM_Bank N * @{ N */ N#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) N#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) N#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) N#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) N/** N * @} N */ N N/** @defgroup FSMC_NAND_Bank N * @{ N */ N#define FSMC_Bank2_NAND ((uint32_t)0x00000010) N#define FSMC_Bank3_NAND ((uint32_t)0x00000100) N/** N * @} N */ N N/** @defgroup FSMC_PCCARD_Bank N * @{ N */ N#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) N/** N * @} N */ N N#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ N ((BANK) == FSMC_Bank1_NORSRAM2) || \ N ((BANK) == FSMC_Bank1_NORSRAM3) || \ N ((BANK) == FSMC_Bank1_NORSRAM4)) X#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || ((BANK) == FSMC_Bank1_NORSRAM2) || ((BANK) == FSMC_Bank1_NORSRAM3) || ((BANK) == FSMC_Bank1_NORSRAM4)) N N#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ N ((BANK) == FSMC_Bank3_NAND)) X#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND)) N N#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ N ((BANK) == FSMC_Bank3_NAND) || \ N ((BANK) == FSMC_Bank4_PCCARD)) X#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND) || ((BANK) == FSMC_Bank4_PCCARD)) N N#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ N ((BANK) == FSMC_Bank3_NAND) || \ N ((BANK) == FSMC_Bank4_PCCARD)) X#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND) || ((BANK) == FSMC_Bank4_PCCARD)) N N/** @defgroup NOR_SRAM_Controller N * @{ N */ N N/** @defgroup FSMC_Data_Address_Bus_Multiplexing N * @{ N */ N N#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) N#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) N#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ N ((MUX) == FSMC_DataAddressMux_Enable)) X#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || ((MUX) == FSMC_DataAddressMux_Enable)) N N/** N * @} N */ N N/** @defgroup FSMC_Memory_Type N * @{ N */ N N#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) N#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) N#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) N#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ N ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ N ((MEMORY) == FSMC_MemoryType_NOR)) X#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || ((MEMORY) == FSMC_MemoryType_PSRAM)|| ((MEMORY) == FSMC_MemoryType_NOR)) N N/** N * @} N */ N N/** @defgroup FSMC_Data_Width N * @{ N */ N N#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) N#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) N#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ N ((WIDTH) == FSMC_MemoryDataWidth_16b)) X#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || ((WIDTH) == FSMC_MemoryDataWidth_16b)) N N/** N * @} N */ N N/** @defgroup FSMC_Burst_Access_Mode N * @{ N */ N N#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) N#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) N#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ N ((STATE) == FSMC_BurstAccessMode_Enable)) X#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || ((STATE) == FSMC_BurstAccessMode_Enable)) N/** N * @} N */ N N/** @defgroup FSMC_AsynchronousWait N * @{ N */ N#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) N#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) N#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ N ((STATE) == FSMC_AsynchronousWait_Enable)) X#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || ((STATE) == FSMC_AsynchronousWait_Enable)) N N/** N * @} N */ N N/** @defgroup FSMC_Wait_Signal_Polarity N * @{ N */ N N#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) N#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) N#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ N ((POLARITY) == FSMC_WaitSignalPolarity_High)) X#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || ((POLARITY) == FSMC_WaitSignalPolarity_High)) N N/** N * @} N */ N N/** @defgroup FSMC_Wrap_Mode N * @{ N */ N N#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) N#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) N#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ N ((MODE) == FSMC_WrapMode_Enable)) X#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || ((MODE) == FSMC_WrapMode_Enable)) N N/** N * @} N */ N N/** @defgroup FSMC_Wait_Timing N * @{ N */ N N#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) N#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) N#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ N ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) X#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) N N/** N * @} N */ N N/** @defgroup FSMC_Write_Operation N * @{ N */ N N#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) N#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) N#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ N ((OPERATION) == FSMC_WriteOperation_Enable)) X#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || ((OPERATION) == FSMC_WriteOperation_Enable)) N N/** N * @} N */ N N/** @defgroup FSMC_Wait_Signal N * @{ N */ N N#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) N#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) N#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ N ((SIGNAL) == FSMC_WaitSignal_Enable)) X#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || ((SIGNAL) == FSMC_WaitSignal_Enable)) N/** N * @} N */ N N/** @defgroup FSMC_Extended_Mode N * @{ N */ N N#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) N#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) N N#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ N ((MODE) == FSMC_ExtendedMode_Enable)) X#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || ((MODE) == FSMC_ExtendedMode_Enable)) N N/** N * @} N */ N N/** @defgroup FSMC_Write_Burst N * @{ N */ N N#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) N#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) N#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ N ((BURST) == FSMC_WriteBurst_Enable)) X#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || ((BURST) == FSMC_WriteBurst_Enable)) N/** N * @} N */ N N/** @defgroup FSMC_Address_Setup_Time N * @{ N */ N N#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) N N/** N * @} N */ N N/** @defgroup FSMC_Address_Hold_Time N * @{ N */ N N#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) N N/** N * @} N */ N N/** @defgroup FSMC_Data_Setup_Time N * @{ N */ N N#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) N N/** N * @} N */ N N/** @defgroup FSMC_Bus_Turn_around_Duration N * @{ N */ N N#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) N N/** N * @} N */ N N/** @defgroup FSMC_CLK_Division N * @{ N */ N N#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) N N/** N * @} N */ N N/** @defgroup FSMC_Data_Latency N * @{ N */ N N#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) N N/** N * @} N */ N N/** @defgroup FSMC_Access_Mode N * @{ N */ N N#define FSMC_AccessMode_A ((uint32_t)0x00000000) N#define FSMC_AccessMode_B ((uint32_t)0x10000000) N#define FSMC_AccessMode_C ((uint32_t)0x20000000) N#define FSMC_AccessMode_D ((uint32_t)0x30000000) N#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ N ((MODE) == FSMC_AccessMode_B) || \ N ((MODE) == FSMC_AccessMode_C) || \ N ((MODE) == FSMC_AccessMode_D)) X#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || ((MODE) == FSMC_AccessMode_B) || ((MODE) == FSMC_AccessMode_C) || ((MODE) == FSMC_AccessMode_D)) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup NAND_PCCARD_Controller N * @{ N */ N N/** @defgroup FSMC_Wait_feature N * @{ N */ N N#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) N#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) N#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ N ((FEATURE) == FSMC_Waitfeature_Enable)) X#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || ((FEATURE) == FSMC_Waitfeature_Enable)) N N/** N * @} N */ N N N/** @defgroup FSMC_ECC N * @{ N */ N N#define FSMC_ECC_Disable ((uint32_t)0x00000000) N#define FSMC_ECC_Enable ((uint32_t)0x00000040) N#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ N ((STATE) == FSMC_ECC_Enable)) X#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || ((STATE) == FSMC_ECC_Enable)) N N/** N * @} N */ N N/** @defgroup FSMC_ECC_Page_Size N * @{ N */ N N#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) N#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) N#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) N#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) N#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) N#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) N#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ N ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ N ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ N ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ N ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ N ((SIZE) == FSMC_ECCPageSize_8192Bytes)) X#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || ((SIZE) == FSMC_ECCPageSize_512Bytes) || ((SIZE) == FSMC_ECCPageSize_1024Bytes) || ((SIZE) == FSMC_ECCPageSize_2048Bytes) || ((SIZE) == FSMC_ECCPageSize_4096Bytes) || ((SIZE) == FSMC_ECCPageSize_8192Bytes)) N N/** N * @} N */ N N/** @defgroup FSMC_TCLR_Setup_Time N * @{ N */ N N#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) N N/** N * @} N */ N N/** @defgroup FSMC_TAR_Setup_Time N * @{ N */ N N#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) N N/** N * @} N */ N N/** @defgroup FSMC_Setup_Time N * @{ N */ N N#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) N N/** N * @} N */ N N/** @defgroup FSMC_Wait_Setup_Time N * @{ N */ N N#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) N N/** N * @} N */ N N/** @defgroup FSMC_Hold_Setup_Time N * @{ N */ N N#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) N N/** N * @} N */ N N/** @defgroup FSMC_HiZ_Setup_Time N * @{ N */ N N#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) N N/** N * @} N */ N N/** @defgroup FSMC_Interrupt_sources N * @{ N */ N N#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) N#define FSMC_IT_Level ((uint32_t)0x00000010) N#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) N#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) N#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ N ((IT) == FSMC_IT_Level) || \ N ((IT) == FSMC_IT_FallingEdge)) X#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || ((IT) == FSMC_IT_Level) || ((IT) == FSMC_IT_FallingEdge)) N/** N * @} N */ N N/** @defgroup FSMC_Flags N * @{ N */ N N#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) N#define FSMC_FLAG_Level ((uint32_t)0x00000002) N#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) N#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) N#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ N ((FLAG) == FSMC_FLAG_Level) || \ N ((FLAG) == FSMC_FLAG_FallingEdge) || \ N ((FLAG) == FSMC_FLAG_FEMPT)) X#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || ((FLAG) == FSMC_FLAG_Level) || ((FLAG) == FSMC_FLAG_FallingEdge) || ((FLAG) == FSMC_FLAG_FEMPT)) N N#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) N N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup FSMC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup FSMC_Exported_Functions N * @{ N */ N Nvoid FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); Nvoid FSMC_NANDDeInit(uint32_t FSMC_Bank); Nvoid FSMC_PCCARDDeInit(void); Nvoid FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); Nvoid FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); Nvoid FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); Nvoid FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); Nvoid FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); Nvoid FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); Nvoid FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); Nvoid FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); Nvoid FSMC_PCCARDCmd(FunctionalState NewState); Nvoid FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); Nuint32_t FSMC_GetECC(uint32_t FSMC_Bank); Nvoid FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); NFlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); Nvoid FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); NITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); Nvoid FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_FSMC_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 39 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_gpio.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_gpio.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the GPIO N * firmware library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_GPIO_H N#define __STM32F10x_GPIO_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup GPIO N * @{ N */ N N/** @defgroup GPIO_Exported_Types N * @{ N */ N N#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ N ((PERIPH) == GPIOB) || \ N ((PERIPH) == GPIOC) || \ N ((PERIPH) == GPIOD) || \ N ((PERIPH) == GPIOE) || \ N ((PERIPH) == GPIOF) || \ N ((PERIPH) == GPIOG)) X#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG)) N N/** N * @brief Output Maximum frequency selection N */ N Ntypedef enum N{ N GPIO_Speed_10MHz = 1, N GPIO_Speed_2MHz, N GPIO_Speed_50MHz N}GPIOSpeed_TypeDef; N#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ N ((SPEED) == GPIO_Speed_50MHz)) X#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_50MHz)) N N/** N * @brief Configuration Mode enumeration N */ N Ntypedef enum N{ GPIO_Mode_AIN = 0x0, N GPIO_Mode_IN_FLOATING = 0x04, N GPIO_Mode_IPD = 0x28, N GPIO_Mode_IPU = 0x48, N GPIO_Mode_Out_OD = 0x14, N GPIO_Mode_Out_PP = 0x10, N GPIO_Mode_AF_OD = 0x1C, N GPIO_Mode_AF_PP = 0x18 N}GPIOMode_TypeDef; N N#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ N ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ N ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ N ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) X#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) N N/** N * @brief GPIO Init structure definition N */ N Ntypedef struct N{ N uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. N This parameter can be any value of @ref GPIO_pins_define */ N N GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. N This parameter can be a value of @ref GPIOSpeed_TypeDef */ N N GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. N This parameter can be a value of @ref GPIOMode_TypeDef */ N}GPIO_InitTypeDef; N N N/** N * @brief Bit_SET and Bit_RESET enumeration N */ N Ntypedef enum N{ Bit_RESET = 0, N Bit_SET N}BitAction; N N#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) N N/** N * @} N */ N N/** @defgroup GPIO_Exported_Constants N * @{ N */ N N/** @defgroup GPIO_pins_define N * @{ N */ N N#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ N#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ N#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ N#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ N#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ N#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ N#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ N#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ N#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ N#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ N#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ N#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ N#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ N#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ N#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ N#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ N#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ N N#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) N N#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ N ((PIN) == GPIO_Pin_1) || \ N ((PIN) == GPIO_Pin_2) || \ N ((PIN) == GPIO_Pin_3) || \ N ((PIN) == GPIO_Pin_4) || \ N ((PIN) == GPIO_Pin_5) || \ N ((PIN) == GPIO_Pin_6) || \ N ((PIN) == GPIO_Pin_7) || \ N ((PIN) == GPIO_Pin_8) || \ N ((PIN) == GPIO_Pin_9) || \ N ((PIN) == GPIO_Pin_10) || \ N ((PIN) == GPIO_Pin_11) || \ N ((PIN) == GPIO_Pin_12) || \ N ((PIN) == GPIO_Pin_13) || \ N ((PIN) == GPIO_Pin_14) || \ N ((PIN) == GPIO_Pin_15)) X#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15)) N N/** N * @} N */ N N/** @defgroup GPIO_Remap_define N * @{ N */ N N#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ N#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ N#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ N#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ N#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ N#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ N#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ N#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ N#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ N#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ N#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ N#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ N#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ N#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ N#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ N#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ N#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ N#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ N#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ N#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ N#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ N#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ N#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ N#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ N#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ N#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ N#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ N#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ N#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected N to TIM2 Internal Trigger 1 for calibration N (only for Connectivity line devices) */ N#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ N N#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ N#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ N#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ N#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ N#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ N N#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ N#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ N#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ N#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ N#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ N#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ N N#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ N#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ N#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, N only for High density Value line devices) */ N N#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ N ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ N ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ N ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ N ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ N ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ N ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ N ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ N ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ N ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ N ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ N ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ N ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ N ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ N ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ N ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ N ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ N ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ N ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ N ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ N ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ N ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) X#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) N N/** N * @} N */ N N/** @defgroup GPIO_Port_Sources N * @{ N */ N N#define GPIO_PortSourceGPIOA ((uint8_t)0x00) N#define GPIO_PortSourceGPIOB ((uint8_t)0x01) N#define GPIO_PortSourceGPIOC ((uint8_t)0x02) N#define GPIO_PortSourceGPIOD ((uint8_t)0x03) N#define GPIO_PortSourceGPIOE ((uint8_t)0x04) N#define GPIO_PortSourceGPIOF ((uint8_t)0x05) N#define GPIO_PortSourceGPIOG ((uint8_t)0x06) N#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOE)) X#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || ((PORTSOURCE) == GPIO_PortSourceGPIOB) || ((PORTSOURCE) == GPIO_PortSourceGPIOC) || ((PORTSOURCE) == GPIO_PortSourceGPIOD) || ((PORTSOURCE) == GPIO_PortSourceGPIOE)) N N#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ N ((PORTSOURCE) == GPIO_PortSourceGPIOG)) X#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || ((PORTSOURCE) == GPIO_PortSourceGPIOB) || ((PORTSOURCE) == GPIO_PortSourceGPIOC) || ((PORTSOURCE) == GPIO_PortSourceGPIOD) || ((PORTSOURCE) == GPIO_PortSourceGPIOE) || ((PORTSOURCE) == GPIO_PortSourceGPIOF) || ((PORTSOURCE) == GPIO_PortSourceGPIOG)) N N/** N * @} N */ N N/** @defgroup GPIO_Pin_sources N * @{ N */ N N#define GPIO_PinSource0 ((uint8_t)0x00) N#define GPIO_PinSource1 ((uint8_t)0x01) N#define GPIO_PinSource2 ((uint8_t)0x02) N#define GPIO_PinSource3 ((uint8_t)0x03) N#define GPIO_PinSource4 ((uint8_t)0x04) N#define GPIO_PinSource5 ((uint8_t)0x05) N#define GPIO_PinSource6 ((uint8_t)0x06) N#define GPIO_PinSource7 ((uint8_t)0x07) N#define GPIO_PinSource8 ((uint8_t)0x08) N#define GPIO_PinSource9 ((uint8_t)0x09) N#define GPIO_PinSource10 ((uint8_t)0x0A) N#define GPIO_PinSource11 ((uint8_t)0x0B) N#define GPIO_PinSource12 ((uint8_t)0x0C) N#define GPIO_PinSource13 ((uint8_t)0x0D) N#define GPIO_PinSource14 ((uint8_t)0x0E) N#define GPIO_PinSource15 ((uint8_t)0x0F) N N#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ N ((PINSOURCE) == GPIO_PinSource1) || \ N ((PINSOURCE) == GPIO_PinSource2) || \ N ((PINSOURCE) == GPIO_PinSource3) || \ N ((PINSOURCE) == GPIO_PinSource4) || \ N ((PINSOURCE) == GPIO_PinSource5) || \ N ((PINSOURCE) == GPIO_PinSource6) || \ N ((PINSOURCE) == GPIO_PinSource7) || \ N ((PINSOURCE) == GPIO_PinSource8) || \ N ((PINSOURCE) == GPIO_PinSource9) || \ N ((PINSOURCE) == GPIO_PinSource10) || \ N ((PINSOURCE) == GPIO_PinSource11) || \ N ((PINSOURCE) == GPIO_PinSource12) || \ N ((PINSOURCE) == GPIO_PinSource13) || \ N ((PINSOURCE) == GPIO_PinSource14) || \ N ((PINSOURCE) == GPIO_PinSource15)) X#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || ((PINSOURCE) == GPIO_PinSource1) || ((PINSOURCE) == GPIO_PinSource2) || ((PINSOURCE) == GPIO_PinSource3) || ((PINSOURCE) == GPIO_PinSource4) || ((PINSOURCE) == GPIO_PinSource5) || ((PINSOURCE) == GPIO_PinSource6) || ((PINSOURCE) == GPIO_PinSource7) || ((PINSOURCE) == GPIO_PinSource8) || ((PINSOURCE) == GPIO_PinSource9) || ((PINSOURCE) == GPIO_PinSource10) || ((PINSOURCE) == GPIO_PinSource11) || ((PINSOURCE) == GPIO_PinSource12) || ((PINSOURCE) == GPIO_PinSource13) || ((PINSOURCE) == GPIO_PinSource14) || ((PINSOURCE) == GPIO_PinSource15)) N N/** N * @} N */ N N/** @defgroup Ethernet_Media_Interface N * @{ N */ N#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) N#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) N N#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ N ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) X#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) N N/** N * @} N */ N/** N * @} N */ N N/** @defgroup GPIO_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup GPIO_Exported_Functions N * @{ N */ N Nvoid GPIO_DeInit(GPIO_TypeDef* GPIOx); Nvoid GPIO_AFIODeInit(void); Nvoid GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); Nvoid GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); Nuint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); Nuint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); Nuint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); Nuint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); Nvoid GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); Nvoid GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); Nvoid GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); Nvoid GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); Nvoid GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); Nvoid GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); Nvoid GPIO_EventOutputCmd(FunctionalState NewState); Nvoid GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); Nvoid GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); Nvoid GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_GPIO_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 40 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_i2c.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_i2c.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the I2C firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_I2C_H N#define __STM32F10x_I2C_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup I2C N * @{ N */ N N/** @defgroup I2C_Exported_Types N * @{ N */ N N/** N * @brief I2C Init structure definition N */ N Ntypedef struct N{ N uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. N This parameter must be set to a value lower than 400kHz */ N N uint16_t I2C_Mode; /*!< Specifies the I2C mode. N This parameter can be a value of @ref I2C_mode */ N N uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. N This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ N N uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. N This parameter can be a 7-bit or 10-bit address. */ N N uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. N This parameter can be a value of @ref I2C_acknowledgement */ N N uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. N This parameter can be a value of @ref I2C_acknowledged_address */ N}I2C_InitTypeDef; N N/** N * @} N */ N N N/** @defgroup I2C_Exported_Constants N * @{ N */ N N#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ N ((PERIPH) == I2C2)) X#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2)) N/** @defgroup I2C_mode N * @{ N */ N N#define I2C_Mode_I2C ((uint16_t)0x0000) N#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) N#define I2C_Mode_SMBusHost ((uint16_t)0x000A) N#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ N ((MODE) == I2C_Mode_SMBusDevice) || \ N ((MODE) == I2C_Mode_SMBusHost)) X#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || ((MODE) == I2C_Mode_SMBusDevice) || ((MODE) == I2C_Mode_SMBusHost)) N/** N * @} N */ N N/** @defgroup I2C_duty_cycle_in_fast_mode N * @{ N */ N N#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ N#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ N#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ N ((CYCLE) == I2C_DutyCycle_2)) X#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || ((CYCLE) == I2C_DutyCycle_2)) N/** N * @} N */ N N/** @defgroup I2C_acknowledgement N * @{ N */ N N#define I2C_Ack_Enable ((uint16_t)0x0400) N#define I2C_Ack_Disable ((uint16_t)0x0000) N#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ N ((STATE) == I2C_Ack_Disable)) X#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || ((STATE) == I2C_Ack_Disable)) N/** N * @} N */ N N/** @defgroup I2C_transfer_direction N * @{ N */ N N#define I2C_Direction_Transmitter ((uint8_t)0x00) N#define I2C_Direction_Receiver ((uint8_t)0x01) N#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ N ((DIRECTION) == I2C_Direction_Receiver)) X#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || ((DIRECTION) == I2C_Direction_Receiver)) N/** N * @} N */ N N/** @defgroup I2C_acknowledged_address N * @{ N */ N N#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) N#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) N#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ N ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) X#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) N/** N * @} N */ N N/** @defgroup I2C_registers N * @{ N */ N N#define I2C_Register_CR1 ((uint8_t)0x00) N#define I2C_Register_CR2 ((uint8_t)0x04) N#define I2C_Register_OAR1 ((uint8_t)0x08) N#define I2C_Register_OAR2 ((uint8_t)0x0C) N#define I2C_Register_DR ((uint8_t)0x10) N#define I2C_Register_SR1 ((uint8_t)0x14) N#define I2C_Register_SR2 ((uint8_t)0x18) N#define I2C_Register_CCR ((uint8_t)0x1C) N#define I2C_Register_TRISE ((uint8_t)0x20) N#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ N ((REGISTER) == I2C_Register_CR2) || \ N ((REGISTER) == I2C_Register_OAR1) || \ N ((REGISTER) == I2C_Register_OAR2) || \ N ((REGISTER) == I2C_Register_DR) || \ N ((REGISTER) == I2C_Register_SR1) || \ N ((REGISTER) == I2C_Register_SR2) || \ N ((REGISTER) == I2C_Register_CCR) || \ N ((REGISTER) == I2C_Register_TRISE)) X#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || ((REGISTER) == I2C_Register_CR2) || ((REGISTER) == I2C_Register_OAR1) || ((REGISTER) == I2C_Register_OAR2) || ((REGISTER) == I2C_Register_DR) || ((REGISTER) == I2C_Register_SR1) || ((REGISTER) == I2C_Register_SR2) || ((REGISTER) == I2C_Register_CCR) || ((REGISTER) == I2C_Register_TRISE)) N/** N * @} N */ N N/** @defgroup I2C_SMBus_alert_pin_level N * @{ N */ N N#define I2C_SMBusAlert_Low ((uint16_t)0x2000) N#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) N#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ N ((ALERT) == I2C_SMBusAlert_High)) X#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || ((ALERT) == I2C_SMBusAlert_High)) N/** N * @} N */ N N/** @defgroup I2C_PEC_position N * @{ N */ N N#define I2C_PECPosition_Next ((uint16_t)0x0800) N#define I2C_PECPosition_Current ((uint16_t)0xF7FF) N#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ N ((POSITION) == I2C_PECPosition_Current)) X#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || ((POSITION) == I2C_PECPosition_Current)) N/** N * @} N */ N N/** @defgroup I2C_NCAK_position N * @{ N */ N N#define I2C_NACKPosition_Next ((uint16_t)0x0800) N#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) N#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ N ((POSITION) == I2C_NACKPosition_Current)) X#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || ((POSITION) == I2C_NACKPosition_Current)) N/** N * @} N */ N N/** @defgroup I2C_interrupts_definition N * @{ N */ N N#define I2C_IT_BUF ((uint16_t)0x0400) N#define I2C_IT_EVT ((uint16_t)0x0200) N#define I2C_IT_ERR ((uint16_t)0x0100) N#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) N/** N * @} N */ N N/** @defgroup I2C_interrupts_definition N * @{ N */ N N#define I2C_IT_SMBALERT ((uint32_t)0x01008000) N#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) N#define I2C_IT_PECERR ((uint32_t)0x01001000) N#define I2C_IT_OVR ((uint32_t)0x01000800) N#define I2C_IT_AF ((uint32_t)0x01000400) N#define I2C_IT_ARLO ((uint32_t)0x01000200) N#define I2C_IT_BERR ((uint32_t)0x01000100) N#define I2C_IT_TXE ((uint32_t)0x06000080) N#define I2C_IT_RXNE ((uint32_t)0x06000040) N#define I2C_IT_STOPF ((uint32_t)0x02000010) N#define I2C_IT_ADD10 ((uint32_t)0x02000008) N#define I2C_IT_BTF ((uint32_t)0x02000004) N#define I2C_IT_ADDR ((uint32_t)0x02000002) N#define I2C_IT_SB ((uint32_t)0x02000001) N N#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) N N#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ N ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ N ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ N ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ N ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ N ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ N ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) X#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) N/** N * @} N */ N N/** @defgroup I2C_flags_definition N * @{ N */ N N/** N * @brief SR2 register flags N */ N N#define I2C_FLAG_DUALF ((uint32_t)0x00800000) N#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) N#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) N#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) N#define I2C_FLAG_TRA ((uint32_t)0x00040000) N#define I2C_FLAG_BUSY ((uint32_t)0x00020000) N#define I2C_FLAG_MSL ((uint32_t)0x00010000) N N/** N * @brief SR1 register flags N */ N N#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) N#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) N#define I2C_FLAG_PECERR ((uint32_t)0x10001000) N#define I2C_FLAG_OVR ((uint32_t)0x10000800) N#define I2C_FLAG_AF ((uint32_t)0x10000400) N#define I2C_FLAG_ARLO ((uint32_t)0x10000200) N#define I2C_FLAG_BERR ((uint32_t)0x10000100) N#define I2C_FLAG_TXE ((uint32_t)0x10000080) N#define I2C_FLAG_RXNE ((uint32_t)0x10000040) N#define I2C_FLAG_STOPF ((uint32_t)0x10000010) N#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) N#define I2C_FLAG_BTF ((uint32_t)0x10000004) N#define I2C_FLAG_ADDR ((uint32_t)0x10000002) N#define I2C_FLAG_SB ((uint32_t)0x10000001) N N#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) N N#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ N ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ N ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ N ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ N ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ N ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ N ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ N ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ N ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ N ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ N ((FLAG) == I2C_FLAG_SB)) X#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || ((FLAG) == I2C_FLAG_SB)) N/** N * @} N */ N N/** @defgroup I2C_Events N * @{ N */ N N/*======================================== N N I2C Master Events (Events grouped in order of communication) N ==========================================*/ N/** N * @brief Communication start N * N * After sending the START condition (I2C_GenerateSTART() function) the master N * has to wait for this event. It means that the Start condition has been correctly N * released on the I2C bus (the bus is free, no other devices is communicating). N * N */ N/* --EV5 */ N#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ N N/** N * @brief Address Acknowledge N * N * After checking on EV5 (start condition correctly released on the bus), the N * master sends the address of the slave(s) with which it will communicate N * (I2C_Send7bitAddress() function, it also determines the direction of the communication: N * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges N * his address. If an acknowledge is sent on the bus, one of the following events will N * be set: N * N * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED N * event is set. N * N * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED N * is set N * N * 3) In case of 10-Bit addressing mode, the master (just after generating the START N * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() N * function). Then master should wait on EV9. It means that the 10-bit addressing N * header has been correctly sent on the bus. Then master should send the second part of N * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master N * should wait for event EV6. N * N */ N N/* --EV6 */ N#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ N#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ N/* --EV9 */ N#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ N N/** N * @brief Communication events N * N * If a communication is established (START condition generated and slave address N * acknowledged) then the master has to check on one of the following events for N * communication procedures: N * N * 1) Master Receiver mode: The master has to wait on the event EV7 then to read N * the data received from the slave (I2C_ReceiveData() function). N * N * 2) Master Transmitter mode: The master has to send data (I2C_SendData() N * function) then to wait on event EV8 or EV8_2. N * These two events are similar: N * - EV8 means that the data has been written in the data register and is N * being shifted out. N * - EV8_2 means that the data has been physically shifted out and output N * on the bus. N * In most cases, using EV8 is sufficient for the application. N * Using EV8_2 leads to a slower communication but ensure more reliable test. N * EV8_2 is also more suitable than EV8 for testing on the last data transmission N * (before Stop condition generation). N * N * @note In case the user software does not guarantee that this event EV7 is N * managed before the current byte end of transfer, then user may check on EV7 N * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). N * In this case the communication may be slower. N * N */ N N/* Master RECEIVER mode -----------------------------*/ N/* --EV7 */ N#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ N N/* Master TRANSMITTER mode --------------------------*/ N/* --EV8 */ N#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ N/* --EV8_2 */ N#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ N N N/*======================================== N N I2C Slave Events (Events grouped in order of communication) N ==========================================*/ N N/** N * @brief Communication start events N * N * Wait on one of these events at the start of the communication. It means that N * the I2C peripheral detected a Start condition on the bus (generated by master N * device) followed by the peripheral address. The peripheral generates an ACK N * condition on the bus (if the acknowledge feature is enabled through function N * I2C_AcknowledgeConfig()) and the events listed above are set : N * N * 1) In normal case (only one address managed by the slave), when the address N * sent by the master matches the own address of the peripheral (configured by N * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set N * (where XXX could be TRANSMITTER or RECEIVER). N * N * 2) In case the address sent by the master matches the second address of the N * peripheral (configured by the function I2C_OwnAddress2Config() and enabled N * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED N * (where XXX could be TRANSMITTER or RECEIVER) are set. N * N * 3) In case the address sent by the master is General Call (address 0x00) and N * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) N * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. N * N */ N N/* --EV1 (all the events below are variants of EV1) */ N/* 1) Case of One Single Address managed by the slave */ N#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ N#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ N N/* 2) Case of Dual address managed by the slave */ N#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ N#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ N N/* 3) Case of General Call enabled for the slave */ N#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ N N/** N * @brief Communication events N * N * Wait on one of these events when EV1 has already been checked and: N * N * - Slave RECEIVER mode: N * - EV2: When the application is expecting a data byte to be received. N * - EV4: When the application is expecting the end of the communication: master N * sends a stop condition and data transmission is stopped. N * N * - Slave Transmitter mode: N * - EV3: When a byte has been transmitted by the slave and the application is expecting N * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and N * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be N * used when the user software doesn't guarantee the EV3 is managed before the N * current byte end of transfer. N * - EV3_2: When the master sends a NACK in order to tell slave that data transmission N * shall end (before sending the STOP condition). In this case slave has to stop sending N * data bytes and expect a Stop condition on the bus. N * N * @note In case the user software does not guarantee that the event EV2 is N * managed before the current byte end of transfer, then user may check on EV2 N * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). N * In this case the communication may be slower. N * N */ N N/* Slave RECEIVER mode --------------------------*/ N/* --EV2 */ N#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ N/* --EV4 */ N#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ N N/* Slave TRANSMITTER mode -----------------------*/ N/* --EV3 */ N#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ N#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ N/* --EV3_2 */ N#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ N N/*=========================== End of Events Description ==========================================*/ N N#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ N ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ N ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ N ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ N ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ N ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ N ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ N ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ N ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ N ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ N ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ N ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ N ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ N ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ N ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ N ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) X#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) N/** N * @} N */ N N/** @defgroup I2C_own_address1 N * @{ N */ N N#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) N/** N * @} N */ N N/** @defgroup I2C_clock_speed N * @{ N */ N N#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup I2C_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup I2C_Exported_Functions N * @{ N */ N Nvoid I2C_DeInit(I2C_TypeDef* I2Cx); Nvoid I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); Nvoid I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); Nvoid I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); Nvoid I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); Nvoid I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); Nuint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); Nvoid I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); Nuint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); Nvoid I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); Nvoid I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); Nvoid I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); Nvoid I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); Nuint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); Nvoid I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); Nvoid I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); N N/** N * @brief N **************************************************************************************** N * N * I2C State Monitoring Functions N * N **************************************************************************************** N * This I2C driver provides three different ways for I2C state monitoring N * depending on the application requirements and constraints: N * N * N * 1) Basic state monitoring: N * Using I2C_CheckEvent() function: N * It compares the status registers (SR1 and SR2) content to a given event N * (can be the combination of one or more flags). N * It returns SUCCESS if the current status includes the given flags N * and returns ERROR if one or more flags are missing in the current status. N * - When to use: N * - This function is suitable for most applications as well as for startup N * activity since the events are fully described in the product reference manual N * (RM0008). N * - It is also suitable for users who need to define their own events. N * - Limitations: N * - If an error occurs (ie. error flags are set besides to the monitored flags), N * the I2C_CheckEvent() function may return SUCCESS despite the communication N * hold or corrupted real state. N * In this case, it is advised to use error interrupts to monitor the error N * events and handle them in the interrupt IRQ handler. N * N * @note N * For error management, it is advised to use the following functions: N * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). N * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. N * Where x is the peripheral instance (I2C1, I2C2 ...) N * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() N * in order to determine which error occurred. N * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() N * and/or I2C_GenerateStop() in order to clear the error flag and source, N * and return to correct communication status. N * N * N * 2) Advanced state monitoring: N * Using the function I2C_GetLastEvent() which returns the image of both status N * registers in a single word (uint32_t) (Status Register 2 value is shifted left N * by 16 bits and concatenated to Status Register 1). N * - When to use: N * - This function is suitable for the same applications above but it allows to N * overcome the limitations of I2C_GetFlagStatus() function (see below). N * The returned value could be compared to events already defined in the N * library (stm32f10x_i2c.h) or to custom values defined by user. N * - This function is suitable when multiple flags are monitored at the same time. N * - At the opposite of I2C_CheckEvent() function, this function allows user to N * choose when an event is accepted (when all events flags are set and no N * other flags are set or just when the needed flags are set like N * I2C_CheckEvent() function). N * - Limitations: N * - User may need to define his own events. N * - Same remark concerning the error management is applicable for this N * function if user decides to check only regular communication flags (and N * ignores error flags). N * N * N * 3) Flag-based state monitoring: N * Using the function I2C_GetFlagStatus() which simply returns the status of N * one single flag (ie. I2C_FLAG_RXNE ...). N * - When to use: N * - This function could be used for specific applications or in debug phase. N * - It is suitable when only one flag checking is needed (most I2C events N * are monitored through multiple flags). N * - Limitations: N * - When calling this function, the Status register is accessed. Some flags are N * cleared when the status register is accessed. So checking the status N * of one Flag, may clear other ones. N * - Function may need to be called twice or more in order to monitor one N * single event. N * N */ N N/** N * N * 1) Basic state monitoring N ******************************************************************************* N */ NErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); N/** N * N * 2) Advanced state monitoring N ******************************************************************************* N */ Nuint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); N/** N * N * 3) Flag-based state monitoring N ******************************************************************************* N */ NFlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); N/** N * N ******************************************************************************* N */ N Nvoid I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); NITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); Nvoid I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_I2C_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 41 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_iwdg.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_iwdg.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_iwdg.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the IWDG N * firmware library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_IWDG_H N#define __STM32F10x_IWDG_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup IWDG N * @{ N */ N N/** @defgroup IWDG_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup IWDG_Exported_Constants N * @{ N */ N N/** @defgroup IWDG_WriteAccess N * @{ N */ N N#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) N#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) N#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ N ((ACCESS) == IWDG_WriteAccess_Disable)) X#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || ((ACCESS) == IWDG_WriteAccess_Disable)) N/** N * @} N */ N N/** @defgroup IWDG_prescaler N * @{ N */ N N#define IWDG_Prescaler_4 ((uint8_t)0x00) N#define IWDG_Prescaler_8 ((uint8_t)0x01) N#define IWDG_Prescaler_16 ((uint8_t)0x02) N#define IWDG_Prescaler_32 ((uint8_t)0x03) N#define IWDG_Prescaler_64 ((uint8_t)0x04) N#define IWDG_Prescaler_128 ((uint8_t)0x05) N#define IWDG_Prescaler_256 ((uint8_t)0x06) N#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ N ((PRESCALER) == IWDG_Prescaler_8) || \ N ((PRESCALER) == IWDG_Prescaler_16) || \ N ((PRESCALER) == IWDG_Prescaler_32) || \ N ((PRESCALER) == IWDG_Prescaler_64) || \ N ((PRESCALER) == IWDG_Prescaler_128)|| \ N ((PRESCALER) == IWDG_Prescaler_256)) X#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || ((PRESCALER) == IWDG_Prescaler_8) || ((PRESCALER) == IWDG_Prescaler_16) || ((PRESCALER) == IWDG_Prescaler_32) || ((PRESCALER) == IWDG_Prescaler_64) || ((PRESCALER) == IWDG_Prescaler_128)|| ((PRESCALER) == IWDG_Prescaler_256)) N/** N * @} N */ N N/** @defgroup IWDG_Flag N * @{ N */ N N#define IWDG_FLAG_PVU ((uint16_t)0x0001) N#define IWDG_FLAG_RVU ((uint16_t)0x0002) N#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) N#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup IWDG_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup IWDG_Exported_Functions N * @{ N */ N Nvoid IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); Nvoid IWDG_SetPrescaler(uint8_t IWDG_Prescaler); Nvoid IWDG_SetReload(uint16_t Reload); Nvoid IWDG_ReloadCounter(void); Nvoid IWDG_Enable(void); NFlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_IWDG_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 42 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_pwr.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_pwr.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_pwr.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the PWR firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_PWR_H N#define __STM32F10x_PWR_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup PWR N * @{ N */ N N/** @defgroup PWR_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup PWR_Exported_Constants N * @{ N */ N N/** @defgroup PVD_detection_level N * @{ N */ N N#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) N#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) N#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) N#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) N#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) N#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) N#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) N#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) N#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ N ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ N ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ N ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) X#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) N/** N * @} N */ N N/** @defgroup Regulator_state_is_STOP_mode N * @{ N */ N N#define PWR_Regulator_ON ((uint32_t)0x00000000) N#define PWR_Regulator_LowPower ((uint32_t)0x00000001) N#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ N ((REGULATOR) == PWR_Regulator_LowPower)) X#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || ((REGULATOR) == PWR_Regulator_LowPower)) N/** N * @} N */ N N/** @defgroup STOP_mode_entry N * @{ N */ N N#define PWR_STOPEntry_WFI ((uint8_t)0x01) N#define PWR_STOPEntry_WFE ((uint8_t)0x02) N#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) N N/** N * @} N */ N N/** @defgroup PWR_Flag N * @{ N */ N N#define PWR_FLAG_WU ((uint32_t)0x00000001) N#define PWR_FLAG_SB ((uint32_t)0x00000002) N#define PWR_FLAG_PVDO ((uint32_t)0x00000004) N#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ N ((FLAG) == PWR_FLAG_PVDO)) X#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || ((FLAG) == PWR_FLAG_PVDO)) N N#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup PWR_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup PWR_Exported_Functions N * @{ N */ N Nvoid PWR_DeInit(void); Nvoid PWR_BackupAccessCmd(FunctionalState NewState); Nvoid PWR_PVDCmd(FunctionalState NewState); Nvoid PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); Nvoid PWR_WakeUpPinCmd(FunctionalState NewState); Nvoid PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); Nvoid PWR_EnterSTANDBYMode(void); NFlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); Nvoid PWR_ClearFlag(uint32_t PWR_FLAG); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_PWR_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 43 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_rcc.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_rcc.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the RCC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_RCC_H N#define __STM32F10x_RCC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup RCC N * @{ N */ N N/** @defgroup RCC_Exported_Types N * @{ N */ N Ntypedef struct N{ N uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ N uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ N uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ N uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ N uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ N}RCC_ClocksTypeDef; N N/** N * @} N */ N N/** @defgroup RCC_Exported_Constants N * @{ N */ N N/** @defgroup HSE_configuration N * @{ N */ N N#define RCC_HSE_OFF ((uint32_t)0x00000000) N#define RCC_HSE_ON ((uint32_t)0x00010000) N#define RCC_HSE_Bypass ((uint32_t)0x00040000) N#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ N ((HSE) == RCC_HSE_Bypass)) X#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_Bypass)) N N/** N * @} N */ N N/** @defgroup PLL_entry_clock_source N * @{ N */ N N#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) N N#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) X#if !0L && !0L && !0L && !0L N #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) N #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) N #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ N ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ N ((SOURCE) == RCC_PLLSource_HSE_Div2)) X #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || ((SOURCE) == RCC_PLLSource_HSE_Div1) || ((SOURCE) == RCC_PLLSource_HSE_Div2)) N#else S #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) S #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ S ((SOURCE) == RCC_PLLSource_PREDIV1)) X #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || ((SOURCE) == RCC_PLLSource_PREDIV1)) N#endif /* STM32F10X_CL */ N N/** N * @} N */ N N/** @defgroup PLL_multiplication_factor N * @{ N */ N#ifndef STM32F10X_CL N #define RCC_PLLMul_2 ((uint32_t)0x00000000) N #define RCC_PLLMul_3 ((uint32_t)0x00040000) N #define RCC_PLLMul_4 ((uint32_t)0x00080000) N #define RCC_PLLMul_5 ((uint32_t)0x000C0000) N #define RCC_PLLMul_6 ((uint32_t)0x00100000) N #define RCC_PLLMul_7 ((uint32_t)0x00140000) N #define RCC_PLLMul_8 ((uint32_t)0x00180000) N #define RCC_PLLMul_9 ((uint32_t)0x001C0000) N #define RCC_PLLMul_10 ((uint32_t)0x00200000) N #define RCC_PLLMul_11 ((uint32_t)0x00240000) N #define RCC_PLLMul_12 ((uint32_t)0x00280000) N #define RCC_PLLMul_13 ((uint32_t)0x002C0000) N #define RCC_PLLMul_14 ((uint32_t)0x00300000) N #define RCC_PLLMul_15 ((uint32_t)0x00340000) N #define RCC_PLLMul_16 ((uint32_t)0x00380000) N #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ N ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ N ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ N ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ N ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ N ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ N ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ N ((MUL) == RCC_PLLMul_16)) X #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || ((MUL) == RCC_PLLMul_16)) N N#else S #define RCC_PLLMul_4 ((uint32_t)0x00080000) S #define RCC_PLLMul_5 ((uint32_t)0x000C0000) S #define RCC_PLLMul_6 ((uint32_t)0x00100000) S #define RCC_PLLMul_7 ((uint32_t)0x00140000) S #define RCC_PLLMul_8 ((uint32_t)0x00180000) S #define RCC_PLLMul_9 ((uint32_t)0x001C0000) S #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) S S #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ S ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ S ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ S ((MUL) == RCC_PLLMul_6_5)) X #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || ((MUL) == RCC_PLLMul_6_5)) N#endif /* STM32F10X_CL */ N/** N * @} N */ N N/** @defgroup PREDIV1_division_factor N * @{ N */ N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) X#if 0L || 0L || 0L || 0L S #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) S #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) S #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) S #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) S #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) S #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) S #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) S #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) S #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) S #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) S #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) S #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) S #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) S #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) S #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) S #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) S S #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ S ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ S ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ S ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ S ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ S ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ S ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ S ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) X #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) N#endif N/** N * @} N */ N N N/** @defgroup PREDIV1_clock_source N * @{ N */ N#ifdef STM32F10X_CL S/* PREDIV1 clock source (for STM32 connectivity line devices) */ S #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) S #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) S S #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ S ((SOURCE) == RCC_PREDIV1_Source_PLL2)) X #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || ((SOURCE) == RCC_PREDIV1_Source_PLL2)) S#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) X#elif 0L || 0L || 0L S/* PREDIV1 clock source (for STM32 Value line devices) */ S #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) S S #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) N#endif N/** N * @} N */ N N#ifdef STM32F10X_CL S/** @defgroup PREDIV2_division_factor S * @{ S */ S S #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) S #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) S #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) S #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) S #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) S #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) S #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) S #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) S #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) S #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) S #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) S #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) S #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) S #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) S #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) S #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) S S #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ S ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ S ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ S ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ S ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ S ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ S ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ S ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) X #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) S/** S * @} S */ S S S/** @defgroup PLL2_multiplication_factor S * @{ S */ S S #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) S #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) S #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) S #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) S #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) S #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) S #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) S #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) S #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) S S #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ S ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ S ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ S ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ S ((MUL) == RCC_PLL2Mul_20)) X #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || ((MUL) == RCC_PLL2Mul_20)) S/** S * @} S */ S S S/** @defgroup PLL3_multiplication_factor S * @{ S */ S S #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) S #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) S #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) S #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) S #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) S #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) S #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) S #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) S #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) S S #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ S ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ S ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ S ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ S ((MUL) == RCC_PLL3Mul_20)) X #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || ((MUL) == RCC_PLL3Mul_20)) S/** S * @} S */ S N#endif /* STM32F10X_CL */ N N N/** @defgroup System_clock_source N * @{ N */ N N#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) N#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) N#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) N#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ N ((SOURCE) == RCC_SYSCLKSource_HSE) || \ N ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) X#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || ((SOURCE) == RCC_SYSCLKSource_HSE) || ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) N/** N * @} N */ N N/** @defgroup AHB_clock_source N * @{ N */ N N#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) N#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) N#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) N#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) N#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) N#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) N#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) N#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) N#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) N#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ N ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ N ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ N ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ N ((HCLK) == RCC_SYSCLK_Div512)) X#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || ((HCLK) == RCC_SYSCLK_Div512)) N/** N * @} N */ N N/** @defgroup APB1_APB2_clock_source N * @{ N */ N N#define RCC_HCLK_Div1 ((uint32_t)0x00000000) N#define RCC_HCLK_Div2 ((uint32_t)0x00000400) N#define RCC_HCLK_Div4 ((uint32_t)0x00000500) N#define RCC_HCLK_Div8 ((uint32_t)0x00000600) N#define RCC_HCLK_Div16 ((uint32_t)0x00000700) N#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ N ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ N ((PCLK) == RCC_HCLK_Div16)) X#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || ((PCLK) == RCC_HCLK_Div16)) N/** N * @} N */ N N/** @defgroup RCC_Interrupt_source N * @{ N */ N N#define RCC_IT_LSIRDY ((uint8_t)0x01) N#define RCC_IT_LSERDY ((uint8_t)0x02) N#define RCC_IT_HSIRDY ((uint8_t)0x04) N#define RCC_IT_HSERDY ((uint8_t)0x08) N#define RCC_IT_PLLRDY ((uint8_t)0x10) N#define RCC_IT_CSS ((uint8_t)0x80) N N#ifndef STM32F10X_CL N #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) N #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ N ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ N ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) X #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) N #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) N#else S #define RCC_IT_PLL2RDY ((uint8_t)0x20) S #define RCC_IT_PLL3RDY ((uint8_t)0x40) S #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) S #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ S ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ S ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ S ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) X #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) S #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) N#endif /* STM32F10X_CL */ N N N/** N * @} N */ N N#ifndef STM32F10X_CL N/** @defgroup USB_Device_clock_source N * @{ N */ N N #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) N #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) N N #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ N ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) X #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) N/** N * @} N */ N#else S/** @defgroup USB_OTG_FS_clock_source S * @{ S */ S #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) S #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) S S #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ S ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) X #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) S/** S * @} S */ N#endif /* STM32F10X_CL */ N N N#ifdef STM32F10X_CL S/** @defgroup I2S2_clock_source S * @{ S */ S #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) S #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) S S #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ S ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) X #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) S/** S * @} S */ S S/** @defgroup I2S3_clock_source S * @{ S */ S #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) S #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) S S #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ S ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) X #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) S/** S * @} S */ N#endif /* STM32F10X_CL */ N N N/** @defgroup ADC_clock_source N * @{ N */ N N#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) N#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) N#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) N#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) N#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ N ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) X#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) N/** N * @} N */ N N/** @defgroup LSE_configuration N * @{ N */ N N#define RCC_LSE_OFF ((uint8_t)0x00) N#define RCC_LSE_ON ((uint8_t)0x01) N#define RCC_LSE_Bypass ((uint8_t)0x04) N#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ N ((LSE) == RCC_LSE_Bypass)) X#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_Bypass)) N/** N * @} N */ N N/** @defgroup RTC_clock_source N * @{ N */ N N#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) N#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) N#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) N#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ N ((SOURCE) == RCC_RTCCLKSource_LSI) || \ N ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) X#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || ((SOURCE) == RCC_RTCCLKSource_LSI) || ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) N/** N * @} N */ N N/** @defgroup AHB_peripheral N * @{ N */ N N#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) N#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) N#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) N#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) N#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) N N#ifndef STM32F10X_CL N #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) N #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) N #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) N#else S #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) S #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) S #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) S #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) S S #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) S #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) N#endif /* STM32F10X_CL */ N/** N * @} N */ N N/** @defgroup APB2_peripheral N * @{ N */ N N#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) N#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) N#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) N#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) N#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) N#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) N#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) N#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) N#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) N#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) N#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) N#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) N#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) N#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) N#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) N#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) N#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) N#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) N#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) N#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) N#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) N N#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) N/** N * @} N */ N N/** @defgroup APB1_peripheral N * @{ N */ N N#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) N#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) N#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) N#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) N#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) N#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) N#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) N#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) N#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) N#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) N#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) N#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) N#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) N#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) N#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) N#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) N#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) N#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) N#define RCC_APB1Periph_USB ((uint32_t)0x00800000) N#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) N#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) N#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) N#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) N#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) N#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) N N#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) N N/** N * @} N */ N N/** @defgroup Clock_source_to_output_on_MCO_pin N * @{ N */ N N#define RCC_MCO_NoClock ((uint8_t)0x00) N#define RCC_MCO_SYSCLK ((uint8_t)0x04) N#define RCC_MCO_HSI ((uint8_t)0x05) N#define RCC_MCO_HSE ((uint8_t)0x06) N#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) N N#ifndef STM32F10X_CL N #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ N ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ N ((MCO) == RCC_MCO_PLLCLK_Div2)) X #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK_Div2)) N#else S #define RCC_MCO_PLL2CLK ((uint8_t)0x08) S #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) S #define RCC_MCO_XT1 ((uint8_t)0x0A) S #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) S S #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ S ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ S ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ S ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ S ((MCO) == RCC_MCO_PLL3CLK)) X #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || ((MCO) == RCC_MCO_PLL3CLK)) N#endif /* STM32F10X_CL */ N N/** N * @} N */ N N/** @defgroup RCC_Flag N * @{ N */ N N#define RCC_FLAG_HSIRDY ((uint8_t)0x21) N#define RCC_FLAG_HSERDY ((uint8_t)0x31) N#define RCC_FLAG_PLLRDY ((uint8_t)0x39) N#define RCC_FLAG_LSERDY ((uint8_t)0x41) N#define RCC_FLAG_LSIRDY ((uint8_t)0x61) N#define RCC_FLAG_PINRST ((uint8_t)0x7A) N#define RCC_FLAG_PORRST ((uint8_t)0x7B) N#define RCC_FLAG_SFTRST ((uint8_t)0x7C) N#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) N#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) N#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) N N#ifndef STM32F10X_CL N #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ N ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ N ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ N ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ N ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ N ((FLAG) == RCC_FLAG_LPWRRST)) X #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)) N#else S #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) S #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) S #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ S ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ S ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ S ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ S ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ S ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ S ((FLAG) == RCC_FLAG_LPWRRST)) X #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)) N#endif /* STM32F10X_CL */ N N#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup RCC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup RCC_Exported_Functions N * @{ N */ N Nvoid RCC_DeInit(void); Nvoid RCC_HSEConfig(uint32_t RCC_HSE); NErrorStatus RCC_WaitForHSEStartUp(void); Nvoid RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); Nvoid RCC_HSICmd(FunctionalState NewState); Nvoid RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); Nvoid RCC_PLLCmd(FunctionalState NewState); N N#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) X#if 0L || 0L || 0L || 0L S void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); N#endif N N#ifdef STM32F10X_CL S void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); S void RCC_PLL2Config(uint32_t RCC_PLL2Mul); S void RCC_PLL2Cmd(FunctionalState NewState); S void RCC_PLL3Config(uint32_t RCC_PLL3Mul); S void RCC_PLL3Cmd(FunctionalState NewState); N#endif /* STM32F10X_CL */ N Nvoid RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); Nuint8_t RCC_GetSYSCLKSource(void); Nvoid RCC_HCLKConfig(uint32_t RCC_SYSCLK); Nvoid RCC_PCLK1Config(uint32_t RCC_HCLK); Nvoid RCC_PCLK2Config(uint32_t RCC_HCLK); Nvoid RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); N N#ifndef STM32F10X_CL N void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); N#else S void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); N#endif /* STM32F10X_CL */ N Nvoid RCC_ADCCLKConfig(uint32_t RCC_PCLK2); N N#ifdef STM32F10X_CL S void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); S void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); N#endif /* STM32F10X_CL */ N Nvoid RCC_LSEConfig(uint8_t RCC_LSE); Nvoid RCC_LSICmd(FunctionalState NewState); Nvoid RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); Nvoid RCC_RTCCLKCmd(FunctionalState NewState); Nvoid RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); Nvoid RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); Nvoid RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); Nvoid RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); N N#ifdef STM32F10X_CL Svoid RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); N#endif /* STM32F10X_CL */ N Nvoid RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); Nvoid RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); Nvoid RCC_BackupResetCmd(FunctionalState NewState); Nvoid RCC_ClockSecuritySystemCmd(FunctionalState NewState); Nvoid RCC_MCOConfig(uint8_t RCC_MCO); NFlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); Nvoid RCC_ClearFlag(void); NITStatus RCC_GetITStatus(uint8_t RCC_IT); Nvoid RCC_ClearITPendingBit(uint8_t RCC_IT); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_RCC_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 44 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_rtc.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rtc.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_rtc.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the RTC firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_RTC_H N#define __STM32F10x_RTC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup RTC N * @{ N */ N N/** @defgroup RTC_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup RTC_Exported_Constants N * @{ N */ N N/** @defgroup RTC_interrupts_define N * @{ N */ N N#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ N#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ N#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ N#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) N#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ N ((IT) == RTC_IT_SEC)) X#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || ((IT) == RTC_IT_SEC)) N/** N * @} N */ N N/** @defgroup RTC_interrupts_flags N * @{ N */ N N#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ N#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ N#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ N#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ N#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ N#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) N#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ N ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ N ((FLAG) == RTC_FLAG_SEC)) X#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || ((FLAG) == RTC_FLAG_SEC)) N#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup RTC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup RTC_Exported_Functions N * @{ N */ N Nvoid RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); Nvoid RTC_EnterConfigMode(void); Nvoid RTC_ExitConfigMode(void); Nuint32_t RTC_GetCounter(void); Nvoid RTC_SetCounter(uint32_t CounterValue); Nvoid RTC_SetPrescaler(uint32_t PrescalerValue); Nvoid RTC_SetAlarm(uint32_t AlarmValue); Nuint32_t RTC_GetDivider(void); Nvoid RTC_WaitForLastTask(void); Nvoid RTC_WaitForSynchro(void); NFlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); Nvoid RTC_ClearFlag(uint16_t RTC_FLAG); NITStatus RTC_GetITStatus(uint16_t RTC_IT); Nvoid RTC_ClearITPendingBit(uint16_t RTC_IT); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_RTC_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 45 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_sdio.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_sdio.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_sdio.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the SDIO firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_SDIO_H N#define __STM32F10x_SDIO_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup SDIO N * @{ N */ N N/** @defgroup SDIO_Exported_Types N * @{ N */ N Ntypedef struct N{ N uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. N This parameter can be a value of @ref SDIO_Clock_Edge */ N N uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is N enabled or disabled. N This parameter can be a value of @ref SDIO_Clock_Bypass */ N N uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or N disabled when the bus is idle. N This parameter can be a value of @ref SDIO_Clock_Power_Save */ N N uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. N This parameter can be a value of @ref SDIO_Bus_Wide */ N N uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. N This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ N N uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. N This parameter can be a value between 0x00 and 0xFF. */ N N} SDIO_InitTypeDef; N Ntypedef struct N{ N uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent N to a card as part of a command message. If a command N contains an argument, it must be loaded into this register N before writing the command to the command register */ N N uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ N N uint32_t SDIO_Response; /*!< Specifies the SDIO response type. N This parameter can be a value of @ref SDIO_Response_Type */ N N uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. N This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ N N uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) N is enabled or disabled. N This parameter can be a value of @ref SDIO_CPSM_State */ N} SDIO_CmdInitTypeDef; N Ntypedef struct N{ N uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ N N uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ N N uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. N This parameter can be a value of @ref SDIO_Data_Block_Size */ N N uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer N is a read or write. N This parameter can be a value of @ref SDIO_Transfer_Direction */ N N uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. N This parameter can be a value of @ref SDIO_Transfer_Type */ N N uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) N is enabled or disabled. N This parameter can be a value of @ref SDIO_DPSM_State */ N} SDIO_DataInitTypeDef; N N/** N * @} N */ N N/** @defgroup SDIO_Exported_Constants N * @{ N */ N N/** @defgroup SDIO_Clock_Edge N * @{ N */ N N#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) N#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) N#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ N ((EDGE) == SDIO_ClockEdge_Falling)) X#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || ((EDGE) == SDIO_ClockEdge_Falling)) N/** N * @} N */ N N/** @defgroup SDIO_Clock_Bypass N * @{ N */ N N#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) N#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) N#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ N ((BYPASS) == SDIO_ClockBypass_Enable)) X#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || ((BYPASS) == SDIO_ClockBypass_Enable)) N/** N * @} N */ N N/** @defgroup SDIO_Clock_Power_Save N * @{ N */ N N#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) N#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) N#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ N ((SAVE) == SDIO_ClockPowerSave_Enable)) X#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || ((SAVE) == SDIO_ClockPowerSave_Enable)) N/** N * @} N */ N N/** @defgroup SDIO_Bus_Wide N * @{ N */ N N#define SDIO_BusWide_1b ((uint32_t)0x00000000) N#define SDIO_BusWide_4b ((uint32_t)0x00000800) N#define SDIO_BusWide_8b ((uint32_t)0x00001000) N#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ N ((WIDE) == SDIO_BusWide_8b)) X#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || ((WIDE) == SDIO_BusWide_8b)) N N/** N * @} N */ N N/** @defgroup SDIO_Hardware_Flow_Control N * @{ N */ N N#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) N#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) N#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ N ((CONTROL) == SDIO_HardwareFlowControl_Enable)) X#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || ((CONTROL) == SDIO_HardwareFlowControl_Enable)) N/** N * @} N */ N N/** @defgroup SDIO_Power_State N * @{ N */ N N#define SDIO_PowerState_OFF ((uint32_t)0x00000000) N#define SDIO_PowerState_ON ((uint32_t)0x00000003) N#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) N/** N * @} N */ N N N/** @defgroup SDIO_Interrupt_sources N * @{ N */ N N#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) N#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) N#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) N#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) N#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) N#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) N#define SDIO_IT_CMDREND ((uint32_t)0x00000040) N#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) N#define SDIO_IT_DATAEND ((uint32_t)0x00000100) N#define SDIO_IT_STBITERR ((uint32_t)0x00000200) N#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) N#define SDIO_IT_CMDACT ((uint32_t)0x00000800) N#define SDIO_IT_TXACT ((uint32_t)0x00001000) N#define SDIO_IT_RXACT ((uint32_t)0x00002000) N#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) N#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) N#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) N#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) N#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) N#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) N#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) N#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) N#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) N#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) N#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) N/** N * @} N */ N N/** @defgroup SDIO_Command_Index N * @{ N */ N N#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) N/** N * @} N */ N N/** @defgroup SDIO_Response_Type N * @{ N */ N N#define SDIO_Response_No ((uint32_t)0x00000000) N#define SDIO_Response_Short ((uint32_t)0x00000040) N#define SDIO_Response_Long ((uint32_t)0x000000C0) N#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ N ((RESPONSE) == SDIO_Response_Short) || \ N ((RESPONSE) == SDIO_Response_Long)) X#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || ((RESPONSE) == SDIO_Response_Short) || ((RESPONSE) == SDIO_Response_Long)) N/** N * @} N */ N N/** @defgroup SDIO_Wait_Interrupt_State N * @{ N */ N N#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ N#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ N#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ N#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ N ((WAIT) == SDIO_Wait_Pend)) X#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || ((WAIT) == SDIO_Wait_Pend)) N/** N * @} N */ N N/** @defgroup SDIO_CPSM_State N * @{ N */ N N#define SDIO_CPSM_Disable ((uint32_t)0x00000000) N#define SDIO_CPSM_Enable ((uint32_t)0x00000400) N#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) N/** N * @} N */ N N/** @defgroup SDIO_Response_Registers N * @{ N */ N N#define SDIO_RESP1 ((uint32_t)0x00000000) N#define SDIO_RESP2 ((uint32_t)0x00000004) N#define SDIO_RESP3 ((uint32_t)0x00000008) N#define SDIO_RESP4 ((uint32_t)0x0000000C) N#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ N ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) X#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) N/** N * @} N */ N N/** @defgroup SDIO_Data_Length N * @{ N */ N N#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) N/** N * @} N */ N N/** @defgroup SDIO_Data_Block_Size N * @{ N */ N N#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) N#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) N#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) N#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) N#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) N#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) N#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) N#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) N#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) N#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) N#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) N#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) N#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) N#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) N#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) N#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ N ((SIZE) == SDIO_DataBlockSize_2b) || \ N ((SIZE) == SDIO_DataBlockSize_4b) || \ N ((SIZE) == SDIO_DataBlockSize_8b) || \ N ((SIZE) == SDIO_DataBlockSize_16b) || \ N ((SIZE) == SDIO_DataBlockSize_32b) || \ N ((SIZE) == SDIO_DataBlockSize_64b) || \ N ((SIZE) == SDIO_DataBlockSize_128b) || \ N ((SIZE) == SDIO_DataBlockSize_256b) || \ N ((SIZE) == SDIO_DataBlockSize_512b) || \ N ((SIZE) == SDIO_DataBlockSize_1024b) || \ N ((SIZE) == SDIO_DataBlockSize_2048b) || \ N ((SIZE) == SDIO_DataBlockSize_4096b) || \ N ((SIZE) == SDIO_DataBlockSize_8192b) || \ N ((SIZE) == SDIO_DataBlockSize_16384b)) X#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || ((SIZE) == SDIO_DataBlockSize_2b) || ((SIZE) == SDIO_DataBlockSize_4b) || ((SIZE) == SDIO_DataBlockSize_8b) || ((SIZE) == SDIO_DataBlockSize_16b) || ((SIZE) == SDIO_DataBlockSize_32b) || ((SIZE) == SDIO_DataBlockSize_64b) || ((SIZE) == SDIO_DataBlockSize_128b) || ((SIZE) == SDIO_DataBlockSize_256b) || ((SIZE) == SDIO_DataBlockSize_512b) || ((SIZE) == SDIO_DataBlockSize_1024b) || ((SIZE) == SDIO_DataBlockSize_2048b) || ((SIZE) == SDIO_DataBlockSize_4096b) || ((SIZE) == SDIO_DataBlockSize_8192b) || ((SIZE) == SDIO_DataBlockSize_16384b)) N/** N * @} N */ N N/** @defgroup SDIO_Transfer_Direction N * @{ N */ N N#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) N#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) N#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ N ((DIR) == SDIO_TransferDir_ToSDIO)) X#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || ((DIR) == SDIO_TransferDir_ToSDIO)) N/** N * @} N */ N N/** @defgroup SDIO_Transfer_Type N * @{ N */ N N#define SDIO_TransferMode_Block ((uint32_t)0x00000000) N#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) N#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ N ((MODE) == SDIO_TransferMode_Block)) X#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || ((MODE) == SDIO_TransferMode_Block)) N/** N * @} N */ N N/** @defgroup SDIO_DPSM_State N * @{ N */ N N#define SDIO_DPSM_Disable ((uint32_t)0x00000000) N#define SDIO_DPSM_Enable ((uint32_t)0x00000001) N#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) N/** N * @} N */ N N/** @defgroup SDIO_Flags N * @{ N */ N N#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) N#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) N#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) N#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) N#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) N#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) N#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) N#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) N#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) N#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) N#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) N#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) N#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) N#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) N#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) N#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) N#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) N#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) N#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) N#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) N#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) N#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) N#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) N#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) N#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ N ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ N ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ N ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ N ((FLAG) == SDIO_FLAG_TXUNDERR) || \ N ((FLAG) == SDIO_FLAG_RXOVERR) || \ N ((FLAG) == SDIO_FLAG_CMDREND) || \ N ((FLAG) == SDIO_FLAG_CMDSENT) || \ N ((FLAG) == SDIO_FLAG_DATAEND) || \ N ((FLAG) == SDIO_FLAG_STBITERR) || \ N ((FLAG) == SDIO_FLAG_DBCKEND) || \ N ((FLAG) == SDIO_FLAG_CMDACT) || \ N ((FLAG) == SDIO_FLAG_TXACT) || \ N ((FLAG) == SDIO_FLAG_RXACT) || \ N ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ N ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ N ((FLAG) == SDIO_FLAG_TXFIFOF) || \ N ((FLAG) == SDIO_FLAG_RXFIFOF) || \ N ((FLAG) == SDIO_FLAG_TXFIFOE) || \ N ((FLAG) == SDIO_FLAG_RXFIFOE) || \ N ((FLAG) == SDIO_FLAG_TXDAVL) || \ N ((FLAG) == SDIO_FLAG_RXDAVL) || \ N ((FLAG) == SDIO_FLAG_SDIOIT) || \ N ((FLAG) == SDIO_FLAG_CEATAEND)) X#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || ((FLAG) == SDIO_FLAG_DCRCFAIL) || ((FLAG) == SDIO_FLAG_CTIMEOUT) || ((FLAG) == SDIO_FLAG_DTIMEOUT) || ((FLAG) == SDIO_FLAG_TXUNDERR) || ((FLAG) == SDIO_FLAG_RXOVERR) || ((FLAG) == SDIO_FLAG_CMDREND) || ((FLAG) == SDIO_FLAG_CMDSENT) || ((FLAG) == SDIO_FLAG_DATAEND) || ((FLAG) == SDIO_FLAG_STBITERR) || ((FLAG) == SDIO_FLAG_DBCKEND) || ((FLAG) == SDIO_FLAG_CMDACT) || ((FLAG) == SDIO_FLAG_TXACT) || ((FLAG) == SDIO_FLAG_RXACT) || ((FLAG) == SDIO_FLAG_TXFIFOHE) || ((FLAG) == SDIO_FLAG_RXFIFOHF) || ((FLAG) == SDIO_FLAG_TXFIFOF) || ((FLAG) == SDIO_FLAG_RXFIFOF) || ((FLAG) == SDIO_FLAG_TXFIFOE) || ((FLAG) == SDIO_FLAG_RXFIFOE) || ((FLAG) == SDIO_FLAG_TXDAVL) || ((FLAG) == SDIO_FLAG_RXDAVL) || ((FLAG) == SDIO_FLAG_SDIOIT) || ((FLAG) == SDIO_FLAG_CEATAEND)) N N#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) N N#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ N ((IT) == SDIO_IT_DCRCFAIL) || \ N ((IT) == SDIO_IT_CTIMEOUT) || \ N ((IT) == SDIO_IT_DTIMEOUT) || \ N ((IT) == SDIO_IT_TXUNDERR) || \ N ((IT) == SDIO_IT_RXOVERR) || \ N ((IT) == SDIO_IT_CMDREND) || \ N ((IT) == SDIO_IT_CMDSENT) || \ N ((IT) == SDIO_IT_DATAEND) || \ N ((IT) == SDIO_IT_STBITERR) || \ N ((IT) == SDIO_IT_DBCKEND) || \ N ((IT) == SDIO_IT_CMDACT) || \ N ((IT) == SDIO_IT_TXACT) || \ N ((IT) == SDIO_IT_RXACT) || \ N ((IT) == SDIO_IT_TXFIFOHE) || \ N ((IT) == SDIO_IT_RXFIFOHF) || \ N ((IT) == SDIO_IT_TXFIFOF) || \ N ((IT) == SDIO_IT_RXFIFOF) || \ N ((IT) == SDIO_IT_TXFIFOE) || \ N ((IT) == SDIO_IT_RXFIFOE) || \ N ((IT) == SDIO_IT_TXDAVL) || \ N ((IT) == SDIO_IT_RXDAVL) || \ N ((IT) == SDIO_IT_SDIOIT) || \ N ((IT) == SDIO_IT_CEATAEND)) X#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || ((IT) == SDIO_IT_DCRCFAIL) || ((IT) == SDIO_IT_CTIMEOUT) || ((IT) == SDIO_IT_DTIMEOUT) || ((IT) == SDIO_IT_TXUNDERR) || ((IT) == SDIO_IT_RXOVERR) || ((IT) == SDIO_IT_CMDREND) || ((IT) == SDIO_IT_CMDSENT) || ((IT) == SDIO_IT_DATAEND) || ((IT) == SDIO_IT_STBITERR) || ((IT) == SDIO_IT_DBCKEND) || ((IT) == SDIO_IT_CMDACT) || ((IT) == SDIO_IT_TXACT) || ((IT) == SDIO_IT_RXACT) || ((IT) == SDIO_IT_TXFIFOHE) || ((IT) == SDIO_IT_RXFIFOHF) || ((IT) == SDIO_IT_TXFIFOF) || ((IT) == SDIO_IT_RXFIFOF) || ((IT) == SDIO_IT_TXFIFOE) || ((IT) == SDIO_IT_RXFIFOE) || ((IT) == SDIO_IT_TXDAVL) || ((IT) == SDIO_IT_RXDAVL) || ((IT) == SDIO_IT_SDIOIT) || ((IT) == SDIO_IT_CEATAEND)) N N#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) N N/** N * @} N */ N N/** @defgroup SDIO_Read_Wait_Mode N * @{ N */ N N#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) N#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) N#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ N ((MODE) == SDIO_ReadWaitMode_DATA2)) X#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || ((MODE) == SDIO_ReadWaitMode_DATA2)) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup SDIO_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup SDIO_Exported_Functions N * @{ N */ N Nvoid SDIO_DeInit(void); Nvoid SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); Nvoid SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); Nvoid SDIO_ClockCmd(FunctionalState NewState); Nvoid SDIO_SetPowerState(uint32_t SDIO_PowerState); Nuint32_t SDIO_GetPowerState(void); Nvoid SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); Nvoid SDIO_DMACmd(FunctionalState NewState); Nvoid SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); Nvoid SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); Nuint8_t SDIO_GetCommandResponse(void); Nuint32_t SDIO_GetResponse(uint32_t SDIO_RESP); Nvoid SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); Nvoid SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); Nuint32_t SDIO_GetDataCounter(void); Nuint32_t SDIO_ReadData(void); Nvoid SDIO_WriteData(uint32_t Data); Nuint32_t SDIO_GetFIFOCount(void); Nvoid SDIO_StartSDIOReadWait(FunctionalState NewState); Nvoid SDIO_StopSDIOReadWait(FunctionalState NewState); Nvoid SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); Nvoid SDIO_SetSDIOOperation(FunctionalState NewState); Nvoid SDIO_SendSDIOSuspendCmd(FunctionalState NewState); Nvoid SDIO_CommandCompletionCmd(FunctionalState NewState); Nvoid SDIO_CEATAITCmd(FunctionalState NewState); Nvoid SDIO_SendCEATACmd(FunctionalState NewState); NFlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); Nvoid SDIO_ClearFlag(uint32_t SDIO_FLAG); NITStatus SDIO_GetITStatus(uint32_t SDIO_IT); Nvoid SDIO_ClearITPendingBit(uint32_t SDIO_IT); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_SDIO_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 46 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_spi.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_spi.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the SPI firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_SPI_H N#define __STM32F10x_SPI_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup SPI N * @{ N */ N N/** @defgroup SPI_Exported_Types N * @{ N */ N N/** N * @brief SPI Init structure definition N */ N Ntypedef struct N{ N uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. N This parameter can be a value of @ref SPI_data_direction */ N N uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. N This parameter can be a value of @ref SPI_mode */ N N uint16_t SPI_DataSize; /*!< Specifies the SPI data size. N This parameter can be a value of @ref SPI_data_size */ N N uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. N This parameter can be a value of @ref SPI_Clock_Polarity */ N N uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. N This parameter can be a value of @ref SPI_Clock_Phase */ N N uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by N hardware (NSS pin) or by software using the SSI bit. N This parameter can be a value of @ref SPI_Slave_Select_management */ N N uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be N used to configure the transmit and receive SCK clock. N This parameter can be a value of @ref SPI_BaudRate_Prescaler. N @note The communication clock is derived from the master N clock. The slave clock does not need to be set. */ N N uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. N This parameter can be a value of @ref SPI_MSB_LSB_transmission */ N N uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ N}SPI_InitTypeDef; N N/** N * @brief I2S Init structure definition N */ N Ntypedef struct N{ N N uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. N This parameter can be a value of @ref I2S_Mode */ N N uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. N This parameter can be a value of @ref I2S_Standard */ N N uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. N This parameter can be a value of @ref I2S_Data_Format */ N N uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. N This parameter can be a value of @ref I2S_MCLK_Output */ N N uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. N This parameter can be a value of @ref I2S_Audio_Frequency */ N N uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. N This parameter can be a value of @ref I2S_Clock_Polarity */ N}I2S_InitTypeDef; N N/** N * @} N */ N N/** @defgroup SPI_Exported_Constants N * @{ N */ N N#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ N ((PERIPH) == SPI2) || \ N ((PERIPH) == SPI3)) X#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3)) N N#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ N ((PERIPH) == SPI3)) X#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3)) N N/** @defgroup SPI_data_direction N * @{ N */ N N#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) N#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) N#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) N#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) N#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ N ((MODE) == SPI_Direction_2Lines_RxOnly) || \ N ((MODE) == SPI_Direction_1Line_Rx) || \ N ((MODE) == SPI_Direction_1Line_Tx)) X#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || ((MODE) == SPI_Direction_2Lines_RxOnly) || ((MODE) == SPI_Direction_1Line_Rx) || ((MODE) == SPI_Direction_1Line_Tx)) N/** N * @} N */ N N/** @defgroup SPI_mode N * @{ N */ N N#define SPI_Mode_Master ((uint16_t)0x0104) N#define SPI_Mode_Slave ((uint16_t)0x0000) N#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ N ((MODE) == SPI_Mode_Slave)) X#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || ((MODE) == SPI_Mode_Slave)) N/** N * @} N */ N N/** @defgroup SPI_data_size N * @{ N */ N N#define SPI_DataSize_16b ((uint16_t)0x0800) N#define SPI_DataSize_8b ((uint16_t)0x0000) N#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ N ((DATASIZE) == SPI_DataSize_8b)) X#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || ((DATASIZE) == SPI_DataSize_8b)) N/** N * @} N */ N N/** @defgroup SPI_Clock_Polarity N * @{ N */ N N#define SPI_CPOL_Low ((uint16_t)0x0000) N#define SPI_CPOL_High ((uint16_t)0x0002) N#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ N ((CPOL) == SPI_CPOL_High)) X#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || ((CPOL) == SPI_CPOL_High)) N/** N * @} N */ N N/** @defgroup SPI_Clock_Phase N * @{ N */ N N#define SPI_CPHA_1Edge ((uint16_t)0x0000) N#define SPI_CPHA_2Edge ((uint16_t)0x0001) N#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ N ((CPHA) == SPI_CPHA_2Edge)) X#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || ((CPHA) == SPI_CPHA_2Edge)) N/** N * @} N */ N N/** @defgroup SPI_Slave_Select_management N * @{ N */ N N#define SPI_NSS_Soft ((uint16_t)0x0200) N#define SPI_NSS_Hard ((uint16_t)0x0000) N#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ N ((NSS) == SPI_NSS_Hard)) X#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || ((NSS) == SPI_NSS_Hard)) N/** N * @} N */ N N/** @defgroup SPI_BaudRate_Prescaler N * @{ N */ N N#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) N#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) N#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) N#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) N#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) N#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) N#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) N#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) N#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ N ((PRESCALER) == SPI_BaudRatePrescaler_256)) X#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || ((PRESCALER) == SPI_BaudRatePrescaler_4) || ((PRESCALER) == SPI_BaudRatePrescaler_8) || ((PRESCALER) == SPI_BaudRatePrescaler_16) || ((PRESCALER) == SPI_BaudRatePrescaler_32) || ((PRESCALER) == SPI_BaudRatePrescaler_64) || ((PRESCALER) == SPI_BaudRatePrescaler_128) || ((PRESCALER) == SPI_BaudRatePrescaler_256)) N/** N * @} N */ N N/** @defgroup SPI_MSB_LSB_transmission N * @{ N */ N N#define SPI_FirstBit_MSB ((uint16_t)0x0000) N#define SPI_FirstBit_LSB ((uint16_t)0x0080) N#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ N ((BIT) == SPI_FirstBit_LSB)) X#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || ((BIT) == SPI_FirstBit_LSB)) N/** N * @} N */ N N/** @defgroup I2S_Mode N * @{ N */ N N#define I2S_Mode_SlaveTx ((uint16_t)0x0000) N#define I2S_Mode_SlaveRx ((uint16_t)0x0100) N#define I2S_Mode_MasterTx ((uint16_t)0x0200) N#define I2S_Mode_MasterRx ((uint16_t)0x0300) N#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ N ((MODE) == I2S_Mode_SlaveRx) || \ N ((MODE) == I2S_Mode_MasterTx) || \ N ((MODE) == I2S_Mode_MasterRx) ) X#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || ((MODE) == I2S_Mode_SlaveRx) || ((MODE) == I2S_Mode_MasterTx) || ((MODE) == I2S_Mode_MasterRx) ) N/** N * @} N */ N N/** @defgroup I2S_Standard N * @{ N */ N N#define I2S_Standard_Phillips ((uint16_t)0x0000) N#define I2S_Standard_MSB ((uint16_t)0x0010) N#define I2S_Standard_LSB ((uint16_t)0x0020) N#define I2S_Standard_PCMShort ((uint16_t)0x0030) N#define I2S_Standard_PCMLong ((uint16_t)0x00B0) N#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ N ((STANDARD) == I2S_Standard_MSB) || \ N ((STANDARD) == I2S_Standard_LSB) || \ N ((STANDARD) == I2S_Standard_PCMShort) || \ N ((STANDARD) == I2S_Standard_PCMLong)) X#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || ((STANDARD) == I2S_Standard_MSB) || ((STANDARD) == I2S_Standard_LSB) || ((STANDARD) == I2S_Standard_PCMShort) || ((STANDARD) == I2S_Standard_PCMLong)) N/** N * @} N */ N N/** @defgroup I2S_Data_Format N * @{ N */ N N#define I2S_DataFormat_16b ((uint16_t)0x0000) N#define I2S_DataFormat_16bextended ((uint16_t)0x0001) N#define I2S_DataFormat_24b ((uint16_t)0x0003) N#define I2S_DataFormat_32b ((uint16_t)0x0005) N#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ N ((FORMAT) == I2S_DataFormat_16bextended) || \ N ((FORMAT) == I2S_DataFormat_24b) || \ N ((FORMAT) == I2S_DataFormat_32b)) X#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || ((FORMAT) == I2S_DataFormat_16bextended) || ((FORMAT) == I2S_DataFormat_24b) || ((FORMAT) == I2S_DataFormat_32b)) N/** N * @} N */ N N/** @defgroup I2S_MCLK_Output N * @{ N */ N N#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) N#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) N#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ N ((OUTPUT) == I2S_MCLKOutput_Disable)) X#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || ((OUTPUT) == I2S_MCLKOutput_Disable)) N/** N * @} N */ N N/** @defgroup I2S_Audio_Frequency N * @{ N */ N N#define I2S_AudioFreq_192k ((uint32_t)192000) N#define I2S_AudioFreq_96k ((uint32_t)96000) N#define I2S_AudioFreq_48k ((uint32_t)48000) N#define I2S_AudioFreq_44k ((uint32_t)44100) N#define I2S_AudioFreq_32k ((uint32_t)32000) N#define I2S_AudioFreq_22k ((uint32_t)22050) N#define I2S_AudioFreq_16k ((uint32_t)16000) N#define I2S_AudioFreq_11k ((uint32_t)11025) N#define I2S_AudioFreq_8k ((uint32_t)8000) N#define I2S_AudioFreq_Default ((uint32_t)2) N N#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ N ((FREQ) <= I2S_AudioFreq_192k)) || \ N ((FREQ) == I2S_AudioFreq_Default)) X#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || ((FREQ) == I2S_AudioFreq_Default)) N/** N * @} N */ N N/** @defgroup I2S_Clock_Polarity N * @{ N */ N N#define I2S_CPOL_Low ((uint16_t)0x0000) N#define I2S_CPOL_High ((uint16_t)0x0008) N#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ N ((CPOL) == I2S_CPOL_High)) X#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || ((CPOL) == I2S_CPOL_High)) N/** N * @} N */ N N/** @defgroup SPI_I2S_DMA_transfer_requests N * @{ N */ N N#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) N#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) N#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) N/** N * @} N */ N N/** @defgroup SPI_NSS_internal_software_management N * @{ N */ N N#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) N#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) N#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ N ((INTERNAL) == SPI_NSSInternalSoft_Reset)) X#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || ((INTERNAL) == SPI_NSSInternalSoft_Reset)) N/** N * @} N */ N N/** @defgroup SPI_CRC_Transmit_Receive N * @{ N */ N N#define SPI_CRC_Tx ((uint8_t)0x00) N#define SPI_CRC_Rx ((uint8_t)0x01) N#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) N/** N * @} N */ N N/** @defgroup SPI_direction_transmit_receive N * @{ N */ N N#define SPI_Direction_Rx ((uint16_t)0xBFFF) N#define SPI_Direction_Tx ((uint16_t)0x4000) N#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ N ((DIRECTION) == SPI_Direction_Tx)) X#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || ((DIRECTION) == SPI_Direction_Tx)) N/** N * @} N */ N N/** @defgroup SPI_I2S_interrupts_definition N * @{ N */ N N#define SPI_I2S_IT_TXE ((uint8_t)0x71) N#define SPI_I2S_IT_RXNE ((uint8_t)0x60) N#define SPI_I2S_IT_ERR ((uint8_t)0x50) N#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ N ((IT) == SPI_I2S_IT_RXNE) || \ N ((IT) == SPI_I2S_IT_ERR)) X#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || ((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_ERR)) N#define SPI_I2S_IT_OVR ((uint8_t)0x56) N#define SPI_IT_MODF ((uint8_t)0x55) N#define SPI_IT_CRCERR ((uint8_t)0x54) N#define I2S_IT_UDR ((uint8_t)0x53) N#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) N#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ N ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ N ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) X#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) N/** N * @} N */ N N/** @defgroup SPI_I2S_flags_definition N * @{ N */ N N#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) N#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) N#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) N#define I2S_FLAG_UDR ((uint16_t)0x0008) N#define SPI_FLAG_CRCERR ((uint16_t)0x0010) N#define SPI_FLAG_MODF ((uint16_t)0x0020) N#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) N#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) N#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) N#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ N ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ N ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ N ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) X#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) N/** N * @} N */ N N/** @defgroup SPI_CRC_polynomial N * @{ N */ N N#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup SPI_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup SPI_Exported_Functions N * @{ N */ N Nvoid SPI_I2S_DeInit(SPI_TypeDef* SPIx); Nvoid SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); Nvoid I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); Nvoid SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); Nvoid I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); Nvoid SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); Nvoid I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); Nvoid SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); Nvoid SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); Nvoid SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); Nuint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); Nvoid SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); Nvoid SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); Nvoid SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); Nvoid SPI_TransmitCRC(SPI_TypeDef* SPIx); Nvoid SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); Nuint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); Nuint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); Nvoid SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); NFlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); Nvoid SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); NITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); Nvoid SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_SPI_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 47 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_tim.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_tim.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the TIM firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_TIM_H N#define __STM32F10x_TIM_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup TIM N * @{ N */ N N/** @defgroup TIM_Exported_Types N * @{ N */ N N/** N * @brief TIM Time Base Init structure definition N * @note This structure is used with all TIMx except for TIM6 and TIM7. N */ N Ntypedef struct N{ N uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. N This parameter can be a number between 0x0000 and 0xFFFF */ N N uint16_t TIM_CounterMode; /*!< Specifies the counter mode. N This parameter can be a value of @ref TIM_Counter_Mode */ N N uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active N Auto-Reload Register at the next update event. N This parameter must be a number between 0x0000 and 0xFFFF. */ N N uint16_t TIM_ClockDivision; /*!< Specifies the clock division. N This parameter can be a value of @ref TIM_Clock_Division_CKD */ N N uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter N reaches zero, an update event is generated and counting restarts N from the RCR value (N). N This means in PWM mode that (N+1) corresponds to: N - the number of PWM periods in edge-aligned mode N - the number of half PWM period in center-aligned mode N This parameter must be a number between 0x00 and 0xFF. N @note This parameter is valid only for TIM1 and TIM8. */ N} TIM_TimeBaseInitTypeDef; N N/** N * @brief TIM Output Compare Init structure definition N */ N Ntypedef struct N{ N uint16_t TIM_OCMode; /*!< Specifies the TIM mode. N This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ N N uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. N This parameter can be a value of @ref TIM_Output_Compare_state */ N N uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. N This parameter can be a value of @ref TIM_Output_Compare_N_state N @note This parameter is valid only for TIM1 and TIM8. */ N N uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. N This parameter can be a number between 0x0000 and 0xFFFF */ N N uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. N This parameter can be a value of @ref TIM_Output_Compare_Polarity */ N N uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. N This parameter can be a value of @ref TIM_Output_Compare_N_Polarity N @note This parameter is valid only for TIM1 and TIM8. */ N N uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. N This parameter can be a value of @ref TIM_Output_Compare_Idle_State N @note This parameter is valid only for TIM1 and TIM8. */ N N uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. N This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State N @note This parameter is valid only for TIM1 and TIM8. */ N} TIM_OCInitTypeDef; N N/** N * @brief TIM Input Capture Init structure definition N */ N Ntypedef struct N{ N N uint16_t TIM_Channel; /*!< Specifies the TIM channel. N This parameter can be a value of @ref TIM_Channel */ N N uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. N This parameter can be a value of @ref TIM_Input_Capture_Polarity */ N N uint16_t TIM_ICSelection; /*!< Specifies the input. N This parameter can be a value of @ref TIM_Input_Capture_Selection */ N N uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. N This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ N N uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. N This parameter can be a number between 0x0 and 0xF */ N} TIM_ICInitTypeDef; N N/** N * @brief BDTR structure definition N * @note This structure is used only with TIM1 and TIM8. N */ N Ntypedef struct N{ N N uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. N This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ N N uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. N This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ N N uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. N This parameter can be a value of @ref Lock_level */ N N uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the N switching-on of the outputs. N This parameter can be a number between 0x00 and 0xFF */ N N uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. N This parameter can be a value of @ref Break_Input_enable_disable */ N N uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. N This parameter can be a value of @ref Break_Polarity */ N N uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. N This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ N} TIM_BDTRInitTypeDef; N N/** @defgroup TIM_Exported_constants N * @{ N */ N N#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM6) || \ N ((PERIPH) == TIM7) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM9) || \ N ((PERIPH) == TIM10)|| \ N ((PERIPH) == TIM11)|| \ N ((PERIPH) == TIM12)|| \ N ((PERIPH) == TIM13)|| \ N ((PERIPH) == TIM14)|| \ N ((PERIPH) == TIM15)|| \ N ((PERIPH) == TIM16)|| \ N ((PERIPH) == TIM17)) X#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM10)|| ((PERIPH) == TIM11)|| ((PERIPH) == TIM12)|| ((PERIPH) == TIM13)|| ((PERIPH) == TIM14)|| ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) N N/* LIST1: TIM 1 and 8 */ N#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM8)) X#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) N N/* LIST2: TIM 1, 8, 15 16 and 17 */ N#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM15)|| \ N ((PERIPH) == TIM16)|| \ N ((PERIPH) == TIM17)) X#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) N N/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ N#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM8)) X#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8)) N N/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ N#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM15)|| \ N ((PERIPH) == TIM16)|| \ N ((PERIPH) == TIM17)) X#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) N N/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ N#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM15)) X#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)) N N/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ N#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM9) || \ N ((PERIPH) == TIM12)|| \ N ((PERIPH) == TIM15)) X#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM12)|| ((PERIPH) == TIM15)) N N/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ N#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM6) || \ N ((PERIPH) == TIM7) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM9) || \ N ((PERIPH) == TIM12)|| \ N ((PERIPH) == TIM15)) X#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM12)|| ((PERIPH) == TIM15)) N N/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ N#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM9) || \ N ((PERIPH) == TIM10)|| \ N ((PERIPH) == TIM11)|| \ N ((PERIPH) == TIM12)|| \ N ((PERIPH) == TIM13)|| \ N ((PERIPH) == TIM14)|| \ N ((PERIPH) == TIM15)|| \ N ((PERIPH) == TIM16)|| \ N ((PERIPH) == TIM17)) X#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM10)|| ((PERIPH) == TIM11)|| ((PERIPH) == TIM12)|| ((PERIPH) == TIM13)|| ((PERIPH) == TIM14)|| ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) N N/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ N#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ N ((PERIPH) == TIM2) || \ N ((PERIPH) == TIM3) || \ N ((PERIPH) == TIM4) || \ N ((PERIPH) == TIM5) || \ N ((PERIPH) == TIM6) || \ N ((PERIPH) == TIM7) || \ N ((PERIPH) == TIM8) || \ N ((PERIPH) == TIM15)|| \ N ((PERIPH) == TIM16)|| \ N ((PERIPH) == TIM17)) X#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) N N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_and_PWM_modes N * @{ N */ N N#define TIM_OCMode_Timing ((uint16_t)0x0000) N#define TIM_OCMode_Active ((uint16_t)0x0010) N#define TIM_OCMode_Inactive ((uint16_t)0x0020) N#define TIM_OCMode_Toggle ((uint16_t)0x0030) N#define TIM_OCMode_PWM1 ((uint16_t)0x0060) N#define TIM_OCMode_PWM2 ((uint16_t)0x0070) N#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ N ((MODE) == TIM_OCMode_Active) || \ N ((MODE) == TIM_OCMode_Inactive) || \ N ((MODE) == TIM_OCMode_Toggle)|| \ N ((MODE) == TIM_OCMode_PWM1) || \ N ((MODE) == TIM_OCMode_PWM2)) X#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2)) N#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ N ((MODE) == TIM_OCMode_Active) || \ N ((MODE) == TIM_OCMode_Inactive) || \ N ((MODE) == TIM_OCMode_Toggle)|| \ N ((MODE) == TIM_OCMode_PWM1) || \ N ((MODE) == TIM_OCMode_PWM2) || \ N ((MODE) == TIM_ForcedAction_Active) || \ N ((MODE) == TIM_ForcedAction_InActive)) X#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2) || ((MODE) == TIM_ForcedAction_Active) || ((MODE) == TIM_ForcedAction_InActive)) N/** N * @} N */ N N/** @defgroup TIM_One_Pulse_Mode N * @{ N */ N N#define TIM_OPMode_Single ((uint16_t)0x0008) N#define TIM_OPMode_Repetitive ((uint16_t)0x0000) N#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ N ((MODE) == TIM_OPMode_Repetitive)) X#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || ((MODE) == TIM_OPMode_Repetitive)) N/** N * @} N */ N N/** @defgroup TIM_Channel N * @{ N */ N N#define TIM_Channel_1 ((uint16_t)0x0000) N#define TIM_Channel_2 ((uint16_t)0x0004) N#define TIM_Channel_3 ((uint16_t)0x0008) N#define TIM_Channel_4 ((uint16_t)0x000C) N#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ N ((CHANNEL) == TIM_Channel_2) || \ N ((CHANNEL) == TIM_Channel_3) || \ N ((CHANNEL) == TIM_Channel_4)) X#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3) || ((CHANNEL) == TIM_Channel_4)) N#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ N ((CHANNEL) == TIM_Channel_2)) X#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2)) N#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ N ((CHANNEL) == TIM_Channel_2) || \ N ((CHANNEL) == TIM_Channel_3)) X#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3)) N/** N * @} N */ N N/** @defgroup TIM_Clock_Division_CKD N * @{ N */ N N#define TIM_CKD_DIV1 ((uint16_t)0x0000) N#define TIM_CKD_DIV2 ((uint16_t)0x0100) N#define TIM_CKD_DIV4 ((uint16_t)0x0200) N#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ N ((DIV) == TIM_CKD_DIV2) || \ N ((DIV) == TIM_CKD_DIV4)) X#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || ((DIV) == TIM_CKD_DIV2) || ((DIV) == TIM_CKD_DIV4)) N/** N * @} N */ N N/** @defgroup TIM_Counter_Mode N * @{ N */ N N#define TIM_CounterMode_Up ((uint16_t)0x0000) N#define TIM_CounterMode_Down ((uint16_t)0x0010) N#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) N#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) N#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) N#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ N ((MODE) == TIM_CounterMode_Down) || \ N ((MODE) == TIM_CounterMode_CenterAligned1) || \ N ((MODE) == TIM_CounterMode_CenterAligned2) || \ N ((MODE) == TIM_CounterMode_CenterAligned3)) X#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || ((MODE) == TIM_CounterMode_Down) || ((MODE) == TIM_CounterMode_CenterAligned1) || ((MODE) == TIM_CounterMode_CenterAligned2) || ((MODE) == TIM_CounterMode_CenterAligned3)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_Polarity N * @{ N */ N N#define TIM_OCPolarity_High ((uint16_t)0x0000) N#define TIM_OCPolarity_Low ((uint16_t)0x0002) N#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ N ((POLARITY) == TIM_OCPolarity_Low)) X#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || ((POLARITY) == TIM_OCPolarity_Low)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_N_Polarity N * @{ N */ N N#define TIM_OCNPolarity_High ((uint16_t)0x0000) N#define TIM_OCNPolarity_Low ((uint16_t)0x0008) N#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ N ((POLARITY) == TIM_OCNPolarity_Low)) X#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || ((POLARITY) == TIM_OCNPolarity_Low)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_state N * @{ N */ N N#define TIM_OutputState_Disable ((uint16_t)0x0000) N#define TIM_OutputState_Enable ((uint16_t)0x0001) N#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ N ((STATE) == TIM_OutputState_Enable)) X#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || ((STATE) == TIM_OutputState_Enable)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_N_state N * @{ N */ N N#define TIM_OutputNState_Disable ((uint16_t)0x0000) N#define TIM_OutputNState_Enable ((uint16_t)0x0004) N#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ N ((STATE) == TIM_OutputNState_Enable)) X#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || ((STATE) == TIM_OutputNState_Enable)) N/** N * @} N */ N N/** @defgroup TIM_Capture_Compare_state N * @{ N */ N N#define TIM_CCx_Enable ((uint16_t)0x0001) N#define TIM_CCx_Disable ((uint16_t)0x0000) N#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ N ((CCX) == TIM_CCx_Disable)) X#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable)) N/** N * @} N */ N N/** @defgroup TIM_Capture_Compare_N_state N * @{ N */ N N#define TIM_CCxN_Enable ((uint16_t)0x0004) N#define TIM_CCxN_Disable ((uint16_t)0x0000) N#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ N ((CCXN) == TIM_CCxN_Disable)) X#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || ((CCXN) == TIM_CCxN_Disable)) N/** N * @} N */ N N/** @defgroup Break_Input_enable_disable N * @{ N */ N N#define TIM_Break_Enable ((uint16_t)0x1000) N#define TIM_Break_Disable ((uint16_t)0x0000) N#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ N ((STATE) == TIM_Break_Disable)) X#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || ((STATE) == TIM_Break_Disable)) N/** N * @} N */ N N/** @defgroup Break_Polarity N * @{ N */ N N#define TIM_BreakPolarity_Low ((uint16_t)0x0000) N#define TIM_BreakPolarity_High ((uint16_t)0x2000) N#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ N ((POLARITY) == TIM_BreakPolarity_High)) X#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || ((POLARITY) == TIM_BreakPolarity_High)) N/** N * @} N */ N N/** @defgroup TIM_AOE_Bit_Set_Reset N * @{ N */ N N#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) N#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) N#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ N ((STATE) == TIM_AutomaticOutput_Disable)) X#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || ((STATE) == TIM_AutomaticOutput_Disable)) N/** N * @} N */ N N/** @defgroup Lock_level N * @{ N */ N N#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) N#define TIM_LOCKLevel_1 ((uint16_t)0x0100) N#define TIM_LOCKLevel_2 ((uint16_t)0x0200) N#define TIM_LOCKLevel_3 ((uint16_t)0x0300) N#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ N ((LEVEL) == TIM_LOCKLevel_1) || \ N ((LEVEL) == TIM_LOCKLevel_2) || \ N ((LEVEL) == TIM_LOCKLevel_3)) X#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || ((LEVEL) == TIM_LOCKLevel_1) || ((LEVEL) == TIM_LOCKLevel_2) || ((LEVEL) == TIM_LOCKLevel_3)) N/** N * @} N */ N N/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state N * @{ N */ N N#define TIM_OSSIState_Enable ((uint16_t)0x0400) N#define TIM_OSSIState_Disable ((uint16_t)0x0000) N#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ N ((STATE) == TIM_OSSIState_Disable)) X#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || ((STATE) == TIM_OSSIState_Disable)) N/** N * @} N */ N N/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state N * @{ N */ N N#define TIM_OSSRState_Enable ((uint16_t)0x0800) N#define TIM_OSSRState_Disable ((uint16_t)0x0000) N#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ N ((STATE) == TIM_OSSRState_Disable)) X#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || ((STATE) == TIM_OSSRState_Disable)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_Idle_State N * @{ N */ N N#define TIM_OCIdleState_Set ((uint16_t)0x0100) N#define TIM_OCIdleState_Reset ((uint16_t)0x0000) N#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ N ((STATE) == TIM_OCIdleState_Reset)) X#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || ((STATE) == TIM_OCIdleState_Reset)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_N_Idle_State N * @{ N */ N N#define TIM_OCNIdleState_Set ((uint16_t)0x0200) N#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) N#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ N ((STATE) == TIM_OCNIdleState_Reset)) X#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || ((STATE) == TIM_OCNIdleState_Reset)) N/** N * @} N */ N N/** @defgroup TIM_Input_Capture_Polarity N * @{ N */ N N#define TIM_ICPolarity_Rising ((uint16_t)0x0000) N#define TIM_ICPolarity_Falling ((uint16_t)0x0002) N#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) N#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ N ((POLARITY) == TIM_ICPolarity_Falling)) X#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || ((POLARITY) == TIM_ICPolarity_Falling)) N#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ N ((POLARITY) == TIM_ICPolarity_Falling)|| \ N ((POLARITY) == TIM_ICPolarity_BothEdge)) X#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || ((POLARITY) == TIM_ICPolarity_Falling)|| ((POLARITY) == TIM_ICPolarity_BothEdge)) N/** N * @} N */ N N/** @defgroup TIM_Input_Capture_Selection N * @{ N */ N N#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be N connected to IC1, IC2, IC3 or IC4, respectively */ N#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be N connected to IC2, IC1, IC4 or IC3, respectively. */ N#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ N#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ N ((SELECTION) == TIM_ICSelection_IndirectTI) || \ N ((SELECTION) == TIM_ICSelection_TRC)) X#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || ((SELECTION) == TIM_ICSelection_IndirectTI) || ((SELECTION) == TIM_ICSelection_TRC)) N/** N * @} N */ N N/** @defgroup TIM_Input_Capture_Prescaler N * @{ N */ N N#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ N#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ N#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ N#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ N#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ N ((PRESCALER) == TIM_ICPSC_DIV2) || \ N ((PRESCALER) == TIM_ICPSC_DIV4) || \ N ((PRESCALER) == TIM_ICPSC_DIV8)) X#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || ((PRESCALER) == TIM_ICPSC_DIV2) || ((PRESCALER) == TIM_ICPSC_DIV4) || ((PRESCALER) == TIM_ICPSC_DIV8)) N/** N * @} N */ N N/** @defgroup TIM_interrupt_sources N * @{ N */ N N#define TIM_IT_Update ((uint16_t)0x0001) N#define TIM_IT_CC1 ((uint16_t)0x0002) N#define TIM_IT_CC2 ((uint16_t)0x0004) N#define TIM_IT_CC3 ((uint16_t)0x0008) N#define TIM_IT_CC4 ((uint16_t)0x0010) N#define TIM_IT_COM ((uint16_t)0x0020) N#define TIM_IT_Trigger ((uint16_t)0x0040) N#define TIM_IT_Break ((uint16_t)0x0080) N#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) N N#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ N ((IT) == TIM_IT_CC1) || \ N ((IT) == TIM_IT_CC2) || \ N ((IT) == TIM_IT_CC3) || \ N ((IT) == TIM_IT_CC4) || \ N ((IT) == TIM_IT_COM) || \ N ((IT) == TIM_IT_Trigger) || \ N ((IT) == TIM_IT_Break)) X#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || ((IT) == TIM_IT_CC1) || ((IT) == TIM_IT_CC2) || ((IT) == TIM_IT_CC3) || ((IT) == TIM_IT_CC4) || ((IT) == TIM_IT_COM) || ((IT) == TIM_IT_Trigger) || ((IT) == TIM_IT_Break)) N/** N * @} N */ N N/** @defgroup TIM_DMA_Base_address N * @{ N */ N N#define TIM_DMABase_CR1 ((uint16_t)0x0000) N#define TIM_DMABase_CR2 ((uint16_t)0x0001) N#define TIM_DMABase_SMCR ((uint16_t)0x0002) N#define TIM_DMABase_DIER ((uint16_t)0x0003) N#define TIM_DMABase_SR ((uint16_t)0x0004) N#define TIM_DMABase_EGR ((uint16_t)0x0005) N#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) N#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) N#define TIM_DMABase_CCER ((uint16_t)0x0008) N#define TIM_DMABase_CNT ((uint16_t)0x0009) N#define TIM_DMABase_PSC ((uint16_t)0x000A) N#define TIM_DMABase_ARR ((uint16_t)0x000B) N#define TIM_DMABase_RCR ((uint16_t)0x000C) N#define TIM_DMABase_CCR1 ((uint16_t)0x000D) N#define TIM_DMABase_CCR2 ((uint16_t)0x000E) N#define TIM_DMABase_CCR3 ((uint16_t)0x000F) N#define TIM_DMABase_CCR4 ((uint16_t)0x0010) N#define TIM_DMABase_BDTR ((uint16_t)0x0011) N#define TIM_DMABase_DCR ((uint16_t)0x0012) N#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ N ((BASE) == TIM_DMABase_CR2) || \ N ((BASE) == TIM_DMABase_SMCR) || \ N ((BASE) == TIM_DMABase_DIER) || \ N ((BASE) == TIM_DMABase_SR) || \ N ((BASE) == TIM_DMABase_EGR) || \ N ((BASE) == TIM_DMABase_CCMR1) || \ N ((BASE) == TIM_DMABase_CCMR2) || \ N ((BASE) == TIM_DMABase_CCER) || \ N ((BASE) == TIM_DMABase_CNT) || \ N ((BASE) == TIM_DMABase_PSC) || \ N ((BASE) == TIM_DMABase_ARR) || \ N ((BASE) == TIM_DMABase_RCR) || \ N ((BASE) == TIM_DMABase_CCR1) || \ N ((BASE) == TIM_DMABase_CCR2) || \ N ((BASE) == TIM_DMABase_CCR3) || \ N ((BASE) == TIM_DMABase_CCR4) || \ N ((BASE) == TIM_DMABase_BDTR) || \ N ((BASE) == TIM_DMABase_DCR)) X#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || ((BASE) == TIM_DMABase_CR2) || ((BASE) == TIM_DMABase_SMCR) || ((BASE) == TIM_DMABase_DIER) || ((BASE) == TIM_DMABase_SR) || ((BASE) == TIM_DMABase_EGR) || ((BASE) == TIM_DMABase_CCMR1) || ((BASE) == TIM_DMABase_CCMR2) || ((BASE) == TIM_DMABase_CCER) || ((BASE) == TIM_DMABase_CNT) || ((BASE) == TIM_DMABase_PSC) || ((BASE) == TIM_DMABase_ARR) || ((BASE) == TIM_DMABase_RCR) || ((BASE) == TIM_DMABase_CCR1) || ((BASE) == TIM_DMABase_CCR2) || ((BASE) == TIM_DMABase_CCR3) || ((BASE) == TIM_DMABase_CCR4) || ((BASE) == TIM_DMABase_BDTR) || ((BASE) == TIM_DMABase_DCR)) N/** N * @} N */ N N/** @defgroup TIM_DMA_Burst_Length N * @{ N */ N N#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) N#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) N#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) N#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) N#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) N#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) N#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) N#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) N#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) N#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) N#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) N#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) N#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) N#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) N#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) N#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) N#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) N#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) N#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ N ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ N ((LENGTH) == TIM_DMABurstLength_18Transfers)) X#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || ((LENGTH) == TIM_DMABurstLength_2Transfers) || ((LENGTH) == TIM_DMABurstLength_3Transfers) || ((LENGTH) == TIM_DMABurstLength_4Transfers) || ((LENGTH) == TIM_DMABurstLength_5Transfers) || ((LENGTH) == TIM_DMABurstLength_6Transfers) || ((LENGTH) == TIM_DMABurstLength_7Transfers) || ((LENGTH) == TIM_DMABurstLength_8Transfers) || ((LENGTH) == TIM_DMABurstLength_9Transfers) || ((LENGTH) == TIM_DMABurstLength_10Transfers) || ((LENGTH) == TIM_DMABurstLength_11Transfers) || ((LENGTH) == TIM_DMABurstLength_12Transfers) || ((LENGTH) == TIM_DMABurstLength_13Transfers) || ((LENGTH) == TIM_DMABurstLength_14Transfers) || ((LENGTH) == TIM_DMABurstLength_15Transfers) || ((LENGTH) == TIM_DMABurstLength_16Transfers) || ((LENGTH) == TIM_DMABurstLength_17Transfers) || ((LENGTH) == TIM_DMABurstLength_18Transfers)) N/** N * @} N */ N N/** @defgroup TIM_DMA_sources N * @{ N */ N N#define TIM_DMA_Update ((uint16_t)0x0100) N#define TIM_DMA_CC1 ((uint16_t)0x0200) N#define TIM_DMA_CC2 ((uint16_t)0x0400) N#define TIM_DMA_CC3 ((uint16_t)0x0800) N#define TIM_DMA_CC4 ((uint16_t)0x1000) N#define TIM_DMA_COM ((uint16_t)0x2000) N#define TIM_DMA_Trigger ((uint16_t)0x4000) N#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) N N/** N * @} N */ N N/** @defgroup TIM_External_Trigger_Prescaler N * @{ N */ N N#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) N#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) N#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) N#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) N#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ N ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ N ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ N ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) X#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) N/** N * @} N */ N N/** @defgroup TIM_Internal_Trigger_Selection N * @{ N */ N N#define TIM_TS_ITR0 ((uint16_t)0x0000) N#define TIM_TS_ITR1 ((uint16_t)0x0010) N#define TIM_TS_ITR2 ((uint16_t)0x0020) N#define TIM_TS_ITR3 ((uint16_t)0x0030) N#define TIM_TS_TI1F_ED ((uint16_t)0x0040) N#define TIM_TS_TI1FP1 ((uint16_t)0x0050) N#define TIM_TS_TI2FP2 ((uint16_t)0x0060) N#define TIM_TS_ETRF ((uint16_t)0x0070) N#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ N ((SELECTION) == TIM_TS_ITR1) || \ N ((SELECTION) == TIM_TS_ITR2) || \ N ((SELECTION) == TIM_TS_ITR3) || \ N ((SELECTION) == TIM_TS_TI1F_ED) || \ N ((SELECTION) == TIM_TS_TI1FP1) || \ N ((SELECTION) == TIM_TS_TI2FP2) || \ N ((SELECTION) == TIM_TS_ETRF)) X#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_TI1F_ED) || ((SELECTION) == TIM_TS_TI1FP1) || ((SELECTION) == TIM_TS_TI2FP2) || ((SELECTION) == TIM_TS_ETRF)) N#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ N ((SELECTION) == TIM_TS_ITR1) || \ N ((SELECTION) == TIM_TS_ITR2) || \ N ((SELECTION) == TIM_TS_ITR3)) X#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3)) N/** N * @} N */ N N/** @defgroup TIM_TIx_External_Clock_Source N * @{ N */ N N#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) N#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) N#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) N#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ N ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ N ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) X#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) N/** N * @} N */ N N/** @defgroup TIM_External_Trigger_Polarity N * @{ N */ N#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) N#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) N#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ N ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) X#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) N/** N * @} N */ N N/** @defgroup TIM_Prescaler_Reload_Mode N * @{ N */ N N#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) N#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) N#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ N ((RELOAD) == TIM_PSCReloadMode_Immediate)) X#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || ((RELOAD) == TIM_PSCReloadMode_Immediate)) N/** N * @} N */ N N/** @defgroup TIM_Forced_Action N * @{ N */ N N#define TIM_ForcedAction_Active ((uint16_t)0x0050) N#define TIM_ForcedAction_InActive ((uint16_t)0x0040) N#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ N ((ACTION) == TIM_ForcedAction_InActive)) X#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || ((ACTION) == TIM_ForcedAction_InActive)) N/** N * @} N */ N N/** @defgroup TIM_Encoder_Mode N * @{ N */ N N#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) N#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) N#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) N#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ N ((MODE) == TIM_EncoderMode_TI2) || \ N ((MODE) == TIM_EncoderMode_TI12)) X#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || ((MODE) == TIM_EncoderMode_TI2) || ((MODE) == TIM_EncoderMode_TI12)) N/** N * @} N */ N N N/** @defgroup TIM_Event_Source N * @{ N */ N N#define TIM_EventSource_Update ((uint16_t)0x0001) N#define TIM_EventSource_CC1 ((uint16_t)0x0002) N#define TIM_EventSource_CC2 ((uint16_t)0x0004) N#define TIM_EventSource_CC3 ((uint16_t)0x0008) N#define TIM_EventSource_CC4 ((uint16_t)0x0010) N#define TIM_EventSource_COM ((uint16_t)0x0020) N#define TIM_EventSource_Trigger ((uint16_t)0x0040) N#define TIM_EventSource_Break ((uint16_t)0x0080) N#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) N N/** N * @} N */ N N/** @defgroup TIM_Update_Source N * @{ N */ N N#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow N or the setting of UG bit, or an update generation N through the slave mode controller. */ N#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ N#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ N ((SOURCE) == TIM_UpdateSource_Regular)) X#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || ((SOURCE) == TIM_UpdateSource_Regular)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_Preload_State N * @{ N */ N N#define TIM_OCPreload_Enable ((uint16_t)0x0008) N#define TIM_OCPreload_Disable ((uint16_t)0x0000) N#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ N ((STATE) == TIM_OCPreload_Disable)) X#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || ((STATE) == TIM_OCPreload_Disable)) N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_Fast_State N * @{ N */ N N#define TIM_OCFast_Enable ((uint16_t)0x0004) N#define TIM_OCFast_Disable ((uint16_t)0x0000) N#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ N ((STATE) == TIM_OCFast_Disable)) X#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || ((STATE) == TIM_OCFast_Disable)) N N/** N * @} N */ N N/** @defgroup TIM_Output_Compare_Clear_State N * @{ N */ N N#define TIM_OCClear_Enable ((uint16_t)0x0080) N#define TIM_OCClear_Disable ((uint16_t)0x0000) N#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ N ((STATE) == TIM_OCClear_Disable)) X#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || ((STATE) == TIM_OCClear_Disable)) N/** N * @} N */ N N/** @defgroup TIM_Trigger_Output_Source N * @{ N */ N N#define TIM_TRGOSource_Reset ((uint16_t)0x0000) N#define TIM_TRGOSource_Enable ((uint16_t)0x0010) N#define TIM_TRGOSource_Update ((uint16_t)0x0020) N#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) N#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) N#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) N#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) N#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) N#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ N ((SOURCE) == TIM_TRGOSource_Enable) || \ N ((SOURCE) == TIM_TRGOSource_Update) || \ N ((SOURCE) == TIM_TRGOSource_OC1) || \ N ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ N ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ N ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ N ((SOURCE) == TIM_TRGOSource_OC4Ref)) X#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || ((SOURCE) == TIM_TRGOSource_Enable) || ((SOURCE) == TIM_TRGOSource_Update) || ((SOURCE) == TIM_TRGOSource_OC1) || ((SOURCE) == TIM_TRGOSource_OC1Ref) || ((SOURCE) == TIM_TRGOSource_OC2Ref) || ((SOURCE) == TIM_TRGOSource_OC3Ref) || ((SOURCE) == TIM_TRGOSource_OC4Ref)) N/** N * @} N */ N N/** @defgroup TIM_Slave_Mode N * @{ N */ N N#define TIM_SlaveMode_Reset ((uint16_t)0x0004) N#define TIM_SlaveMode_Gated ((uint16_t)0x0005) N#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) N#define TIM_SlaveMode_External1 ((uint16_t)0x0007) N#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ N ((MODE) == TIM_SlaveMode_Gated) || \ N ((MODE) == TIM_SlaveMode_Trigger) || \ N ((MODE) == TIM_SlaveMode_External1)) X#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || ((MODE) == TIM_SlaveMode_Gated) || ((MODE) == TIM_SlaveMode_Trigger) || ((MODE) == TIM_SlaveMode_External1)) N/** N * @} N */ N N/** @defgroup TIM_Master_Slave_Mode N * @{ N */ N N#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) N#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) N#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ N ((STATE) == TIM_MasterSlaveMode_Disable)) X#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || ((STATE) == TIM_MasterSlaveMode_Disable)) N/** N * @} N */ N N/** @defgroup TIM_Flags N * @{ N */ N N#define TIM_FLAG_Update ((uint16_t)0x0001) N#define TIM_FLAG_CC1 ((uint16_t)0x0002) N#define TIM_FLAG_CC2 ((uint16_t)0x0004) N#define TIM_FLAG_CC3 ((uint16_t)0x0008) N#define TIM_FLAG_CC4 ((uint16_t)0x0010) N#define TIM_FLAG_COM ((uint16_t)0x0020) N#define TIM_FLAG_Trigger ((uint16_t)0x0040) N#define TIM_FLAG_Break ((uint16_t)0x0080) N#define TIM_FLAG_CC1OF ((uint16_t)0x0200) N#define TIM_FLAG_CC2OF ((uint16_t)0x0400) N#define TIM_FLAG_CC3OF ((uint16_t)0x0800) N#define TIM_FLAG_CC4OF ((uint16_t)0x1000) N#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ N ((FLAG) == TIM_FLAG_CC1) || \ N ((FLAG) == TIM_FLAG_CC2) || \ N ((FLAG) == TIM_FLAG_CC3) || \ N ((FLAG) == TIM_FLAG_CC4) || \ N ((FLAG) == TIM_FLAG_COM) || \ N ((FLAG) == TIM_FLAG_Trigger) || \ N ((FLAG) == TIM_FLAG_Break) || \ N ((FLAG) == TIM_FLAG_CC1OF) || \ N ((FLAG) == TIM_FLAG_CC2OF) || \ N ((FLAG) == TIM_FLAG_CC3OF) || \ N ((FLAG) == TIM_FLAG_CC4OF)) X#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_Trigger) || ((FLAG) == TIM_FLAG_Break) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF)) N N N#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) N/** N * @} N */ N N/** @defgroup TIM_Input_Capture_Filer_Value N * @{ N */ N N#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) N/** N * @} N */ N N/** @defgroup TIM_External_Trigger_Filter N * @{ N */ N N#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) N/** N * @} N */ N N/** @defgroup TIM_Legacy N * @{ N */ N N#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer N#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers N#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers N#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers N#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers N#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers N#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers N#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers N#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers N#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers N#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers N#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers N#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers N#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers N#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers N#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers N#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers N#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup TIM_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup TIM_Exported_Functions N * @{ N */ N Nvoid TIM_DeInit(TIM_TypeDef* TIMx); Nvoid TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); Nvoid TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); Nvoid TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); Nvoid TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); Nvoid TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); Nvoid TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); Nvoid TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); Nvoid TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); Nvoid TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); Nvoid TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); Nvoid TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); Nvoid TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); Nvoid TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); Nvoid TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); Nvoid TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); Nvoid TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); Nvoid TIM_InternalClockConfig(TIM_TypeDef* TIMx); Nvoid TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); Nvoid TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, N uint16_t TIM_ICPolarity, uint16_t ICFilter); Nvoid TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, N uint16_t ExtTRGFilter); Nvoid TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, N uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); Nvoid TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, N uint16_t ExtTRGFilter); Nvoid TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); Nvoid TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); Nvoid TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); Nvoid TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, N uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); Nvoid TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); Nvoid TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); Nvoid TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); Nvoid TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); Nvoid TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); Nvoid TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); Nvoid TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); Nvoid TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); Nvoid TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); Nvoid TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); Nvoid TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); Nvoid TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); Nvoid TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); Nvoid TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); Nvoid TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); Nvoid TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); Nvoid TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); Nvoid TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); Nvoid TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); Nvoid TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); Nvoid TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); Nvoid TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); Nvoid TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); Nvoid TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); Nvoid TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); Nvoid TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); Nvoid TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); Nvoid TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); Nvoid TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); Nvoid TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); Nvoid TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); Nvoid TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); Nvoid TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); Nvoid TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); Nvoid TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); Nvoid TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); Nvoid TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); Nvoid TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); Nvoid TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); Nvoid TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); Nvoid TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); Nvoid TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); Nvoid TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); Nuint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); Nuint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); Nuint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); Nuint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); Nuint16_t TIM_GetCounter(TIM_TypeDef* TIMx); Nuint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); NFlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); Nvoid TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); NITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); Nvoid TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); N N#ifdef __cplusplus S} N#endif N N#endif /*__STM32F10x_TIM_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 48 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_usart.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_usart.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the USART N * firmware library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_USART_H N#define __STM32F10x_USART_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup USART N * @{ N */ N N/** @defgroup USART_Exported_Types N * @{ N */ N N/** N * @brief USART Init Structure definition N */ N Ntypedef struct N{ N uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. N The baud rate is computed using the following formula: N - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) N - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ N N uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. N This parameter can be a value of @ref USART_Word_Length */ N N uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. N This parameter can be a value of @ref USART_Stop_Bits */ N N uint16_t USART_Parity; /*!< Specifies the parity mode. N This parameter can be a value of @ref USART_Parity N @note When parity is enabled, the computed parity is inserted N at the MSB position of the transmitted data (9th bit when N the word length is set to 9 data bits; 8th bit when the N word length is set to 8 data bits). */ N N uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. N This parameter can be a value of @ref USART_Mode */ N N uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled N or disabled. N This parameter can be a value of @ref USART_Hardware_Flow_Control */ N} USART_InitTypeDef; N N/** N * @brief USART Clock Init Structure definition N */ N Ntypedef struct N{ N N uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. N This parameter can be a value of @ref USART_Clock */ N N uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. N This parameter can be a value of @ref USART_Clock_Polarity */ N N uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. N This parameter can be a value of @ref USART_Clock_Phase */ N N uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted N data bit (MSB) has to be output on the SCLK pin in synchronous mode. N This parameter can be a value of @ref USART_Last_Bit */ N} USART_ClockInitTypeDef; N N/** N * @} N */ N N/** @defgroup USART_Exported_Constants N * @{ N */ N N#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ N ((PERIPH) == USART2) || \ N ((PERIPH) == USART3) || \ N ((PERIPH) == UART4) || \ N ((PERIPH) == UART5)) X#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5)) N N#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ N ((PERIPH) == USART2) || \ N ((PERIPH) == USART3)) X#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3)) N N#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ N ((PERIPH) == USART2) || \ N ((PERIPH) == USART3) || \ N ((PERIPH) == UART4)) X#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4)) N/** @defgroup USART_Word_Length N * @{ N */ N N#define USART_WordLength_8b ((uint16_t)0x0000) N#define USART_WordLength_9b ((uint16_t)0x1000) N N#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ N ((LENGTH) == USART_WordLength_9b)) X#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || ((LENGTH) == USART_WordLength_9b)) N/** N * @} N */ N N/** @defgroup USART_Stop_Bits N * @{ N */ N N#define USART_StopBits_1 ((uint16_t)0x0000) N#define USART_StopBits_0_5 ((uint16_t)0x1000) N#define USART_StopBits_2 ((uint16_t)0x2000) N#define USART_StopBits_1_5 ((uint16_t)0x3000) N#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ N ((STOPBITS) == USART_StopBits_0_5) || \ N ((STOPBITS) == USART_StopBits_2) || \ N ((STOPBITS) == USART_StopBits_1_5)) X#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || ((STOPBITS) == USART_StopBits_0_5) || ((STOPBITS) == USART_StopBits_2) || ((STOPBITS) == USART_StopBits_1_5)) N/** N * @} N */ N N/** @defgroup USART_Parity N * @{ N */ N N#define USART_Parity_No ((uint16_t)0x0000) N#define USART_Parity_Even ((uint16_t)0x0400) N#define USART_Parity_Odd ((uint16_t)0x0600) N#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ N ((PARITY) == USART_Parity_Even) || \ N ((PARITY) == USART_Parity_Odd)) X#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || ((PARITY) == USART_Parity_Even) || ((PARITY) == USART_Parity_Odd)) N/** N * @} N */ N N/** @defgroup USART_Mode N * @{ N */ N N#define USART_Mode_Rx ((uint16_t)0x0004) N#define USART_Mode_Tx ((uint16_t)0x0008) N#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) N/** N * @} N */ N N/** @defgroup USART_Hardware_Flow_Control N * @{ N */ N#define USART_HardwareFlowControl_None ((uint16_t)0x0000) N#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) N#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) N#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) N#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ N (((CONTROL) == USART_HardwareFlowControl_None) || \ N ((CONTROL) == USART_HardwareFlowControl_RTS) || \ N ((CONTROL) == USART_HardwareFlowControl_CTS) || \ N ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) X#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == USART_HardwareFlowControl_None) || ((CONTROL) == USART_HardwareFlowControl_RTS) || ((CONTROL) == USART_HardwareFlowControl_CTS) || ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) N/** N * @} N */ N N/** @defgroup USART_Clock N * @{ N */ N#define USART_Clock_Disable ((uint16_t)0x0000) N#define USART_Clock_Enable ((uint16_t)0x0800) N#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ N ((CLOCK) == USART_Clock_Enable)) X#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || ((CLOCK) == USART_Clock_Enable)) N/** N * @} N */ N N/** @defgroup USART_Clock_Polarity N * @{ N */ N N#define USART_CPOL_Low ((uint16_t)0x0000) N#define USART_CPOL_High ((uint16_t)0x0400) N#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) N N/** N * @} N */ N N/** @defgroup USART_Clock_Phase N * @{ N */ N N#define USART_CPHA_1Edge ((uint16_t)0x0000) N#define USART_CPHA_2Edge ((uint16_t)0x0200) N#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) N N/** N * @} N */ N N/** @defgroup USART_Last_Bit N * @{ N */ N N#define USART_LastBit_Disable ((uint16_t)0x0000) N#define USART_LastBit_Enable ((uint16_t)0x0100) N#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ N ((LASTBIT) == USART_LastBit_Enable)) X#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || ((LASTBIT) == USART_LastBit_Enable)) N/** N * @} N */ N N/** @defgroup USART_Interrupt_definition N * @{ N */ N N#define USART_IT_PE ((uint16_t)0x0028) N#define USART_IT_TXE ((uint16_t)0x0727) N#define USART_IT_TC ((uint16_t)0x0626) N#define USART_IT_RXNE ((uint16_t)0x0525) N#define USART_IT_IDLE ((uint16_t)0x0424) N#define USART_IT_LBD ((uint16_t)0x0846) N#define USART_IT_CTS ((uint16_t)0x096A) N#define USART_IT_ERR ((uint16_t)0x0060) N#define USART_IT_ORE ((uint16_t)0x0360) N#define USART_IT_NE ((uint16_t)0x0260) N#define USART_IT_FE ((uint16_t)0x0160) N#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ N ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ N ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ N ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) X#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) N#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ N ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ N ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ N ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ N ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) X#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) N#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ N ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) X#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) N/** N * @} N */ N N/** @defgroup USART_DMA_Requests N * @{ N */ N N#define USART_DMAReq_Tx ((uint16_t)0x0080) N#define USART_DMAReq_Rx ((uint16_t)0x0040) N#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) N N/** N * @} N */ N N/** @defgroup USART_WakeUp_methods N * @{ N */ N N#define USART_WakeUp_IdleLine ((uint16_t)0x0000) N#define USART_WakeUp_AddressMark ((uint16_t)0x0800) N#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ N ((WAKEUP) == USART_WakeUp_AddressMark)) X#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || ((WAKEUP) == USART_WakeUp_AddressMark)) N/** N * @} N */ N N/** @defgroup USART_LIN_Break_Detection_Length N * @{ N */ N N#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) N#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) N#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ N (((LENGTH) == USART_LINBreakDetectLength_10b) || \ N ((LENGTH) == USART_LINBreakDetectLength_11b)) X#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBreakDetectLength_10b) || ((LENGTH) == USART_LINBreakDetectLength_11b)) N/** N * @} N */ N N/** @defgroup USART_IrDA_Low_Power N * @{ N */ N N#define USART_IrDAMode_LowPower ((uint16_t)0x0004) N#define USART_IrDAMode_Normal ((uint16_t)0x0000) N#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ N ((MODE) == USART_IrDAMode_Normal)) X#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || ((MODE) == USART_IrDAMode_Normal)) N/** N * @} N */ N N/** @defgroup USART_Flags N * @{ N */ N N#define USART_FLAG_CTS ((uint16_t)0x0200) N#define USART_FLAG_LBD ((uint16_t)0x0100) N#define USART_FLAG_TXE ((uint16_t)0x0080) N#define USART_FLAG_TC ((uint16_t)0x0040) N#define USART_FLAG_RXNE ((uint16_t)0x0020) N#define USART_FLAG_IDLE ((uint16_t)0x0010) N#define USART_FLAG_ORE ((uint16_t)0x0008) N#define USART_FLAG_NE ((uint16_t)0x0004) N#define USART_FLAG_FE ((uint16_t)0x0002) N#define USART_FLAG_PE ((uint16_t)0x0001) N#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ N ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ N ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ N ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ N ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) X#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) N N#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) N#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ N ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ N || ((USART_FLAG) != USART_FLAG_CTS)) X#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) || ((USART_FLAG) != USART_FLAG_CTS)) N#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) N#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) N#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup USART_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup USART_Exported_Functions N * @{ N */ N Nvoid USART_DeInit(USART_TypeDef* USARTx); Nvoid USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); Nvoid USART_StructInit(USART_InitTypeDef* USART_InitStruct); Nvoid USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); Nvoid USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); Nvoid USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); Nvoid USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); Nvoid USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); Nvoid USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); Nvoid USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); Nvoid USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_SendData(USART_TypeDef* USARTx, uint16_t Data); Nuint16_t USART_ReceiveData(USART_TypeDef* USARTx); Nvoid USART_SendBreak(USART_TypeDef* USARTx); Nvoid USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); Nvoid USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); Nvoid USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); Nvoid USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); Nvoid USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); NFlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); Nvoid USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); NITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); Nvoid USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_USART_H */ N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 49 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "stm32f10x_wwdg.h" L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_wwdg.h" 1 N/** N ****************************************************************************** N * @file stm32f10x_wwdg.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the WWDG firmware N * library. N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __STM32F10x_WWDG_H N#define __STM32F10x_WWDG_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup WWDG N * @{ N */ N N/** @defgroup WWDG_Exported_Types N * @{ N */ N N/** N * @} N */ N N/** @defgroup WWDG_Exported_Constants N * @{ N */ N N/** @defgroup WWDG_Prescaler N * @{ N */ N N#define WWDG_Prescaler_1 ((uint32_t)0x00000000) N#define WWDG_Prescaler_2 ((uint32_t)0x00000080) N#define WWDG_Prescaler_4 ((uint32_t)0x00000100) N#define WWDG_Prescaler_8 ((uint32_t)0x00000180) N#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ N ((PRESCALER) == WWDG_Prescaler_2) || \ N ((PRESCALER) == WWDG_Prescaler_4) || \ N ((PRESCALER) == WWDG_Prescaler_8)) X#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || ((PRESCALER) == WWDG_Prescaler_2) || ((PRESCALER) == WWDG_Prescaler_4) || ((PRESCALER) == WWDG_Prescaler_8)) N#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) N#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) N N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup WWDG_Exported_Macros N * @{ N */ N/** N * @} N */ N N/** @defgroup WWDG_Exported_Functions N * @{ N */ N Nvoid WWDG_DeInit(void); Nvoid WWDG_SetPrescaler(uint32_t WWDG_Prescaler); Nvoid WWDG_SetWindowValue(uint8_t WindowValue); Nvoid WWDG_EnableIT(void); Nvoid WWDG_SetCounter(uint8_t Counter); Nvoid WWDG_Enable(uint8_t Counter); NFlagStatus WWDG_GetFlagStatus(void); Nvoid WWDG_ClearFlag(void); N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_WWDG_H */ N N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 50 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ L 1 "..\..\template\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h" 1 N/** N ****************************************************************************** N * @file misc.h N * @author MCD Application Team N * @version V3.5.0 N * @date 11-March-2011 N * @brief This file contains all the functions prototypes for the miscellaneous N * firmware library functions (add-on to CMSIS functions). N ****************************************************************************** N * @attention N * N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. N * N *

© COPYRIGHT 2011 STMicroelectronics

N ****************************************************************************** N */ N N/* Define to prevent recursive inclusion -------------------------------------*/ N#ifndef __MISC_H N#define __MISC_H N N#ifdef __cplusplus S extern "C" { N#endif N N/* Includes ------------------------------------------------------------------*/ N#include "stm32f10x.h" N N/** @addtogroup STM32F10x_StdPeriph_Driver N * @{ N */ N N/** @addtogroup MISC N * @{ N */ N N/** @defgroup MISC_Exported_Types N * @{ N */ N N/** N * @brief NVIC Init Structure definition N */ N Ntypedef struct N{ N uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. N This parameter can be a value of @ref IRQn_Type N (For the complete STM32 Devices IRQ Channels list, please N refer to stm32f10x.h file) */ N N uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel N specified in NVIC_IRQChannel. This parameter can be a value N between 0 and 15 as described in the table @ref NVIC_Priority_Table */ N N uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified N in NVIC_IRQChannel. This parameter can be a value N between 0 and 15 as described in the table @ref NVIC_Priority_Table */ N N FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel N will be enabled or disabled. N This parameter can be set either to ENABLE or DISABLE */ N} NVIC_InitTypeDef; N N/** N * @} N */ N N/** @defgroup NVIC_Priority_Table N * @{ N */ N N/** N@code N The table below gives the allowed values of the pre-emption priority and subpriority according N to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function N ============================================================================================================================ N NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description N ============================================================================================================================ N NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority N | | | 4 bits for subpriority N ---------------------------------------------------------------------------------------------------------------------------- N NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority N | | | 3 bits for subpriority N ---------------------------------------------------------------------------------------------------------------------------- N NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority N | | | 2 bits for subpriority N ---------------------------------------------------------------------------------------------------------------------------- N NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority N | | | 1 bits for subpriority N ---------------------------------------------------------------------------------------------------------------------------- N NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority N | | | 0 bits for subpriority N ============================================================================================================================ N@endcode N*/ N N/** N * @} N */ N N/** @defgroup MISC_Exported_Constants N * @{ N */ N N/** @defgroup Vector_Table_Base N * @{ N */ N N#define NVIC_VectTab_RAM ((uint32_t)0x20000000) N#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) N#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ N ((VECTTAB) == NVIC_VectTab_FLASH)) X#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH)) N/** N * @} N */ N N/** @defgroup System_Low_Power N * @{ N */ N N#define NVIC_LP_SEVONPEND ((uint8_t)0x10) N#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) N#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) N#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ N ((LP) == NVIC_LP_SLEEPDEEP) || \ N ((LP) == NVIC_LP_SLEEPONEXIT)) X#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT)) N/** N * @} N */ N N/** @defgroup Preemption_Priority_Group N * @{ N */ N N#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority N 4 bits for subpriority */ N#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority N 3 bits for subpriority */ N#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority N 2 bits for subpriority */ N#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority N 1 bits for subpriority */ N#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority N 0 bits for subpriority */ N N#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ N ((GROUP) == NVIC_PriorityGroup_1) || \ N ((GROUP) == NVIC_PriorityGroup_2) || \ N ((GROUP) == NVIC_PriorityGroup_3) || \ N ((GROUP) == NVIC_PriorityGroup_4)) X#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4)) N N#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) N N#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) N N#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) N N/** N * @} N */ N N/** @defgroup SysTick_clock_source N * @{ N */ N N#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) N#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) N#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ N ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) X#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) N/** N * @} N */ N N/** N * @} N */ N N/** @defgroup MISC_Exported_Macros N * @{ N */ N N/** N * @} N */ N N/** @defgroup MISC_Exported_Functions N * @{ N */ N Nvoid NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); Nvoid NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); Nvoid NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); Nvoid NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); Nvoid SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); N N#ifdef __cplusplus S} N#endif N N#endif /* __MISC_H */ N N/** N * @} N */ N N/** N * @} N */ N N/** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 51 "..\..\template\Libraries\CMSIS\stm32f10x_conf.h" 2 N N/* Exported types ------------------------------------------------------------*/ N/* Exported constants --------------------------------------------------------*/ N/* Uncomment the line below to expanse the "assert_param" macro in the N Standard Peripheral Library drivers code */ N/* #define USE_FULL_ASSERT 1 */ N N/* Exported macro ------------------------------------------------------------*/ N#ifdef USE_FULL_ASSERT S S/** S * @brief The assert_param macro is used for function's parameters check. S * @param expr: If expr is false, it calls assert_failed function which reports S * the name of the source file and the source line number of the call S * that failed. If expr is true, it returns no value. S * @retval None S */ S #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) S/* Exported functions ------------------------------------------------------- */ S void assert_failed(uint8_t* file, uint32_t line); N#else N #define assert_param(expr) ((void)0) N#endif /* USE_FULL_ASSERT */ N N#endif /* __STM32F10x_CONF_H */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 8298 "..\..\template\Libraries\CMSIS\stm32f10x.h" 2 N#endif N N/** @addtogroup Exported_macro N * @{ N */ N N#define SET_BIT(REG, BIT) ((REG) |= (BIT)) N N#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) N N#define READ_BIT(REG, BIT) ((REG) & (BIT)) N N#define CLEAR_REG(REG) ((REG) = (0x0)) N N#define WRITE_REG(REG, VAL) ((REG) = (VAL)) N N#define READ_REG(REG) ((REG)) N N#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) N N/** N * @} N */ N N#ifdef __cplusplus S} N#endif N N#endif /* __STM32F10x_H */ N N/** N * @} N */ N N /** N * @} N */ N N/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ L 2 "..\user\src\swj.c" 2 N#include "stm32f10x_conf.h" N N N#include "button/iobutton.h" L 1 "..\..\nlib\button/iobutton.h" 1 N#ifndef _IOBUTTON_H_ N#define _IOBUTTON_H_ N N#include "button/iocontrol.h" L 1 "..\..\nlib\button/iocontrol.h" 1 N#ifndef _IOCONTROL_H_ N#define _IOCONTROL_H_ N Ntypedef struct N{ N //指向寄存器的输入输出io N volatile unsigned int* inputIO; N volatile unsigned int* outputIO; N N //当前io的引脚 N unsigned int validBit; N N}IOControlInfo; N N/*宏*/ N#define READIO(x) ((*(x).inputIO) & (x).validBit) N N#define SETIO(x) ((*x.outputIO) |= x.validBit) N#define RESETIO(x) ((*x.outputIO) &= (~x.validBit)) N N/**typedef**/ N#define MAXIOLEN 1 Ntypedef struct N{ N IOControlInfo* io[MAXIOLEN]; X IOControlInfo* io[1]; N unsigned int size; N}IOInfo; Nextern IOInfo allIo; N N N/*初始化io,该函数只能加入全局的io变量*/ Nextern void InitIO(IOControlInfo* io, N volatile unsigned int* input, N volatile unsigned int* output, N unsigned int validBit N ); N N#endif N N N L 5 "..\..\nlib\button/iobutton.h" 2 N#include "stdBool.h" L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdBool.h" 1 N/* stdbool.h: ISO/IEC 9899:1999 (C99), section 7.16 */ N N/* Copyright (C) ARM Ltd., 2002 N * All rights reserved N * RCS $Revision$ N * Checkin $Date$ N * Revising $Author: drodgman $ N */ N N#ifndef __bool_true_false_are_defined N#define __bool_true_false_are_defined 1 N#define __ARMCLIB_VERSION 5060037 N N #ifndef __cplusplus /* In C++, 'bool', 'true' and 'false' and keywords */ N #define bool _Bool N #define true 1 N #define false 0 N #else S #ifdef __GNUC__ S /* GNU C++ supports direct inclusion of stdbool.h to provide C99 S compatibility by defining _Bool */ S #define _Bool bool S #endif N #endif N N#endif /* __bool_true_false_are_defined */ N L 6 "..\..\nlib\button/iobutton.h" 2 N N/*用于按钮的回调函数*/ Ntypedef void(*btnFuc)(void*); N N/*按钮类型*/ Ntypedef struct N{ N IOControlInfo io; /*io控制*/ N unsigned int judgeTime; /*判断次数*/ N unsigned int timeout; /*按下超时值*/ N unsigned int ltimeout; /*按钮被长按超时值*/ N N bool press; /*是否已经按下*/ X _Bool press; N bool lpress; /*是否长按已经按下*/ X _Bool lpress; N N bool OnValid; /*设置高有效还是低有效*/ X _Bool OnValid; N N btnFuc pressFuc; /*按钮被按下函数*/ N btnFuc releaseFuc; /*按钮被抬起触发函数*/ N btnFuc lpressFuc; /*按钮被长按，触发*/ N}IoButtonType; N N/*初始化按钮*/ Nextern void FInitButton(IoButtonType* btn); N N/*判决按钮是否被按下*/ Nextern bool isPress(IoButtonType* btn); Xextern _Bool isPress(IoButtonType* btn); N N/* N*该函数是按钮类，放在定时循环周期中定期执行 N*/ Nextern void FButtonTask(IoButtonType* btn); N#endif N N L 6 "..\user\src\swj.c" 2 N#include "timer/ntimer.h" L 1 "..\..\nlib\timer/ntimer.h" 1 N#ifndef _NTIMER_H_ N#define _NTIMER_H_ N N#include "stdBool.h" N N/*******************宏****************/ N#define TIMER_COUNT_MAX 10 N N/*全局定时器，用于定时心跳*/ Nextern int globalTime; N Ntypedef enum N{ N TimeMode_period, /*周期定时器*/ N TimeMode_triggerOne, /*一次触发*/ N}TimerMode; N N/*定时器函数指针*/ Ntypedef void (*TimerFuc)(void*); N N/*定时器类型*/ Ntypedef struct N{ N int timeout; /*超时值*/ N int currenttime; /*当前定时器值*/ N TimerMode mode; /*定时器模式*/ N TimerFuc fun; /*定时器触发回调函数*/ N bool run; /*是否在运行*/ X _Bool run; N bool vaild; /*是否有效*/ X _Bool vaild; N}TimerType; N N N/*所有定时器的缓存*/ Ntypedef struct N{ N TimerType* timers; N unsigned int size; N}AllTimer; N Nextern AllTimer alltimer; N N N/*返回值：0成功，负数失败 N* 函数作用：初始化所有定时器，注意该函数会用到malloc N* 形参： N* timers：所有定时器的句柄 N* size：定义一个有几个定时器 N*/ Nextern int InitNTimer(AllTimer* timers,unsigned int size); N N N/*返回值：大于等于0成功，负数失败 N* 函数作用：开辟一个定时器 N* 形参： N* timers：所有定时器句柄 N*/ Nextern int CreatNTimer(AllTimer* timers); N N N/*返回值：负数失败，0成功 N* 函数作用：删除一个定时器 N* 形参： N* timers：所有定时器句柄 N* timer：需要删除的定时器号 N*/ Nextern int DeleteNTimer(AllTimer* timers,int timer); N N N/*返回值：0成功，负数失败 N* 函数作用：绑定定时器的回调函数 N* 形参： N* timers：所有定时器的句柄 N* timer：定时器的序号 N* timeout：定时器超时的量 N* mode：定时器的模式 N* f：回调函数 N*/ Nextern int BindNTimer(AllTimer* timers,int timer,int timeout,TimerMode mode,TimerFuc f); N N N/*返回值：无 N* 函数作用：定时运行定时器里面的逻辑 N* 形参： N* timers：所有定时器的句柄 N*/ Nextern void NTImerTask(AllTimer* timers); N N/*返回值：无 N* 函数作用：等待一段时间 N* 形参： N* time：需要等待的延时时长 N*/ Nextern void FWaitNTime(int time); N N/**********************函数接口*************************/ N/*初始化全局定时器*/ N#define FInitNTimer() InitNTimer(&alltimer,alltimer.size) N N/*创建一个新的定时器*/ N#define FCreatNTimer() CreatNTimer(&alltimer) N N/*删除一个定时器*/ N#define FDeleteNTimer(timer) DeleteNTimer(&alltimer,timer) N N/*绑定一个定时器*/ N#define FBindNTimer(timer,timeout,mode,f) BindNTimer(&alltimer,timer,timeout,mode,f) N N/*CPU定时刷新定时器*/ N#define FNTImerTask() NTImerTask(&alltimer); N N N#endif N L 7 "..\user\src\swj.c" 2 N N#include L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h" 1 N/* string.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.11 */ N/* Copyright (C) Codemist Ltd., 1988-1993. */ N/* Copyright 1991-1993 ARM Limited. All rights reserved. */ N/* version 0.04 */ N N/* N * RCS $Revision$ N * Checkin $Date$ N */ N N/* N * string.h declares one type and several functions, and defines one macro N * useful for manipulating character arrays and other objects treated as N * character arrays. Various methods are used for determining the lengths of N * the arrays, but in all cases a char * or void * argument points to the N * initial (lowest addresses) character of the array. If an array is written N * beyond the end of an object, the behaviour is undefined. N */ N N#ifndef __string_h N#define __string_h N#define __ARMCLIB_VERSION 5060037 N N#define _ARMABI __declspec(__nothrow) N N #ifndef __STRING_DECLS N #define __STRING_DECLS N N #undef __CLIBNS N N #ifdef __cplusplus S namespace std { S #define __CLIBNS std:: S extern "C" { N #else N #define __CLIBNS N #endif /* __cplusplus */ N N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) X#if 0L || !0L N /* unconditional in C++ and non-strict C for consistency of debug info */ N #if __sizeof_ptr == 8 X #if 4 == 8 S typedef unsigned long size_t; /* see */ N #else N typedef unsigned int size_t; /* see */ N #endif N#elif !defined(__size_t) S #define __size_t 1 S #if __sizeof_ptr == 8 S typedef unsigned long size_t; /* see */ S #else S typedef unsigned int size_t; /* see */ S #endif N#endif N N#undef NULL N#define NULL 0 /* see */ N Nextern _ARMABI void *memcpy(void * __restrict /*s1*/, Xextern __declspec(__nothrow) void *memcpy(void * __restrict , N const void * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); N /* N * copies n characters from the object pointed to by s2 into the object N * pointed to by s1. If copying takes place between objects that overlap, N * the behaviour is undefined. N * Returns: the value of s1. N */ Nextern _ARMABI void *memmove(void * /*s1*/, Xextern __declspec(__nothrow) void *memmove(void * , N const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); N /* N * copies n characters from the object pointed to by s2 into the object N * pointed to by s1. Copying takes place as if the n characters from the N * object pointed to by s2 are first copied into a temporary array of n N * characters that does not overlap the objects pointed to by s1 and s2, N * and then the n characters from the temporary array are copied into the N * object pointed to by s1. N * Returns: the value of s1. N */ Nextern _ARMABI char *strcpy(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); N /* N * copies the string pointed to by s2 (including the terminating nul N * character) into the array pointed to by s1. If copying takes place N * between objects that overlap, the behaviour is undefined. N * Returns: the value of s1. N */ Nextern _ARMABI char *strncpy(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); N /* N * copies not more than n characters (characters that follow a null N * character are not copied) from the array pointed to by s2 into the array N * pointed to by s1. If copying takes place between objects that overlap, N * the behaviour is undefined. N * Returns: the value of s1. N */ N Nextern _ARMABI char *strcat(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); N /* N * appends a copy of the string pointed to by s2 (including the terminating N * null character) to the end of the string pointed to by s1. The initial N * character of s2 overwrites the null character at the end of s1. N * Returns: the value of s1. N */ Nextern _ARMABI char *strncat(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); N /* N * appends not more than n characters (a null character and characters that N * follow it are not appended) from the array pointed to by s2 to the end of N * the string pointed to by s1. The initial character of s2 overwrites the N * null character at the end of s1. A terminating null character is always N * appended to the result. N * Returns: the value of s1. N */ N N/* N * The sign of a nonzero value returned by the comparison functions is N * determined by the sign of the difference between the values of the first N * pair of characters (both interpreted as unsigned char) that differ in the N * objects being compared. N */ N Nextern _ARMABI int memcmp(const void * /*s1*/, const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); N /* N * compares the first n characters of the object pointed to by s1 to the N * first n characters of the object pointed to by s2. N * Returns: an integer greater than, equal to, or less than zero, according N * as the object pointed to by s1 is greater than, equal to, or N * less than the object pointed to by s2. N */ Nextern _ARMABI int strcmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); N /* N * compares the string pointed to by s1 to the string pointed to by s2. N * Returns: an integer greater than, equal to, or less than zero, according N * as the string pointed to by s1 is greater than, equal to, or N * less than the string pointed to by s2. N */ Nextern _ARMABI int strncmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); N /* N * compares not more than n characters (characters that follow a null N * character are not compared) from the array pointed to by s1 to the array N * pointed to by s2. N * Returns: an integer greater than, equal to, or less than zero, according N * as the string pointed to by s1 is greater than, equal to, or N * less than the string pointed to by s2. N */ Nextern _ARMABI int strcasecmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); N /* N * compares the string pointed to by s1 to the string pointed to by s2, N * case-insensitively as defined by the current locale. N * Returns: an integer greater than, equal to, or less than zero, according N * as the string pointed to by s1 is greater than, equal to, or N * less than the string pointed to by s2. N */ Nextern _ARMABI int strncasecmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); N /* N * compares not more than n characters (characters that follow a null N * character are not compared) from the array pointed to by s1 to the array N * pointed to by s2, case-insensitively as defined by the current locale. N * Returns: an integer greater than, equal to, or less than zero, according N * as the string pointed to by s1 is greater than, equal to, or N * less than the string pointed to by s2. N */ Nextern _ARMABI int strcoll(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); N /* N * compares the string pointed to by s1 to the string pointed to by s2, both N * interpreted as appropriate to the LC_COLLATE category of the current N * locale. N * Returns: an integer greater than, equal to, or less than zero, according N * as the string pointed to by s1 is greater than, equal to, or N * less than the string pointed to by s2 when both are interpreted N * as appropriate to the current locale. N */ N Nextern _ARMABI size_t strxfrm(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); N /* N * transforms the string pointed to by s2 and places the resulting string N * into the array pointed to by s1. The transformation function is such that N * if the strcmp function is applied to two transformed strings, it returns N * a value greater than, equal to or less than zero, corresponding to the N * result of the strcoll function applied to the same two original strings. N * No more than n characters are placed into the resulting array pointed to N * by s1, including the terminating null character. If n is zero, s1 is N * permitted to be a null pointer. If copying takes place between objects N * that overlap, the behaviour is undefined. N * Returns: The length of the transformed string is returned (not including N * the terminating null character). If the value returned is n or N * more, the contents of the array pointed to by s1 are N * indeterminate. N */ N N N#ifdef __cplusplus Sextern _ARMABI const void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); Sextern "C++" void *memchr(void * __s, int __c, size_t __n) __attribute__((__nonnull__(1))); Sextern "C++" inline void *memchr(void * __s, int __c, size_t __n) S { return const_cast(memchr(const_cast(__s), __c, __n)); } N#else Nextern _ARMABI void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); N#endif N /* N * locates the first occurence of c (converted to an unsigned char) in the N * initial n characters (each interpreted as unsigned char) of the object N * pointed to by s. N * Returns: a pointer to the located character, or a null pointer if the N * character does not occur in the object. N */ N N#ifdef __cplusplus Sextern _ARMABI const char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); Sextern "C++" char *strchr(char * __s, int __c) __attribute__((__nonnull__(1))); Sextern "C++" inline char *strchr(char * __s, int __c) S { return const_cast(strchr(const_cast(__s), __c)); } N#else Nextern _ARMABI char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); N#endif N /* N * locates the first occurence of c (converted to an char) in the string N * pointed to by s (including the terminating null character). N * Returns: a pointer to the located character, or a null pointer if the N * character does not occur in the string. N */ N Nextern _ARMABI size_t strcspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); N /* N * computes the length of the initial segment of the string pointed to by s1 N * which consists entirely of characters not from the string pointed to by N * s2. The terminating null character is not considered part of s2. N * Returns: the length of the segment. N */ N N#ifdef __cplusplus Sextern _ARMABI const char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Sextern "C++" char *strpbrk(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); Sextern "C++" inline char *strpbrk(char * __s1, const char * __s2) S { return const_cast(strpbrk(const_cast(__s1), __s2)); } N#else Nextern _ARMABI char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); N#endif N /* N * locates the first occurence in the string pointed to by s1 of any N * character from the string pointed to by s2. N * Returns: returns a pointer to the character, or a null pointer if no N * character form s2 occurs in s1. N */ N N#ifdef __cplusplus Sextern _ARMABI const char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); Sextern "C++" char *strrchr(char * __s, int __c) __attribute__((__nonnull__(1))); Sextern "C++" inline char *strrchr(char * __s, int __c) S { return const_cast(strrchr(const_cast(__s), __c)); } N#else Nextern _ARMABI char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); N#endif N /* N * locates the last occurence of c (converted to a char) in the string N * pointed to by s. The terminating null character is considered part of N * the string. N * Returns: returns a pointer to the character, or a null pointer if c does N * not occur in the string. N */ N Nextern _ARMABI size_t strspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); N /* N * computes the length of the initial segment of the string pointed to by s1 N * which consists entirely of characters from the string pointed to by S2 N * Returns: the length of the segment. N */ N N#ifdef __cplusplus Sextern _ARMABI const char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Sextern "C++" char *strstr(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); Sextern "C++" inline char *strstr(char * __s1, const char * __s2) S { return const_cast(strstr(const_cast(__s1), __s2)); } N#else Nextern _ARMABI char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); N#endif N /* N * locates the first occurence in the string pointed to by s1 of the N * sequence of characters (excluding the terminating null character) in the N * string pointed to by s2. N * Returns: a pointer to the located string, or a null pointer if the string N * is not found. N */ N Nextern _ARMABI char *strtok(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); Nextern _ARMABI char *_strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); Xextern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); N#ifndef __STRICT_ANSI__ Nextern _ARMABI char *strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); Xextern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); N#endif N /* N * A sequence of calls to the strtok function breaks the string pointed to N * by s1 into a sequence of tokens, each of which is delimited by a N * character from the string pointed to by s2. The first call in the N * sequence has s1 as its first argument, and is followed by calls with a N * null pointer as their first argument. The separator string pointed to by N * s2 may be different from call to call. N * The first call in the sequence searches for the first character that is N * not contained in the current separator string s2. If no such character N * is found, then there are no tokens in s1 and the strtok function returns N * a null pointer. If such a character is found, it is the start of the N * first token. N * The strtok function then searches from there for a character that is N * contained in the current separator string. If no such character is found, N * the current token extends to the end of the string pointed to by s1, and N * subsequent searches for a token will fail. If such a character is found, N * it is overwritten by a null character, which terminates the current N * token. The strtok function saves a pointer to the following character, N * from which the next search for a token will start. N * Each subsequent call, with a null pointer as the value for the first N * argument, starts searching from the saved pointer and behaves as N * described above. N * Returns: pointer to the first character of a token, or a null pointer if N * there is no token. N * N * strtok_r() is a common extension which works exactly like N * strtok(), but instead of storing its state in a hidden N * library variable, requires the user to pass in a pointer to a N * char * variable which will be used instead. Any sequence of N * calls to strtok_r() passing the same char ** pointer should N * behave exactly like the corresponding sequence of calls to N * strtok(). This means that strtok_r() can safely be used in N * multi-threaded programs, and also that you can tokenise two N * strings in parallel. N */ N Nextern _ARMABI void *memset(void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); N /* N * copies the value of c (converted to an unsigned char) into each of the N * first n charactes of the object pointed to by s. N * Returns: the value of s. N */ Nextern _ARMABI char *strerror(int /*errnum*/); Xextern __declspec(__nothrow) char *strerror(int ); N /* N * maps the error number in errnum to an error message string. N * Returns: a pointer to the string, the contents of which are N * implementation-defined. The array pointed to shall not be N * modified by the program, but may be overwritten by a N * subsequent call to the strerror function. N */ Nextern _ARMABI size_t strlen(const char * /*s*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); N /* N * computes the length of the string pointed to by s. N * Returns: the number of characters that precede the terminating null N * character. N */ N Nextern _ARMABI size_t strlcpy(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); N /* N * copies the string src into the string dst, using no more than N * len bytes of dst. Always null-terminates dst _within the N * length len (i.e. will copy at most len-1 bytes of string plus N * a NUL), unless len is actually zero. N * N * Return value is the length of the string that _would_ have N * been written, i.e. the length of src. Thus, the operation N * succeeded without truncation if and only if ret < len; N * otherwise, the value in ret tells you how big to make dst if N * you decide to reallocate it. (That value does _not_ include N * the NUL.) N * N * This is a BSD-derived library extension, which we are N * permitted to declare in a standard header because ISO defines N * function names beginning with 'str' as reserved for future N * expansion of . N */ N Nextern _ARMABI size_t strlcat(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); N /* N * concatenates the string src to the string dst, using no more N * than len bytes of dst. Always null-terminates dst _within the N * length len (i.e. will copy at most len-1 bytes of string plus N * a NUL), unless len is actually zero. N * N * Return value is the length of the string that _would_ have N * been written, i.e. the length of src plus the original length N * of dst. Thus, the operation succeeded without truncation if N * and only if ret < len; otherwise, the value in ret tells you N * how big to make dst if you decide to reallocate it. (That N * value does _not_ include the NUL.) N * N * If no NUL is encountered within the first len bytes of dst, N * then the length of dst is considered to have been equal to N * len for the purposes of the return value (as if there were a N * NUL at dst[len]). Thus, the return value in this case is len N * + strlen(src). N * N * This is a BSD-derived library extension, which we are N * permitted to declare in a standard header because ISO defines N * function names beginning with 'str' as reserved for future N * expansion of . N */ N Nextern _ARMABI void _membitcpybl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitcpybb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitcpyhl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitcpyhb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitcpywl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitcpywb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitmovebl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitmovebb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitmovehl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitmovehb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitmovewl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); Nextern _ARMABI void _membitmovewb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); N /* N * Copies or moves a piece of memory from one place to another, N * with one-bit granularity. So you can start or finish a copy N * part way through a byte, and you can copy between regions N * with different alignment within a byte. N * N * All these functions have the same prototype: two void * N * pointers for destination and source, then two integers N * giving the bit offset from those pointers, and finally the N * number of bits to copy. N * N * Just like memcpy and memmove, the "cpy" functions copy as N * fast as they can in the assumption that the memory regions N * do not overlap, while the "move" functions cope correctly N * with overlap. N * N * Treating memory as a stream of individual bits requires N * defining a convention about what order those bits are N * considered to be arranged in. The above functions support N * multiple conventions: N * N * - the "bl" functions consider the unit of memory to be the N * byte, and consider the bits within each byte to be N * arranged in little-endian fashion, so that the LSB comes N * first. (For example, membitcpybl(a,b,0,7,1) would copy N * the MSB of the byte at b to the LSB of the byte at a.) N * N * - the "bb" functions consider the unit of memory to be the N * byte, and consider the bits within each byte to be N * arranged in big-endian fashion, so that the MSB comes N * first. N * N * - the "hl" functions consider the unit of memory to be the N * 16-bit halfword, and consider the bits within each word N * to be arranged in little-endian fashion. N * N * - the "hb" functions consider the unit of memory to be the N * 16-bit halfword, and consider the bits within each word N * to be arranged in big-endian fashion. N * N * - the "wl" functions consider the unit of memory to be the N * 32-bit word, and consider the bits within each word to be N * arranged in little-endian fashion. N * N * - the "wb" functions consider the unit of memory to be the N * 32-bit word, and consider the bits within each word to be N * arranged in big-endian fashion. N */ N N #ifdef __cplusplus S } /* extern "C" */ S } /* namespace std */ N #endif /* __cplusplus */ N #endif /* __STRING_DECLS */ N N #ifdef __cplusplus S #ifndef __STRING_NO_EXPORTS S using ::std::size_t; S using ::std::memcpy; S using ::std::memmove; S using ::std::strcpy; S using ::std::strncpy; S using ::std::strcat; S using ::std::strncat; S using ::std::memcmp; S using ::std::strcmp; S using ::std::strncmp; S using ::std::strcasecmp; S using ::std::strncasecmp; S using ::std::strcoll; S using ::std::strxfrm; S using ::std::memchr; S using ::std::strchr; S using ::std::strcspn; S using ::std::strpbrk; S using ::std::strrchr; S using ::std::strspn; S using ::std::strstr; S using ::std::strtok; S#ifndef __STRICT_ANSI__ S using ::std::strtok_r; S#endif S using ::std::_strtok_r; S using ::std::memset; S using ::std::strerror; S using ::std::strlen; S using ::std::strlcpy; S using ::std::strlcat; S using ::std::_membitcpybl; S using ::std::_membitcpybb; S using ::std::_membitcpyhl; S using ::std::_membitcpyhb; S using ::std::_membitcpywl; S using ::std::_membitcpywb; S using ::std::_membitmovebl; S using ::std::_membitmovebb; S using ::std::_membitmovehl; S using ::std::_membitmovehb; S using ::std::_membitmovewl; S using ::std::_membitmovewb; S #endif /* __STRING_NO_EXPORTS */ N #endif /* __cplusplus */ N N#endif N N/* end of string.h */ N L 9 "..\user\src\swj.c" 2 N#include N#include L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h" 1 N/* stdio.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.9 */ N/* Copyright (C) Codemist Ltd., 1988-1993 */ N/* Copyright 1991-1998 ARM Limited. All rights reserved. */ N N/* N * RCS $Revision$ N * Checkin $Date$ N * Revising $Author: sdouglas $ N */ N N/* N * stdio.h declares two types, several macros, and many functions for N * performing input and output. For a discussion on Streams and Files N * refer to sections 4.9.2 and 4.9.3 in the above ANSI draft, or to a N * modern textbook on C. N */ N N#ifndef __stdio_h N#define __stdio_h N#define __ARMCLIB_VERSION 5060037 N N/* N * Depending on compiler version __int64 or __INT64_TYPE__ should be defined. N */ N#ifndef __int64 N #ifdef __INT64_TYPE__ S #define __int64 __INT64_TYPE__ N #endif N /* On some architectures neither of these may be defined - if so, fall N through and error out if used. */ N#endif N N N#define _ARMABI __declspec(__nothrow) N N #ifndef __STDIO_DECLS N #define __STDIO_DECLS N N #undef __CLIBNS N #ifdef __cplusplus S namespace std { S #define __CLIBNS ::std:: S extern "C" { N #else /* ndef __cplusplus */ N #define __CLIBNS N #endif /* ndef __cplusplus */ N N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) || !defined(__size_t) X#if 0L || !0L || !0L N /* always defined in C++ and non-strict C for consistency of debug info */ N #if __sizeof_ptr == 8 X #if 4 == 8 S typedef unsigned long size_t; /* see */ N #else N typedef unsigned int size_t; /* see */ N #endif N #if !defined(__cplusplus) && defined(__STRICT_ANSI__) X #if !0L && 0L S #define __size_t 1 N #endif N#endif N N#undef NULL N#define NULL 0 /* see */ N N/* ANSI forbids va_list to be defined here */ N/* keep in step with and */ N#if !defined(__va_list) && (defined(__cplusplus) || !defined(__STRICT_ANSI__) || !defined(__va_list_defined)) X#if !0L && (0L || !0L || !0L) N/* always defined in C++ and non-strict C for consistency of debug info */ N #ifdef __clang__ S typedef __builtin_va_list __va_list; N #else N typedef struct __va_list __va_list; N #endif N #if !defined(__cplusplus) && defined(__STRICT_ANSI__) X #if !0L && 0L S #define __va_list_defined 1 N #endif N#endif N N /* N * If the compiler supports signalling nans as per N965 then it N * will define __SUPPORT_SNAN__, in which case a user may define N * _WANT_SNAN in order to obtain compliant versions of the printf N * and scanf families of functions N */ N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) X#if 0L && 0L S#pragma import(__use_snan) N#endif N Ntypedef struct __fpos_t_struct { N unsigned __int64 __pos; N /* N * this structure is equivalent to an mbstate_t, but we're not N * allowed to actually define the type name `mbstate_t' within N * stdio.h N */ N struct { N unsigned int __state1, __state2; N } __mbstate; N} fpos_t; N /* N * fpos_t is an object capable of recording all information needed to N * specify uniquely every position within a file. N */ N N#define _SYS_OPEN 16 N /* _SYS_OPEN defines a limit on the number of open files that is imposed N * by this C library N */ N Ntypedef struct __FILE FILE; N /* N * FILE is an object capable of recording all information needed to control N * a stream, such as its file position indicator, a pointer to its N * associated buffer, an error indicator that records whether a read/write N * error has occurred and an end-of-file indicator that records whether the N * end-of-file has been reached. N * Its structure is not made known to library clients. N */ N N#if defined(__STRICT_ANSI__) && !__FILE_INCOMPLETE X#if 0L && !__FILE_INCOMPLETE Sstruct __FILE { S union { S long __FILE_alignment; S#ifdef __TARGET_ARCH_AARCH64 S char __FILE_size[136]; S#else /* __TARGET_ARCH_AARCH64 */ S char __FILE_size[84]; S#endif /* __TARGET_ARCH_AARCH64 */ S } __FILE_opaque; S}; S /* S * FILE must be an object type (C99 - 7.19.1) and an object type fully S * describes an object [including its static size] (C99 - 6.2.5). S * This definition is a placeholder which matches the struct __FILE in S * size and alignment as used internally by libc. S */ N#endif N N Nextern FILE __stdin, __stdout, __stderr; Nextern FILE *__aeabi_stdin, *__aeabi_stdout, *__aeabi_stderr; N N#if _AEABI_PORTABILITY_LEVEL != 0 || (!defined _AEABI_PORTABILITY_LEVEL && __DEFAULT_AEABI_PORTABILITY_LEVEL != 0) X#if _AEABI_PORTABILITY_LEVEL != 0 || (!0L && __DEFAULT_AEABI_PORTABILITY_LEVEL != 0) S#define stdin (__CLIBNS __aeabi_stdin) S /* pointer to a FILE object associated with standard input stream */ S#define stdout (__CLIBNS __aeabi_stdout) S /* pointer to a FILE object associated with standard output stream */ S#define stderr (__CLIBNS __aeabi_stderr) S /* pointer to a FILE object associated with standard error stream */ Sextern const int __aeabi_IOFBF; S#define _IOFBF (__CLIBNS __aeabi_IOFBF) Sextern const int __aeabi_IONBF; S#define _IONBF (__CLIBNS __aeabi_IONBF) Sextern const int __aeabi_IOLBF; S#define _IOLBF (__CLIBNS __aeabi_IOLBF) Sextern const int __aeabi_BUFSIZ; S#define BUFSIZ (__CLIBNS __aeabi_BUFSIZ) Sextern const int __aeabi_FOPEN_MAX; S#define FOPEN_MAX (__CLIBNS __aeabi_FOPEN_MAX) Sextern const int __aeabi_TMP_MAX; S#define TMP_MAX (__CLIBNS __aeabi_TMP_MAX) Sextern const int __aeabi_FILENAME_MAX; S#define FILENAME_MAX (__CLIBNS __aeabi_FILENAME_MAX) Sextern const int __aeabi_L_tmpnam; S#define L_tmpnam (__CLIBNS __aeabi_L_tmpnam) N#else N#define stdin (&__CLIBNS __stdin) N /* pointer to a FILE object associated with standard input stream */ N#define stdout (&__CLIBNS __stdout) N /* pointer to a FILE object associated with standard output stream */ N#define stderr (&__CLIBNS __stderr) N /* pointer to a FILE object associated with standard error stream */ N N#define _IOFBF 0x100 /* fully buffered IO */ N#define _IOLBF 0x200 /* line buffered IO */ N#define _IONBF 0x400 /* unbuffered IO */ N N /* Various default file IO buffer sizes */ N#define BUFSIZ (512) /* system buffer size (as used by setbuf) */ N N#define FOPEN_MAX _SYS_OPEN N /* N * an integral constant expression that is the minimum number of files that N * this implementation guarantees can be open simultaneously. N */ N N#define FILENAME_MAX 256 N /* N * an integral constant expression that is the size of an array of char N * large enough to hold the longest filename string N */ N#define L_tmpnam FILENAME_MAX N /* N * an integral constant expression that is the size of an array of char N * large enough to hold a temporary file name string generated by the N * tmpnam function. N */ N#define TMP_MAX 256 N /* N * an integral constant expression that is the minimum number of unique N * file names that shall be generated by the tmpnam function. N */ N N#endif N N#define EOF (-1) N /* N * negative integral constant, indicates end-of-file, that is, no more input N * from a stream. N */ N N#define SEEK_SET 0 /* start of stream (see fseek) */ N#define SEEK_CUR 1 /* current position in stream (see fseek) */ N#define SEEK_END 2 /* end of stream (see fseek) */ N N /* N * _IOBIN is the flag passed to _sys_write to denote a binary N * file. N */ N#define _IOBIN 0x04 /* binary stream */ N N#define __STDIN_BUFSIZ (64) /* default stdin buffer size */ N#define __STDOUT_BUFSIZ (64) /* default stdout buffer size */ N#define __STDERR_BUFSIZ (16) /* default stderr buffer size */ N Nextern _ARMABI int remove(const char * /*filename*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int remove(const char * ) __attribute__((__nonnull__(1))); N /* N * causes the file whose name is the string pointed to by filename to be N * removed. Subsequent attempts to open the file will fail, unless it is N * created anew. If the file is open, the behaviour of the remove function N * is implementation-defined. N * Returns: zero if the operation succeeds, nonzero if it fails. N */ Nextern _ARMABI int rename(const char * /*old*/, const char * /*new*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int rename(const char * , const char * ) __attribute__((__nonnull__(1,2))); N /* N * causes the file whose name is the string pointed to by old to be N * henceforth known by the name given by the string pointed to by new. The N * file named old is effectively removed. If a file named by the string N * pointed to by new exists prior to the call of the rename function, the N * behaviour is implementation-defined. N * Returns: zero if the operation succeeds, nonzero if it fails, in which N * case if the file existed previously it is still known by its N * original name. N */ Nextern _ARMABI FILE *tmpfile(void); Xextern __declspec(__nothrow) FILE *tmpfile(void); N /* N * creates a temporary binary file that will be automatically removed when N * it is closed or at program termination. The file is opened for update. N * Returns: a pointer to the stream of the file that it created. If the file N * cannot be created, a null pointer is returned. N */ Nextern _ARMABI char *tmpnam(char * /*s*/); Xextern __declspec(__nothrow) char *tmpnam(char * ); N /* N * generates a string that is not the same as the name of an existing file. N * The tmpnam function generates a different string each time it is called, N * up to TMP_MAX times. If it is called more than TMP_MAX times, the N * behaviour is implementation-defined. N * Returns: If the argument is a null pointer, the tmpnam function leaves N * its result in an internal static object and returns a pointer to N * that object. Subsequent calls to the tmpnam function may modify N * the same object. if the argument is not a null pointer, it is N * assumed to point to an array of at least L_tmpnam characters; N * the tmpnam function writes its result in that array and returns N * the argument as its value. N */ N Nextern _ARMABI int fclose(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int fclose(FILE * ) __attribute__((__nonnull__(1))); N /* N * causes the stream pointed to by stream to be flushed and the associated N * file to be closed. Any unwritten buffered data for the stream are N * delivered to the host environment to be written to the file; any unread N * buffered data are discarded. The stream is disassociated from the file. N * If the associated buffer was automatically allocated, it is deallocated. N * Returns: zero if the stream was succesfully closed, or nonzero if any N * errors were detected or if the stream was already closed. N */ Nextern _ARMABI int fflush(FILE * /*stream*/); Xextern __declspec(__nothrow) int fflush(FILE * ); N /* N * If the stream points to an output or update stream in which the most N * recent operation was output, the fflush function causes any unwritten N * data for that stream to be delivered to the host environment to be N * written to the file. If the stream points to an input or update stream, N * the fflush function undoes the effect of any preceding ungetc operation N * on the stream. N * Returns: nonzero if a write error occurs. N */ Nextern _ARMABI FILE *fopen(const char * __restrict /*filename*/, Xextern __declspec(__nothrow) FILE *fopen(const char * __restrict , N const char * __restrict /*mode*/) __attribute__((__nonnull__(1,2))); N /* N * opens the file whose name is the string pointed to by filename, and N * associates a stream with it. N * The argument mode points to a string beginning with one of the following N * sequences: N * "r" open text file for reading N * "w" create text file for writing, or truncate to zero length N * "a" append; open text file or create for writing at eof N * "rb" open binary file for reading N * "wb" create binary file for writing, or truncate to zero length N * "ab" append; open binary file or create for writing at eof N * "r+" open text file for update (reading and writing) N * "w+" create text file for update, or truncate to zero length N * "a+" append; open text file or create for update, writing at eof N * "r+b"/"rb+" open binary file for update (reading and writing) N * "w+b"/"wb+" create binary file for update, or truncate to zero length N * "a+b"/"ab+" append; open binary file or create for update, writing at eof N * N * Opening a file with read mode ('r' as the first character in the mode N * argument) fails if the file does not exist or cannot be read. N * Opening a file with append mode ('a' as the first character in the mode N * argument) causes all subsequent writes to be forced to the current end of N * file, regardless of intervening calls to the fseek function. In some N * implementations, opening a binary file with append mode ('b' as the N * second or third character in the mode argument) may initially position N * the file position indicator beyond the last data written, because of the N * NUL padding. N * When a file is opened with update mode ('+' as the second or third N * character in the mode argument), both input and output may be performed N * on the associated stream. However, output may not be directly followed N * by input without an intervening call to the fflush fuction or to a file N * positioning function (fseek, fsetpos, or rewind), and input be not be N * directly followed by output without an intervening call to the fflush N * fuction or to a file positioning function, unless the input operation N * encounters end-of-file. Opening a file with update mode may open or N * create a binary stream in some implementations. When opened, a stream N * is fully buffered if and only if it does not refer to an interactive N * device. The error and end-of-file indicators for the stream are N * cleared. N * Returns: a pointer to the object controlling the stream. If the open N * operation fails, fopen returns a null pointer. N */ Nextern _ARMABI FILE *freopen(const char * __restrict /*filename*/, Xextern __declspec(__nothrow) FILE *freopen(const char * __restrict , N const char * __restrict /*mode*/, N FILE * __restrict /*stream*/) __attribute__((__nonnull__(2,3))); N /* N * opens the file whose name is the string pointed to by filename and N * associates the stream pointed to by stream with it. The mode argument is N * used just as in the fopen function. N * The freopen function first attempts to close any file that is associated N * with the specified stream. Failure to close the file successfully is N * ignored. The error and end-of-file indicators for the stream are cleared. N * Returns: a null pointer if the operation fails. Otherwise, freopen N * returns the value of the stream. N */ Nextern _ARMABI void setbuf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) void setbuf(FILE * __restrict , N char * __restrict /*buf*/) __attribute__((__nonnull__(1))); N /* N * Except that it returns no value, the setbuf function is equivalent to the N * setvbuf function invoked with the values _IOFBF for mode and BUFSIZ for N * size, or (if buf is a null pointer), with the value _IONBF for mode. N * Returns: no value. N */ Nextern _ARMABI int setvbuf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int setvbuf(FILE * __restrict , N char * __restrict /*buf*/, N int /*mode*/, size_t /*size*/) __attribute__((__nonnull__(1))); N /* N * may be used after the stream pointed to by stream has been associated N * with an open file but before it is read or written. The argument mode N * determines how stream will be buffered, as follows: _IOFBF causes N * input/output to be fully buffered; _IOLBF causes output to be line N * buffered (the buffer will be flushed when a new-line character is N * written, when the buffer is full, or when input is requested); _IONBF N * causes input/output to be completely unbuffered. If buf is not the null N * pointer, the array it points to may be used instead of an automatically N * allocated buffer (the buffer must have a lifetime at least as great as N * the open stream, so the stream should be closed before a buffer that has N * automatic storage duration is deallocated upon block exit). The argument N * size specifies the size of the array. The contents of the array at any N * time are indeterminate. N * Returns: zero on success, or nonzero if an invalid value is given for N * mode or size, or if the request cannot be honoured. N */ N#pragma __printf_args Nextern _ARMABI int fprintf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int fprintf(FILE * __restrict , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); N /* N * writes output to the stream pointed to by stream, under control of the N * string pointed to by format that specifies how subsequent arguments are N * converted for output. If there are insufficient arguments for the format, N * the behaviour is undefined. If the format is exhausted while arguments N * remain, the excess arguments are evaluated but otherwise ignored. The N * fprintf function returns when the end of the format string is reached. N * The format shall be a multibyte character sequence, beginning and ending N * in its initial shift state. The format is composed of zero or more N * directives: ordinary multibyte characters (not %), which are copied N * unchanged to the output stream; and conversion specifiers, each of which N * results in fetching zero or more subsequent arguments. Each conversion N * specification is introduced by the character %. For a description of the N * available conversion specifiers refer to section 4.9.6.1 in the ANSI N * draft mentioned at the start of this file or to any modern textbook on C. N * The minimum value for the maximum number of characters producable by any N * single conversion is at least 509. N * Returns: the number of characters transmitted, or a negative value if an N * output error occurred. N */ N#pragma __printf_args Nextern _ARMABI int _fprintf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int _fprintf(FILE * __restrict , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to fprintf, but does not support floating-point formats. N * You can use instead of fprintf to improve code size. N * Returns: as fprintf. N */ N#pragma __printf_args Nextern _ARMABI int printf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int printf(const char * __restrict , ...) __attribute__((__nonnull__(1))); N /* N * is equivalent to fprintf with the argument stdout interposed before the N * arguments to printf. N * Returns: the number of characters transmitted, or a negative value if an N * output error occurred. N */ N#pragma __printf_args Nextern _ARMABI int _printf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int _printf(const char * __restrict , ...) __attribute__((__nonnull__(1))); N /* N * is equivalent to printf, but does not support floating-point formats. N * You can use instead of printf to improve code size. N * Returns: as printf. N */ N#pragma __printf_args Nextern _ARMABI int sprintf(char * __restrict /*s*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int sprintf(char * __restrict , const char * __restrict , ...) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to fprintf, except that the argument s specifies an array N * into which the generated output is to be written, rather than to a N * stream. A null character is written at the end of the characters written; N * it is not counted as part of the returned sum. N * Returns: the number of characters written to the array, not counting the N * terminating null character. N */ N#pragma __printf_args Nextern _ARMABI int _sprintf(char * __restrict /*s*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int _sprintf(char * __restrict , const char * __restrict , ...) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to sprintf, but does not support floating-point formats. N * You can use instead of sprintf to improve code size. N * Returns: as sprintf. N */ N N#pragma __printf_args Nextern _ARMABI int __ARM_snprintf(char * __restrict /*s*/, size_t /*n*/, Xextern __declspec(__nothrow) int __ARM_snprintf(char * __restrict , size_t , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3))); N N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) X#if !0L || (1L && 199901L <= 199409L) || (0L && 201103L <= __cplusplus) N#pragma __printf_args Nextern _ARMABI int snprintf(char * __restrict /*s*/, size_t /*n*/, Xextern __declspec(__nothrow) int snprintf(char * __restrict , size_t , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3))); N /* N * is equivalent to fprintf, except that the argument s specifies an array N * into which the generated output is to be written, rather than to a N * stream. The argument n specifies the size of the output array, so as to N * avoid overflowing the buffer. N * A null character is written at the end of the characters written, even N * if the formatting was not completed; it is not counted as part of the N * returned sum. At most n characters of the output buffer are used, N * _including_ the null character. N * Returns: the number of characters that would have been written to the N * array, not counting the terminating null character, if the N * array had been big enough. So if the return is >=0 and =n, the string was truncated (but there is still a null char N * at the end of what was written); if the return is <0, there was N * an error. N */ N#endif N#pragma __printf_args Nextern _ARMABI int _snprintf(char * __restrict /*s*/, size_t /*n*/, Xextern __declspec(__nothrow) int _snprintf(char * __restrict , size_t , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3))); N /* N * is equivalent to snprintf, but does not support floating-point formats. N * You can use instead of snprintf to improve code size. N * Returns: as snprintf. N */ N#pragma __scanf_args Nextern _ARMABI int fscanf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int fscanf(FILE * __restrict , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); N /* N * reads input from the stream pointed to by stream, under control of the N * string pointed to by format that specifies the admissible input sequences N * and how thay are to be converted for assignment, using subsequent N * arguments as pointers to the objects to receive the converted input. If N * there are insufficient arguments for the format, the behaviour is N * undefined. If the format is exhausted while arguments remain, the excess N * arguments are evaluated but otherwise ignored. N * The format is composed of zero or more directives: one or more N * white-space characters; an ordinary character (not %); or a conversion N * specification. Each conversion specification is introduced by the N * character %. For a description of the available conversion specifiers N * refer to section 4.9.6.2 in the ANSI draft mentioned at the start of this N * file, or to any modern textbook on C. N * If end-of-file is encountered during input, conversion is terminated. If N * end-of-file occurs before any characters matching the current directive N * have been read (other than leading white space, where permitted), N * execution of the current directive terminates with an input failure; N * otherwise, unless execution of the current directive is terminated with a N * matching failure, execution of the following directive (if any) is N * terminated with an input failure. N * If conversions terminates on a conflicting input character, the offending N * input character is left unread in the input strem. Trailing white space N * (including new-line characters) is left unread unless matched by a N * directive. The success of literal matches and suppressed asignments is N * not directly determinable other than via the %n directive. N * Returns: the value of the macro EOF if an input failure occurs before any N * conversion. Otherwise, the fscanf function returns the number of N * input items assigned, which can be fewer than provided for, or N * even zero, in the event of an early conflict between an input N * character and the format. N */ N#pragma __scanf_args Nextern _ARMABI int _fscanf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int _fscanf(FILE * __restrict , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to fscanf, but does not support floating-point formats. N * You can use instead of fscanf to improve code size. N * Returns: as fscanf. N */ N#pragma __scanf_args Nextern _ARMABI int scanf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int scanf(const char * __restrict , ...) __attribute__((__nonnull__(1))); N /* N * is equivalent to fscanf with the argument stdin interposed before the N * arguments to scanf. N * Returns: the value of the macro EOF if an input failure occurs before any N * conversion. Otherwise, the scanf function returns the number of N * input items assigned, which can be fewer than provided for, or N * even zero, in the event of an early matching failure. N */ N#pragma __scanf_args Nextern _ARMABI int _scanf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int _scanf(const char * __restrict , ...) __attribute__((__nonnull__(1))); N /* N * is equivalent to scanf, but does not support floating-point formats. N * You can use instead of scanf to improve code size. N * Returns: as scanf. N */ N#pragma __scanf_args Nextern _ARMABI int sscanf(const char * __restrict /*s*/, Xextern __declspec(__nothrow) int sscanf(const char * __restrict , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to fscanf except that the argument s specifies a string N * from which the input is to be obtained, rather than from a stream. N * Reaching the end of the string is equivalent to encountering end-of-file N * for the fscanf function. N * Returns: the value of the macro EOF if an input failure occurs before any N * conversion. Otherwise, the scanf function returns the number of N * input items assigned, which can be fewer than provided for, or N * even zero, in the event of an early matching failure. N */ N#pragma __scanf_args Nextern _ARMABI int _sscanf(const char * __restrict /*s*/, Xextern __declspec(__nothrow) int _sscanf(const char * __restrict , N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to sscanf, but does not support floating-point formats. N * You can use instead of sscanf to improve code size. N * Returns: as sscanf. N */ N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) X#if !0L || (1L && 199901L <= 199409L) || (0L && 201103L <= __cplusplus) N/* C99 additions */ Nextern _ARMABI int vfscanf(FILE * __restrict /*stream*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int vfscanf(FILE * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); Nextern _ARMABI int vscanf(const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int vscanf(const char * __restrict , __va_list) __attribute__((__nonnull__(1))); Nextern _ARMABI int vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); N#endif Nextern _ARMABI int _vfscanf(FILE * __restrict /*stream*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int _vfscanf(FILE * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); Nextern _ARMABI int _vscanf(const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int _vscanf(const char * __restrict , __va_list) __attribute__((__nonnull__(1))); Nextern _ARMABI int _vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int _vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); Nextern _ARMABI int __ARM_vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int __ARM_vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); N Nextern _ARMABI int vprintf(const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int vprintf(const char * __restrict , __va_list ) __attribute__((__nonnull__(1))); N /* N * is equivalent to printf, with the variable argument list replaced by arg, N * which has been initialised by the va_start macro (and possibly subsequent N * va_arg calls). The vprintf function does not invoke the va_end function. N * Returns: the number of characters transmitted, or a negative value if an N * output error occurred. N */ Nextern _ARMABI int _vprintf(const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int _vprintf(const char * __restrict , __va_list ) __attribute__((__nonnull__(1))); N /* N * is equivalent to vprintf, but does not support floating-point formats. N * You can use instead of vprintf to improve code size. N * Returns: as vprintf. N */ Nextern _ARMABI int vfprintf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int vfprintf(FILE * __restrict , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to fprintf, with the variable argument list replaced by N * arg, which has been initialised by the va_start macro (and possibly N * subsequent va_arg calls). The vfprintf function does not invoke the N * va_end function. N * Returns: the number of characters transmitted, or a negative value if an N * output error occurred. N */ Nextern _ARMABI int vsprintf(char * __restrict /*s*/, Xextern __declspec(__nothrow) int vsprintf(char * __restrict , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to sprintf, with the variable argument list replaced by N * arg, which has been initialised by the va_start macro (and possibly N * subsequent va_arg calls). The vsprintf function does not invoke the N * va_end function. N * Returns: the number of characters written in the array, not counting the N * terminating null character. N */ Nextern _ARMABI int __ARM_vsnprintf(char * __restrict /*s*/, size_t /*n*/, Xextern __declspec(__nothrow) int __ARM_vsnprintf(char * __restrict , size_t , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3))); N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) X#if !0L || (1L && 199901L <= 199409L) || (0L && 201103L <= __cplusplus) Nextern _ARMABI int vsnprintf(char * __restrict /*s*/, size_t /*n*/, Xextern __declspec(__nothrow) int vsnprintf(char * __restrict , size_t , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3))); N /* N * is equivalent to snprintf, with the variable argument list replaced by N * arg, which has been initialised by the va_start macro (and possibly N * subsequent va_arg calls). The vsprintf function does not invoke the N * va_end function. N * Returns: the number of characters that would have been written in the N * array, not counting the terminating null character. As N * snprintf. N */ N#endif Nextern _ARMABI int _vsprintf(char * __restrict /*s*/, Xextern __declspec(__nothrow) int _vsprintf(char * __restrict , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to vsprintf, but does not support floating-point formats. N * You can use instead of vsprintf to improve code size. N * Returns: as vsprintf. N */ Nextern _ARMABI int _vfprintf(FILE * __restrict /*stream*/, Xextern __declspec(__nothrow) int _vfprintf(FILE * __restrict , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); N /* N * is equivalent to vfprintf, but does not support floating-point formats. N * You can use instead of vfprintf to improve code size. N * Returns: as vfprintf. N */ Nextern _ARMABI int _vsnprintf(char * __restrict /*s*/, size_t /*n*/, Xextern __declspec(__nothrow) int _vsnprintf(char * __restrict , size_t , N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3))); N /* N * is equivalent to vsnprintf, but does not support floating-point formats. N * You can use instead of vsnprintf to improve code size. N * Returns: as vsnprintf. N */ N#if !defined(__STRICT_ANSI__) X#if !0L N#pragma __printf_args Nextern _ARMABI int asprintf(char ** /*strp*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int asprintf(char ** , const char * __restrict , ...) __attribute__((__nonnull__(2))); Nextern _ARMABI int vasprintf(char ** /*strp*/, const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int vasprintf(char ** , const char * __restrict , __va_list ) __attribute__((__nonnull__(2))); N#endif N#pragma __printf_args Nextern _ARMABI int __ARM_asprintf(char ** /*strp*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int __ARM_asprintf(char ** , const char * __restrict , ...) __attribute__((__nonnull__(2))); Nextern _ARMABI int __ARM_vasprintf(char ** /*strp*/, const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int __ARM_vasprintf(char ** , const char * __restrict , __va_list ) __attribute__((__nonnull__(2))); N /* N * dynamically allocates a buffer of the right size for the N * formatted string, and returns it in (*strp). Formal return value N * is the same as any other printf variant, except that it returns N * -1 if the buffer could not be allocated. N * N * (The functions with __ARM_ prefixed names are identical to the N * ones without, but are available in all compilation modes without N * violating user namespace.) N */ N Nextern _ARMABI int fgetc(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int fgetc(FILE * ) __attribute__((__nonnull__(1))); N /* N * obtains the next character (if present) as an unsigned char converted to N * an int, from the input stream pointed to by stream, and advances the N * associated file position indicator (if defined). N * Returns: the next character from the input stream pointed to by stream. N * If the stream is at end-of-file, the end-of-file indicator is N * set and fgetc returns EOF. If a read error occurs, the error N * indicator is set and fgetc returns EOF. N */ Nextern _ARMABI char *fgets(char * __restrict /*s*/, int /*n*/, Xextern __declspec(__nothrow) char *fgets(char * __restrict , int , N FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,3))); N /* N * reads at most one less than the number of characters specified by n from N * the stream pointed to by stream into the array pointed to by s. No N * additional characters are read after a new-line character (which is N * retained) or after end-of-file. A null character is written immediately N * after the last character read into the array. N * Returns: s if successful. If end-of-file is encountered and no characters N * have been read into the array, the contents of the array remain N * unchanged and a null pointer is returned. If a read error occurs N * during the operation, the array contents are indeterminate and a N * null pointer is returned. N */ Nextern _ARMABI int fputc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int fputc(int , FILE * ) __attribute__((__nonnull__(2))); N /* N * writes the character specified by c (converted to an unsigned char) to N * the output stream pointed to by stream, at the position indicated by the N * asociated file position indicator (if defined), and advances the N * indicator appropriately. If the file position indicator is not defined, N * the character is appended to the output stream. N * Returns: the character written. If a write error occurs, the error N * indicator is set and fputc returns EOF. N */ Nextern _ARMABI int fputs(const char * __restrict /*s*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int fputs(const char * __restrict , FILE * __restrict ) __attribute__((__nonnull__(1,2))); N /* N * writes the string pointed to by s to the stream pointed to by stream. N * The terminating null character is not written. N * Returns: EOF if a write error occurs; otherwise it returns a nonnegative N * value. N */ Nextern _ARMABI int getc(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int getc(FILE * ) __attribute__((__nonnull__(1))); N /* N * is equivalent to fgetc except that it may be implemented as an unsafe N * macro (stream may be evaluated more than once, so the argument should N * never be an expression with side-effects). N * Returns: the next character from the input stream pointed to by stream. N * If the stream is at end-of-file, the end-of-file indicator is N * set and getc returns EOF. If a read error occurs, the error N * indicator is set and getc returns EOF. N */ N#ifdef __cplusplus S inline int getchar() { return getc(stdin); } N#else N #define getchar() getc(stdin) N extern _ARMABI int (getchar)(void); X extern __declspec(__nothrow) int (getchar)(void); N#endif N /* N * is equivalent to getc with the argument stdin. N * Returns: the next character from the input stream pointed to by stdin. N * If the stream is at end-of-file, the end-of-file indicator is N * set and getchar returns EOF. If a read error occurs, the error N * indicator is set and getchar returns EOF. N */ Nextern _ARMABI char *gets(char * /*s*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) char *gets(char * ) __attribute__((__nonnull__(1))); N /* N * reads characters from the input stream pointed to by stdin into the array N * pointed to by s, until end-of-file is encountered or a new-line character N * is read. Any new-line character is discarded, and a null character is N * written immediately after the last character read into the array. N * Returns: s if successful. If end-of-file is encountered and no characters N * have been read into the array, the contents of the array remain N * unchanged and a null pointer is returned. If a read error occurs N * during the operation, the array contents are indeterminate and a N * null pointer is returned. N */ Nextern _ARMABI int putc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int putc(int , FILE * ) __attribute__((__nonnull__(2))); N /* N * is equivalent to fputc except that it may be implemented as aan unsafe N * macro (stream may be evaluated more than once, so the argument should N * never be an expression with side-effects). N * Returns: the character written. If a write error occurs, the error N * indicator is set and putc returns EOF. N */ N#ifdef __cplusplus S inline int putchar(int __c) { return putc(__c, stdout); } N#else N #define putchar(c) putc(c, stdout) N extern _ARMABI int (putchar)(int /*c*/); X extern __declspec(__nothrow) int (putchar)(int ); N#endif N /* N * is equivalent to putc with the second argument stdout. N * Returns: the character written. If a write error occurs, the error N * indicator is set and putc returns EOF. N */ Nextern _ARMABI int puts(const char * /*s*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int puts(const char * ) __attribute__((__nonnull__(1))); N /* N * writes the string pointed to by s to the stream pointed to by stdout, and N * appends a new-line character to the output. The terminating null N * character is not written. N * Returns: EOF if a write error occurs; otherwise it returns a nonnegative N * value. N */ Nextern _ARMABI int ungetc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) int ungetc(int , FILE * ) __attribute__((__nonnull__(2))); N /* N * pushes the character specified by c (converted to an unsigned char) back N * onto the input stream pointed to by stream. The character will be N * returned by the next read on that stream. An intervening call to the N * fflush function or to a file positioning function (fseek, fsetpos, N * rewind) discards any pushed-back characters. The extern _ARMABIal storage N * corresponding to the stream is unchanged. N * One character pushback is guaranteed. If the unget function is called too N * many times on the same stream without an intervening read or file N * positioning operation on that stream, the operation may fail. N * If the value of c equals that of the macro EOF, the operation fails and N * the input stream is unchanged. N * A successful call to the ungetc function clears the end-of-file N * indicator. The value of the file position indicator after reading or N * discarding all pushed-back characters shall be the same as it was before N * the characters were pushed back. For a text stream, the value of the file N * position indicator after a successful call to the ungetc function is N * unspecified until all pushed-back characters are read or discarded. For a N * binary stream, the file position indicator is decremented by each N * successful call to the ungetc function; if its value was zero before a N * call, it is indeterminate after the call. N * Returns: the character pushed back after conversion, or EOF if the N * operation fails. N */ N Nextern _ARMABI size_t fread(void * __restrict /*ptr*/, Xextern __declspec(__nothrow) size_t fread(void * __restrict , N size_t /*size*/, size_t /*nmemb*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,4))); N /* N * reads into the array pointed to by ptr, up to nmemb members whose size is N * specified by size, from the stream pointed to by stream. The file N * position indicator (if defined) is advanced by the number of characters N * successfully read. If an error occurs, the resulting value of the file N * position indicator is indeterminate. If a partial member is read, its N * value is indeterminate. The ferror or feof function shall be used to N * distinguish between a read error and end-of-file. N * Returns: the number of members successfully read, which may be less than N * nmemb if a read error or end-of-file is encountered. If size or N * nmemb is zero, fread returns zero and the contents of the array N * and the state of the stream remain unchanged. N */ N Nextern _ARMABI size_t __fread_bytes_avail(void * __restrict /*ptr*/, Xextern __declspec(__nothrow) size_t __fread_bytes_avail(void * __restrict , N size_t /*count*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,3))); N /* N * reads into the array pointed to by ptr, up to count characters from the N * stream pointed to by stream. The file position indicator (if defined) N * is advanced by the number of characters successfully read. If an error N * occurs, the resulting value of the file position indicator is N * indeterminate. The ferror or feof function shall be used to N * distinguish between a read error and end-of-file. The call will block N * only if no characters are available. N * Returns: the number of characters successfully read, which may be less than N * count. If count is zero, __fread_bytes_avail returns zero and N * the contents of the array and the state of the stream remain N * unchanged. N */ N Nextern _ARMABI size_t fwrite(const void * __restrict /*ptr*/, Xextern __declspec(__nothrow) size_t fwrite(const void * __restrict , N size_t /*size*/, size_t /*nmemb*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,4))); N /* N * writes, from the array pointed to by ptr up to nmemb members whose size N * is specified by size, to the stream pointed to by stream. The file N * position indicator (if defined) is advanced by the number of characters N * successfully written. If an error occurs, the resulting value of the file N * position indicator is indeterminate. N * Returns: the number of members successfully written, which will be less N * than nmemb only if a write error is encountered. N */ N Nextern _ARMABI int fgetpos(FILE * __restrict /*stream*/, fpos_t * __restrict /*pos*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int fgetpos(FILE * __restrict , fpos_t * __restrict ) __attribute__((__nonnull__(1,2))); N /* N * stores the current value of the file position indicator for the stream N * pointed to by stream in the object pointed to by pos. The value stored N * contains unspecified information usable by the fsetpos function for N * repositioning the stream to its position at the time of the call to the N * fgetpos function. N * Returns: zero, if successful. Otherwise nonzero is returned and the N * integer expression errno is set to an implementation-defined N * nonzero value. N */ Nextern _ARMABI int fseek(FILE * /*stream*/, long int /*offset*/, int /*whence*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int fseek(FILE * , long int , int ) __attribute__((__nonnull__(1))); N /* N * sets the file position indicator for the stream pointed to by stream. N * For a binary stream, the new position is at the signed number of N * characters specified by offset away from the point specified by whence. N * The specified point is the beginning of the file for SEEK_SET, the N * current position in the file for SEEK_CUR, or end-of-file for SEEK_END. N * A binary stream need not meaningfully support fseek calls with a whence N * value of SEEK_END. N * For a text stream, either offset shall be zero, or offset shall be a N * value returned by an earlier call to the ftell function on the same N * stream and whence shall be SEEK_SET. N * The fseek function clears the end-of-file indicator and undoes any N * effects of the ungetc function on the same stream. After an fseek call, N * the next operation on an update stream may be either input or output. N * Returns: nonzero only for a request that cannot be satisfied. N */ Nextern _ARMABI int fsetpos(FILE * __restrict /*stream*/, const fpos_t * __restrict /*pos*/) __attribute__((__nonnull__(1,2))); Xextern __declspec(__nothrow) int fsetpos(FILE * __restrict , const fpos_t * __restrict ) __attribute__((__nonnull__(1,2))); N /* N * sets the file position indicator for the stream pointed to by stream N * according to the value of the object pointed to by pos, which shall be a N * value returned by an earlier call to the fgetpos function on the same N * stream. N * The fsetpos function clears the end-of-file indicator and undoes any N * effects of the ungetc function on the same stream. After an fsetpos call, N * the next operation on an update stream may be either input or output. N * Returns: zero, if successful. Otherwise nonzero is returned and the N * integer expression errno is set to an implementation-defined N * nonzero value. N */ Nextern _ARMABI long int ftell(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) long int ftell(FILE * ) __attribute__((__nonnull__(1))); N /* N * obtains the current value of the file position indicator for the stream N * pointed to by stream. For a binary stream, the value is the number of N * characters from the beginning of the file. For a text stream, the file N * position indicator contains unspecified information, usable by the fseek N * function for returning the file position indicator to its position at the N * time of the ftell call; the difference between two such return values is N * not necessarily a meaningful measure of the number of characters written N * or read. N * Returns: if successful, the current value of the file position indicator. N * On failure, the ftell function returns -1L and sets the integer N * expression errno to an implementation-defined nonzero value. N */ Nextern _ARMABI void rewind(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) void rewind(FILE * ) __attribute__((__nonnull__(1))); N /* N * sets the file position indicator for the stream pointed to by stream to N * the beginning of the file. It is equivalent to N * (void)fseek(stream, 0L, SEEK_SET) N * except that the error indicator for the stream is also cleared. N * Returns: no value. N */ N Nextern _ARMABI void clearerr(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) void clearerr(FILE * ) __attribute__((__nonnull__(1))); N /* N * clears the end-of-file and error indicators for the stream pointed to by N * stream. These indicators are cleared only when the file is opened or by N * an explicit call to the clearerr function or to the rewind function. N * Returns: no value. N */ N Nextern _ARMABI int feof(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int feof(FILE * ) __attribute__((__nonnull__(1))); N /* N * tests the end-of-file indicator for the stream pointed to by stream. N * Returns: nonzero iff the end-of-file indicator is set for stream. N */ Nextern _ARMABI int ferror(FILE * /*stream*/) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int ferror(FILE * ) __attribute__((__nonnull__(1))); N /* N * tests the error indicator for the stream pointed to by stream. N * Returns: nonzero iff the error indicator is set for stream. N */ Nextern _ARMABI void perror(const char * /*s*/); Xextern __declspec(__nothrow) void perror(const char * ); N /* N * maps the error number in the integer expression errno to an error N * message. It writes a sequence of characters to the standard error stream N * thus: first (if s is not a null pointer and the character pointed to by N * s is not the null character), the string pointed to by s followed by a N * colon and a space; then an appropriate error message string followed by N * a new-line character. The contents of the error message strings are the N * same as those returned by the strerror function with argument errno, N * which are implementation-defined. N * Returns: no value. N */ N Nextern _ARMABI int _fisatty(FILE * /*stream*/ ) __attribute__((__nonnull__(1))); Xextern __declspec(__nothrow) int _fisatty(FILE * ) __attribute__((__nonnull__(1))); N /* Returns 1 if the stream is tty (stdin), 0 otherwise. Not ANSI compliant. N */ N Nextern _ARMABI void __use_no_semihosting_swi(void); Xextern __declspec(__nothrow) void __use_no_semihosting_swi(void); Nextern _ARMABI void __use_no_semihosting(void); Xextern __declspec(__nothrow) void __use_no_semihosting(void); N /* N * Referencing either of these symbols will cause a link-time N * error if any library functions that use semihosting SWI N * calls are also present in the link, i.e. you define it if N * you want to make sure you haven't accidentally used any such N * SWIs. N */ N N #ifdef __cplusplus S } /* extern "C" */ S } /* namespace std */ N #endif N #endif /* __STDIO_DECLS */ N N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L S #define _AEABI_PORTABLE N #endif N N #if defined(__cplusplus) && !defined(__STDIO_NO_EXPORTS) X #if 0L && !0L S using ::std::size_t; S using ::std::fpos_t; S using ::std::FILE; S using ::std::remove; S using ::std::rename; S using ::std::tmpfile; S using ::std::tmpnam; S using ::std::fclose; S using ::std::fflush; S using ::std::fopen; S using ::std::freopen; S using ::std::setbuf; S using ::std::setvbuf; S using ::std::fprintf; S using ::std::_fprintf; S using ::std::printf; S using ::std::_printf; S using ::std::sprintf; S using ::std::_sprintf; S #if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) S using ::std::snprintf; S using ::std::vsnprintf; S using ::std::vfscanf; S using ::std::vscanf; S using ::std::vsscanf; S #endif S using ::std::_snprintf; S using ::std::_vsnprintf; S#if !defined(__STRICT_ANSI__) S using ::std::asprintf; S using ::std::vasprintf; S#endif S using ::std::__ARM_asprintf; S using ::std::__ARM_vasprintf; S using ::std::__ARM_vsnprintf; S using ::std::__ARM_snprintf; S using ::std::__ARM_vsscanf; S using ::std::fscanf; S using ::std::_fscanf; S using ::std::scanf; S using ::std::_scanf; S using ::std::sscanf; S using ::std::_sscanf; S using ::std::_vfscanf; S using ::std::_vscanf; S using ::std::_vsscanf; S using ::std::vprintf; S using ::std::_vprintf; S using ::std::vfprintf; S using ::std::_vfprintf; S using ::std::vsprintf; S using ::std::_vsprintf; S using ::std::fgetc; S using ::std::fgets; S using ::std::fputc; S using ::std::fputs; S using ::std::getc; S using ::std::getchar; S using ::std::gets; S using ::std::putc; S using ::std::putchar; S using ::std::puts; S using ::std::ungetc; S using ::std::fread; S using ::std::__fread_bytes_avail; S using ::std::fwrite; S using ::std::fgetpos; S using ::std::fseek; S using ::std::fsetpos; S using ::std::ftell; S using ::std::rewind; S using ::std::clearerr; S using ::std::feof; S using ::std::ferror; S using ::std::perror; S using ::std::_fisatty; S using ::std::__use_no_semihosting_swi; S using ::std::__use_no_semihosting; N #endif N N#endif /* ndef __stdio_h */ N N/* end of stdio.h */ N L 11 "..\user\src\swj.c" 2 N#include L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h" 1 N/* N * math.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.5 N * Copyright (C) Codemist Ltd., 1988 N * Copyright 1991-1998,2004-2006,2014 ARM Limited. All rights reserved N */ N N/* N * RCS $Revision$ Codemist 0.03 N * Checkin $Date$ N * Revising $Author: statham $ N */ N N/* N * Parts of this file are based upon fdlibm: N * N * ==================================================== N * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. N * N * Developed at SunSoft, a Sun Microsystems, Inc. business. N * Permission to use, copy, modify, and distribute this N * software is freely granted, provided that this notice N * is preserved. N * ==================================================== N */ N N#ifndef __math_h N#define __math_h N#define __ARMCLIB_VERSION 5060037 N N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) X#if 0L || (1L && !0L) N /* armclang and non-strict armcc allow 'long long' in system headers */ N #define __LONGLONG long long N#else S /* strict armcc has '__int64' */ S #define __LONGLONG __int64 N#endif N N/* N * Some of these declarations are new in C99. To access them in C++ N * you can use -D__USE_C99_MATH (or -D__USE_C99_ALL). N */ N#ifndef __USE_C99_MATH N #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) X #if 0L || (1L && 199901L <= 199409L) || (0L && 201103L <= __cplusplus) S #define __USE_C99_MATH 1 N #endif N#endif N N#define _ARMABI __declspec(__nothrow) N#ifdef __TARGET_ARCH_AARCH64 S# define _ARMABI_SOFTFP __declspec(__nothrow) N#else N# define _ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) N# define __HAVE_LONGDOUBLE 1 N#endif N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) N#ifdef __FP_FENV_EXCEPTIONS S# define _ARMABI_FPEXCEPT _ARMABI N#else N# define _ARMABI_FPEXCEPT _ARMABI __attribute__((const)) N#endif N N#ifdef __cplusplus S#define _ARMABI_INLINE inline S#define _ARMABI_INLINE_DEF inline S#elif defined __GNUC__ || defined _USE_STATIC_INLINE X#elif 0L || 0L S#define _ARMABI_INLINE static __inline S#define _ARMABI_INLINE_DEF static __inline S#elif (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) X#elif (1L && 199901L <= 199409L) S#define _ARMABI_INLINE inline S#define _ARMABI_INLINE_DEF static inline N#else N#define _ARMABI_INLINE __inline N#define _ARMABI_INLINE_DEF __inline N#endif N N#ifdef __TARGET_ARCH_AARCH64 S# define _SOFTFP N#else N# define _SOFTFP __attribute__((__pcs__("aapcs"))) N#endif N N /* N * If the compiler supports signalling nans as per N965 then it N * will define __SUPPORT_SNAN__, in which case a user may define N * _WANT_SNAN in order to obtain the nans function, as well as the N * FP_NANS and FP_NANQ classification macros. N */ N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) X#if 0L && 0L S#pragma import(__use_snan) N#endif N N/* N * Macros for our inline functions down below. N * unsigned& __FLT(float x) - returns the bit pattern of x N * unsigned& __HI(double x) - returns the bit pattern of the high part of x N * (high part has exponent & sign bit in it) N * unsigned& __LO(double x) - returns the bit pattern of the low part of x N * N * We can assign to __FLT, __HI, and __LO and the appropriate bits get set in N * the floating point variable used. N * N * __HI & __LO are affected by the endianness and the target FPU. N */ N#define __FLT(x) (*(unsigned *)&(x)) N#if defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN) X#if 0L || 0L S# define __LO(x) (*(1 + (unsigned *)&(x))) S# define __HI(x) (*(unsigned *)&(x)) N#else /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ N# define __HI(x) (*(1 + (unsigned *)&(x))) N# define __LO(x) (*(unsigned *)&(x)) N#endif /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ N N# ifndef __MATH_DECLS N# define __MATH_DECLS N N N/* N * A set of functions that we don't actually want to put in the standard N * namespace ever. These are all called by the C99 macros. As they're N * not specified by any standard they can't belong in ::std::. The N * macro #defines are below amongst the standard function declarations. N * We only include these if we actually need them later on N */ N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 0L N# ifdef __cplusplus S extern "C" { N# endif /* __cplusplus */ N Nextern _SOFTFP unsigned __ARM_dcmp4(double /*x*/, double /*y*/); Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); Nextern _SOFTFP unsigned __ARM_fcmp4(float /*x*/, float /*y*/); Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); N /* N * Compare x and y and return the CPSR in r0. These means we can test for N * result types with bit pattern matching. N * N * These are a copy of the declarations in rt_fp.h keep in sync. N */ N Nextern _ARMABI_SOFTFP int __ARM_fpclassifyf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); Nextern _ARMABI_SOFTFP int __ARM_fpclassify(double /*x*/); Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); N /* Classify x into NaN, infinite, normal, subnormal, zero */ N /* Used by fpclassify macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinitef(float __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) N{ N return ((__FLT(__x) >> 23) & 0xff) != 0xff; X return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinite(double __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) N{ N return ((__HI(__x) >> 20) & 0x7ff) != 0x7ff; X return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; N} N /* Return 1 if __x is finite, 0 otherwise */ N /* Used by isfinite macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinff(float __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) N{ N return (__FLT(__x) << 1) == 0xff000000; X return ((*(unsigned *)&(__x)) << 1) == 0xff000000; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinf(double __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) N{ N return ((__HI(__x) << 1) == 0xffe00000) && (__LO(__x) == 0); X return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); N} N /* Return 1 if __x is infinite, 0 otherwise */ N /* Used by isinf macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreaterf(float __x, float __y) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) N{ N unsigned __f = __ARM_fcmp4(__x, __y) >> 28; N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreater(double __x, double __y) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) N{ N unsigned __f = __ARM_dcmp4(__x, __y) >> 28; N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ N} N /* N * Compare __x and __y and return 1 if __x < __y or __x > __y, 0 otherwise N * Used by islessgreater macro N */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnanf(float __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) N{ N return (0x7f800000 - (__FLT(__x) & 0x7fffffff)) >> 31; X return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnan(double __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) N{ N unsigned __xf = __HI(__x) | ((__LO(__x) == 0) ? 0 : 1); X unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); N return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; N} N /* Return 1 if __x is a NaN, 0 otherwise */ N /* Used by isnan macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormalf(float __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) N{ N unsigned __xe = (__FLT(__x) >> 23) & 0xff; X unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; N return (__xe != 0xff) && (__xe != 0); N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormal(double __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) N{ N unsigned __xe = (__HI(__x) >> 20) & 0x7ff; X unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; N return (__xe != 0x7ff) && (__xe != 0); N} N /* Return 1 if __x is a normalised number, 0 otherwise */ N /* used by isnormal macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbitf(float __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) N{ N return __FLT(__x) >> 31; X return (*(unsigned *)&(__x)) >> 31; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbit(double __x) X__inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) N{ N return __HI(__x) >> 31; X return (*(1 + (unsigned *)&(__x))) >> 31; N} N /* Return signbit of __x */ N /* Used by signbit macro */ N N# ifdef __cplusplus S } /* extern "C" */ N# endif /* __cplusplus */ N#endif /* Strict ANSI */ N N# undef __CLIBNS N N# ifdef __cplusplus S namespace std { S# define __CLIBNS ::std:: S extern "C" { N# else N# define __CLIBNS N# endif /* __cplusplus */ N N N#ifndef __has_builtin N #define __has_builtin(x) 0 N#endif N N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 0L N /* C99 additions */ N typedef float float_t; N typedef double double_t; N#if __has_builtin(__builtin_inf) X#if 0 S# define HUGE_VALF __builtin_inff() S# define HUGE_VALL __builtin_infl() S# define INFINITY __builtin_inff() S# define NAN __builtin_nanf("") N# else N# define HUGE_VALF ((float)__INFINITY__) N# define HUGE_VALL ((long double)__INFINITY__) N# define INFINITY ((float)__INFINITY__) N# define NAN (__ESCAPE__(0f_7FC00000)) N#endif N N# define MATH_ERRNO 1 N# define MATH_ERREXCEPT 2 Nextern const int math_errhandling; N#endif N#if __has_builtin(__builtin_inf) X#if 0 S# define HUGE_VAL __builtin_inf() N#else N# define HUGE_VAL ((double)__INFINITY__) N#endif N Nextern _ARMABI double acos(double /*x*/); Xextern __declspec(__nothrow) double acos(double ); N /* computes the principal value of the arc cosine of x */ N /* a domain error occurs for arguments not in the range -1 to 1 */ N /* Returns: the arc cosine in the range 0 to Pi. */ Nextern _ARMABI double asin(double /*x*/); Xextern __declspec(__nothrow) double asin(double ); N /* computes the principal value of the arc sine of x */ N /* a domain error occurs for arguments not in the range -1 to 1 */ N /* and -HUGE_VAL is returned. */ N /* Returns: the arc sine in the range -Pi/2 to Pi/2. */ N Nextern _ARMABI_PURE double atan(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double atan(double ); N /* computes the principal value of the arc tangent of x */ N /* Returns: the arc tangent in the range -Pi/2 to Pi/2. */ N Nextern _ARMABI double atan2(double /*y*/, double /*x*/); Xextern __declspec(__nothrow) double atan2(double , double ); N /* computes the principal value of the arc tangent of y/x, using the */ N /* signs of both arguments to determine the quadrant of the return value */ N /* a domain error occurs if both args are zero, and -HUGE_VAL returned. */ N /* Returns: the arc tangent of y/x, in the range -Pi to Pi. */ N Nextern _ARMABI double cos(double /*x*/); Xextern __declspec(__nothrow) double cos(double ); N /* computes the cosine of x (measured in radians). A large magnitude */ N /* argument may yield a result with little or no significance. */ N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ N /* Returns: the cosine value. */ Nextern _ARMABI double sin(double /*x*/); Xextern __declspec(__nothrow) double sin(double ); N /* computes the sine of x (measured in radians). A large magnitude */ N /* argument may yield a result with little or no significance. */ N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ N /* Returns: the sine value. */ N Nextern void __use_accurate_range_reduction(void); N /* reference this to select the larger, slower, but more accurate */ N /* range reduction in sin, cos and tan */ N Nextern _ARMABI double tan(double /*x*/); Xextern __declspec(__nothrow) double tan(double ); N /* computes the tangent of x (measured in radians). A large magnitude */ N /* argument may yield a result with little or no significance */ N /* Returns: the tangent value. */ N /* if range error; returns HUGE_VAL. */ N Nextern _ARMABI double cosh(double /*x*/); Xextern __declspec(__nothrow) double cosh(double ); N /* computes the hyperbolic cosine of x. A range error occurs if the */ N /* magnitude of x is too large. */ N /* Returns: the hyperbolic cosine value. */ N /* if range error; returns HUGE_VAL. */ Nextern _ARMABI double sinh(double /*x*/); Xextern __declspec(__nothrow) double sinh(double ); N /* computes the hyperbolic sine of x. A range error occurs if the */ N /* magnitude of x is too large. */ N /* Returns: the hyperbolic sine value. */ N /* if range error; returns -HUGE_VAL or HUGE_VAL depending */ N /* on the sign of the argument */ N Nextern _ARMABI_PURE double tanh(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double tanh(double ); N /* computes the hyperbolic tangent of x. */ N /* Returns: the hyperbolic tangent value. */ N Nextern _ARMABI double exp(double /*x*/); Xextern __declspec(__nothrow) double exp(double ); N /* computes the exponential function of x. A range error occurs if the */ N /* magnitude of x is too large. */ N /* Returns: the exponential value. */ N /* if underflow range error; 0 is returned. */ N /* if overflow range error; HUGE_VAL is returned. */ N Nextern _ARMABI double frexp(double /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); N /* breaks a floating-point number into a normalised fraction and an */ N /* integral power of 2. It stores the integer in the int object pointed */ N /* to by exp. */ N /* Returns: the value x, such that x is a double with magnitude in the */ N /* interval 0.5 to 1.0 or zero, and value equals x times 2 raised to the */ N /* power *exp. If value is zero, both parts of the result are zero. */ N Nextern _ARMABI double ldexp(double /*x*/, int /*exp*/); Xextern __declspec(__nothrow) double ldexp(double , int ); N /* multiplies a floating-point number by an integral power of 2. */ N /* A range error may occur. */ N /* Returns: the value of x times 2 raised to the power of exp. */ N /* if range error; HUGE_VAL is returned. */ Nextern _ARMABI double log(double /*x*/); Xextern __declspec(__nothrow) double log(double ); N /* computes the natural logarithm of x. A domain error occurs if the */ N /* argument is negative, and -HUGE_VAL is returned. A range error occurs */ N /* if the argument is zero. */ N /* Returns: the natural logarithm. */ N /* if range error; -HUGE_VAL is returned. */ Nextern _ARMABI double log10(double /*x*/); Xextern __declspec(__nothrow) double log10(double ); N /* computes the base-ten logarithm of x. A domain error occurs if the */ N /* argument is negative. A range error occurs if the argument is zero. */ N /* Returns: the base-ten logarithm. */ Nextern _ARMABI double modf(double /*value*/, double * /*iptr*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); N /* breaks the argument value into integral and fraction parts, each of */ N /* which has the same sign as the argument. It stores the integral part */ N /* as a double in the object pointed to by iptr. */ N /* Returns: the signed fractional part of value. */ N Nextern _ARMABI double pow(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double pow(double , double ); N /* computes x raised to the power of y. A domain error occurs if x is */ N /* zero and y is less than or equal to zero, or if x is negative and y */ N /* is not an integer, and -HUGE_VAL returned. A range error may occur. */ N /* Returns: the value of x raised to the power of y. */ N /* if underflow range error; 0 is returned. */ N /* if overflow range error; HUGE_VAL is returned. */ Nextern _ARMABI double sqrt(double /*x*/); Xextern __declspec(__nothrow) double sqrt(double ); N /* computes the non-negative square root of x. A domain error occurs */ N /* if the argument is negative, and -HUGE_VAL returned. */ N /* Returns: the value of the square root. */ N N#if defined(__TARGET_FPU_VFP_DOUBLE) && !defined(__TARGET_FPU_SOFTVFP) X#if 0L && !1L S _ARMABI_INLINE double _sqrt(double __x) { return __sqrt(__x); } N#else N _ARMABI_INLINE double _sqrt(double __x) { return sqrt(__x); } X __inline double _sqrt(double __x) { return sqrt(__x); } N#endif N#if defined(__TARGET_FPU_VFP_SINGLE) && !defined(__TARGET_FPU_SOFTVFP) X#if 0L && !1L S _ARMABI_INLINE float _sqrtf(float __x) { return __sqrtf(__x); } N#else N _ARMABI_INLINE float _sqrtf(float __x) { return (float)sqrt(__x); } X __inline float _sqrtf(float __x) { return (float)sqrt(__x); } N#endif N /* With VFP, _sqrt and _sqrtf should expand inline as the native VFP square root N * instructions. They will not behave like the C sqrt() function, because N * they will report unusual values as IEEE exceptions (in fpmodes which N * support IEEE exceptions) rather than in errno. These function names N * are not specified in any standard. */ N Nextern _ARMABI_PURE double ceil(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double ceil(double ); N /* computes the smallest integer not less than x. */ N /* Returns: the smallest integer not less than x, expressed as a double. */ Nextern _ARMABI_PURE double fabs(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double fabs(double ); N /* computes the absolute value of the floating-point number x. */ N /* Returns: the absolute value of x. */ N Nextern _ARMABI_PURE double floor(double /*d*/); Xextern __declspec(__nothrow) __attribute__((const)) double floor(double ); N /* computes the largest integer not greater than x. */ N /* Returns: the largest integer not greater than x, expressed as a double */ N Nextern _ARMABI double fmod(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double fmod(double , double ); N /* computes the floating-point remainder of x/y. */ N /* Returns: the value x - i * y, for some integer i such that, if y is */ N /* nonzero, the result has the same sign as x and magnitude */ N /* less than the magnitude of y. If y is zero, a domain error */ N /* occurs and -HUGE_VAL is returned. */ N N /* Additional Mathlib functions not defined by the ANSI standard. N * Not guaranteed, and not necessarily very well tested. N * C99 requires the user to include to use these functions N * declaring them "by hand" is not sufficient N * N * The above statement is not completely true now. Some of the above N * C99 functionality has been added as per the Standard, and (where N * necessary) old Mathlib functionality withdrawn/changed. Before N * including this header #define __ENABLE_MATHLIB_LEGACY if you want to N * re-enable the legacy functionality. N */ N N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 0L N Nextern _ARMABI double acosh(double /*x*/); Xextern __declspec(__nothrow) double acosh(double ); N /* N * Inverse cosh. EDOM if argument < 1.0 N */ Nextern _ARMABI double asinh(double /*x*/); Xextern __declspec(__nothrow) double asinh(double ); N /* N * Inverse sinh. N */ Nextern _ARMABI double atanh(double /*x*/); Xextern __declspec(__nothrow) double atanh(double ); N /* N * Inverse tanh. EDOM if |argument| > 1.0 N */ Nextern _ARMABI double cbrt(double /*x*/); Xextern __declspec(__nothrow) double cbrt(double ); N /* N * Cube root. N */ N_ARMABI_INLINE _ARMABI_PURE double copysign(double __x, double __y) X__inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) N /* N * Returns x with sign bit replaced by sign of y. N */ N{ N __HI(__x) = (__HI(__x) & 0x7fffffff) | (__HI(__y) & 0x80000000); X (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); N return __x; N} N_ARMABI_INLINE _ARMABI_PURE float copysignf(float __x, float __y) X__inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) N /* N * Returns x with sign bit replaced by sign of y. N */ N{ N __FLT(__x) = (__FLT(__x) & 0x7fffffff) | (__FLT(__y) & 0x80000000); X (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); N return __x; N} Nextern _ARMABI double erf(double /*x*/); Xextern __declspec(__nothrow) double erf(double ); N /* N * Error function. (2/sqrt(pi)) * integral from 0 to x of exp(-t*t) dt. N */ Nextern _ARMABI double erfc(double /*x*/); Xextern __declspec(__nothrow) double erfc(double ); N /* N * 1-erf(x). (More accurate than just coding 1-erf(x), for large x.) N */ Nextern _ARMABI double expm1(double /*x*/); Xextern __declspec(__nothrow) double expm1(double ); N /* N * exp(x)-1. (More accurate than just coding exp(x)-1, for small x.) N */ N#define fpclassify(x) \ N ((sizeof(x) == sizeof(float)) ? \ N __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) X#define fpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) N /* N * Classify a floating point number into one of the following values: N */ N#define FP_ZERO (0) N#define FP_SUBNORMAL (4) N#define FP_NORMAL (5) N#define FP_INFINITE (3) N#define FP_NAN (7) N N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) X#if 0L && 0L S/* S * Note that we'll never classify a number as FP_NAN, as all NaNs will S * be either FP_NANQ or FP_NANS S */ S# define FP_NANQ (8) S# define FP_NANS (9) N#endif N N Nextern _ARMABI double hypot(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double hypot(double , double ); N /* N * sqrt(x*x+y*y), ie the length of the vector (x,y) or the N * hypotenuse of a right triangle whose other two sides are x N * and y. Won't overflow unless the _answer_ is too big, even N * if the intermediate x*x+y*y is too big. N */ Nextern _ARMABI int ilogb(double /*x*/); Xextern __declspec(__nothrow) int ilogb(double ); N /* N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) N */ Nextern _ARMABI int ilogbf(float /*x*/); Xextern __declspec(__nothrow) int ilogbf(float ); N /* N * Like ilogb but takes a float N */ Nextern _ARMABI int ilogbl(long double /*x*/); Xextern __declspec(__nothrow) int ilogbl(long double ); N /* N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) N */ N#define FP_ILOGB0 (-0x7fffffff) /* ilogb(0) == -INT_MAX */ N#define FP_ILOGBNAN ( 0x80000000) /* ilogb(NAN) == INT_MIN */ N N#define isfinite(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isfinitef(x) \ N : __ARM_isfinite(x)) X#define isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x)) N /* N * Returns true if x is a finite number, size independent. N */ N N#define isgreater(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) \ N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) X#define isgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) N /* N * Returns true if x > y, throws no exceptions except on Signaling NaNs N * N * We want the C not set but the Z bit clear, V must be clear N */ N N#define isgreaterequal(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) \ N : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) X#define isgreaterequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) N /* N * Returns true if x >= y, throws no exceptions except on Signaling NaNs N * N * We just need to see if the C bit is set or not and ensure V clear N */ N N#define isinf(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isinff(x) \ N : __ARM_isinf(x)) X#define isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x)) N /* N * Returns true if x is an infinity, size independent. N */ N N#define isless(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) \ N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) X#define isless(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) N /* N * Returns true if x < y, throws no exceptions except on Signaling NaNs N * N * We're less than if N is set, V clear N */ N N#define islessequal(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) \ N : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) X#define islessequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) N /* N * Returns true if x <= y, throws no exceptions except on Signaling NaNs N * N * We're less than or equal if one of N or Z is set, V clear N */ N N#define islessgreater(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? __ARM_islessgreaterf((x), (y)) \ N : __ARM_islessgreater((x), (y))) X#define islessgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y))) N /* N * Returns true if x <> y, throws no exceptions except on Signaling NaNs N * Unfortunately this test is too complicated to do in a macro without N * evaluating x & y twice. Shame really... N */ N N#define isnan(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isnanf(x) \ N : __ARM_isnan(x)) X#define isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x)) N /* N * Returns TRUE if x is a NaN. N */ N N#define isnormal(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isnormalf(x) \ N : __ARM_isnormal(x)) X#define isnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x)) N /* N * Returns TRUE if x is a NaN. N */ N N#define isunordered(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) \ N : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) X#define isunordered(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) N /* N * Returns true if x ? y, throws no exceptions except on Signaling NaNs N * Unordered occurs if and only if the V bit is set N */ N Nextern _ARMABI double lgamma (double /*x*/); Xextern __declspec(__nothrow) double lgamma (double ); N /* N * The log of the absolute value of the gamma function of x. The sign N * of the gamma function of x is returned in the global `signgam'. N */ Nextern _ARMABI double log1p(double /*x*/); Xextern __declspec(__nothrow) double log1p(double ); N /* N * log(1+x). (More accurate than just coding log(1+x), for small x.) N */ Nextern _ARMABI double logb(double /*x*/); Xextern __declspec(__nothrow) double logb(double ); N /* N * Like ilogb but returns a double. N */ Nextern _ARMABI float logbf(float /*x*/); Xextern __declspec(__nothrow) float logbf(float ); N /* N * Like logb but takes and returns float N */ Nextern _ARMABI long double logbl(long double /*x*/); Xextern __declspec(__nothrow) long double logbl(long double ); N /* N * Like logb but takes and returns long double N */ Nextern _ARMABI double nextafter(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double nextafter(double , double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI float nextafterf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float nextafterf(float , float ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI long double nextafterl(long double /*x*/, long double /*y*/); Xextern __declspec(__nothrow) long double nextafterl(long double , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI double nexttoward(double /*x*/, long double /*y*/); Xextern __declspec(__nothrow) double nexttoward(double , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI float nexttowardf(float /*x*/, long double /*y*/); Xextern __declspec(__nothrow) float nexttowardf(float , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI long double nexttowardl(long double /*x*/, long double /*y*/); Xextern __declspec(__nothrow) long double nexttowardl(long double , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI double remainder(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double remainder(double , double ); N /* N * Returns the remainder of x by y, in the IEEE 754 sense. N */ Nextern _ARMABI_FPEXCEPT double rint(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double rint(double ); N /* N * Rounds x to an integer, in the IEEE 754 sense. N */ Nextern _ARMABI double scalbln(double /*x*/, long int /*n*/); Xextern __declspec(__nothrow) double scalbln(double , long int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI float scalblnf(float /*x*/, long int /*n*/); Xextern __declspec(__nothrow) float scalblnf(float , long int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI long double scalblnl(long double /*x*/, long int /*n*/); Xextern __declspec(__nothrow) long double scalblnl(long double , long int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI double scalbn(double /*x*/, int /*n*/); Xextern __declspec(__nothrow) double scalbn(double , int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI float scalbnf(float /*x*/, int /*n*/); Xextern __declspec(__nothrow) float scalbnf(float , int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI long double scalbnl(long double /*x*/, int /*n*/); Xextern __declspec(__nothrow) long double scalbnl(long double , int ); N /* N * Compute x times 2^n quickly. N */ N#define signbit(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_signbitf(x) \ N : __ARM_signbit(x)) X#define signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x)) N /* N * Returns the signbit of x, size independent macro N */ N#endif N N/* C99 float versions of functions. math.h has always reserved these N identifiers for this purpose (7.13.4). */ Nextern _ARMABI_PURE float _fabsf(float); /* old ARM name */ Xextern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); N_ARMABI_INLINE _ARMABI_PURE float fabsf(float __f) { return _fabsf(__f); } X__inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } Nextern _ARMABI float sinf(float /*x*/); Xextern __declspec(__nothrow) float sinf(float ); Nextern _ARMABI float cosf(float /*x*/); Xextern __declspec(__nothrow) float cosf(float ); Nextern _ARMABI float tanf(float /*x*/); Xextern __declspec(__nothrow) float tanf(float ); Nextern _ARMABI float acosf(float /*x*/); Xextern __declspec(__nothrow) float acosf(float ); Nextern _ARMABI float asinf(float /*x*/); Xextern __declspec(__nothrow) float asinf(float ); Nextern _ARMABI float atanf(float /*x*/); Xextern __declspec(__nothrow) float atanf(float ); Nextern _ARMABI float atan2f(float /*y*/, float /*x*/); Xextern __declspec(__nothrow) float atan2f(float , float ); Nextern _ARMABI float sinhf(float /*x*/); Xextern __declspec(__nothrow) float sinhf(float ); Nextern _ARMABI float coshf(float /*x*/); Xextern __declspec(__nothrow) float coshf(float ); Nextern _ARMABI float tanhf(float /*x*/); Xextern __declspec(__nothrow) float tanhf(float ); Nextern _ARMABI float expf(float /*x*/); Xextern __declspec(__nothrow) float expf(float ); Nextern _ARMABI float logf(float /*x*/); Xextern __declspec(__nothrow) float logf(float ); Nextern _ARMABI float log10f(float /*x*/); Xextern __declspec(__nothrow) float log10f(float ); Nextern _ARMABI float powf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float powf(float , float ); Nextern _ARMABI float sqrtf(float /*x*/); Xextern __declspec(__nothrow) float sqrtf(float ); Nextern _ARMABI float ldexpf(float /*x*/, int /*exp*/); Xextern __declspec(__nothrow) float ldexpf(float , int ); Nextern _ARMABI float frexpf(float /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); Nextern _ARMABI_PURE float ceilf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); Nextern _ARMABI_PURE float floorf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float floorf(float ); Nextern _ARMABI float fmodf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float fmodf(float , float ); Nextern _ARMABI float modff(float /*value*/, float * /*iptr*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); N N/* C99 long double versions of functions. */ N/* (also need to have 'using' declarations below) */ N#define _ARMDEFLD1(f) \ N _ARMABI long double f##l(long double /*x*/) X#define _ARMDEFLD1(f) _ARMABI long double f##l(long double ) N N#define _ARMDEFLD1P(f, T) \ N _ARMABI long double f##l(long double /*x*/, T /*p*/) X#define _ARMDEFLD1P(f, T) _ARMABI long double f##l(long double , T ) N N#define _ARMDEFLD2(f) \ N _ARMABI long double f##l(long double /*x*/, long double /*y*/) X#define _ARMDEFLD2(f) _ARMABI long double f##l(long double , long double ) N N/* N * Long double versions of C89 functions can be defined N * unconditionally, because C89 reserved these names in "future N * library directions". N */ N_ARMDEFLD1(acos); X__declspec(__nothrow) long double acosl(long double ); N_ARMDEFLD1(asin); X__declspec(__nothrow) long double asinl(long double ); N_ARMDEFLD1(atan); X__declspec(__nothrow) long double atanl(long double ); N_ARMDEFLD2(atan2); X__declspec(__nothrow) long double atan2l(long double , long double ); N_ARMDEFLD1(ceil); X__declspec(__nothrow) long double ceill(long double ); N_ARMDEFLD1(cos); X__declspec(__nothrow) long double cosl(long double ); N_ARMDEFLD1(cosh); X__declspec(__nothrow) long double coshl(long double ); N_ARMDEFLD1(exp); X__declspec(__nothrow) long double expl(long double ); N_ARMDEFLD1(fabs); X__declspec(__nothrow) long double fabsl(long double ); N_ARMDEFLD1(floor); X__declspec(__nothrow) long double floorl(long double ); N_ARMDEFLD2(fmod); X__declspec(__nothrow) long double fmodl(long double , long double ); N_ARMDEFLD1P(frexp, int*) __attribute__((__nonnull__(2))); X__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); N_ARMDEFLD1P(ldexp, int); X__declspec(__nothrow) long double ldexpl(long double , int ); N_ARMDEFLD1(log); X__declspec(__nothrow) long double logl(long double ); N_ARMDEFLD1(log10); X__declspec(__nothrow) long double log10l(long double ); N_ARMABI long double modfl(long double /*x*/, long double * /*p*/) __attribute__((__nonnull__(2))); X__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); N_ARMDEFLD2(pow); X__declspec(__nothrow) long double powl(long double , long double ); N_ARMDEFLD1(sin); X__declspec(__nothrow) long double sinl(long double ); N_ARMDEFLD1(sinh); X__declspec(__nothrow) long double sinhl(long double ); N_ARMDEFLD1(sqrt); X__declspec(__nothrow) long double sqrtl(long double ); N_ARMDEFLD1(tan); X__declspec(__nothrow) long double tanl(long double ); N_ARMDEFLD1(tanh); X__declspec(__nothrow) long double tanhl(long double ); N N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 0L N N/* N * C99 float and long double versions of extra-C89 functions. N */ Nextern _ARMABI float acoshf(float /*x*/); Xextern __declspec(__nothrow) float acoshf(float ); N_ARMDEFLD1(acosh); X__declspec(__nothrow) long double acoshl(long double ); Nextern _ARMABI float asinhf(float /*x*/); Xextern __declspec(__nothrow) float asinhf(float ); N_ARMDEFLD1(asinh); X__declspec(__nothrow) long double asinhl(long double ); Nextern _ARMABI float atanhf(float /*x*/); Xextern __declspec(__nothrow) float atanhf(float ); N_ARMDEFLD1(atanh); X__declspec(__nothrow) long double atanhl(long double ); N_ARMDEFLD2(copysign); X__declspec(__nothrow) long double copysignl(long double , long double ); Nextern _ARMABI float cbrtf(float /*x*/); Xextern __declspec(__nothrow) float cbrtf(float ); N_ARMDEFLD1(cbrt); X__declspec(__nothrow) long double cbrtl(long double ); Nextern _ARMABI float erff(float /*x*/); Xextern __declspec(__nothrow) float erff(float ); N_ARMDEFLD1(erf); X__declspec(__nothrow) long double erfl(long double ); Nextern _ARMABI float erfcf(float /*x*/); Xextern __declspec(__nothrow) float erfcf(float ); N_ARMDEFLD1(erfc); X__declspec(__nothrow) long double erfcl(long double ); Nextern _ARMABI float expm1f(float /*x*/); Xextern __declspec(__nothrow) float expm1f(float ); N_ARMDEFLD1(expm1); X__declspec(__nothrow) long double expm1l(long double ); Nextern _ARMABI float log1pf(float /*x*/); Xextern __declspec(__nothrow) float log1pf(float ); N_ARMDEFLD1(log1p); X__declspec(__nothrow) long double log1pl(long double ); Nextern _ARMABI float hypotf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float hypotf(float , float ); N_ARMDEFLD2(hypot); X__declspec(__nothrow) long double hypotl(long double , long double ); Nextern _ARMABI float lgammaf(float /*x*/); Xextern __declspec(__nothrow) float lgammaf(float ); N_ARMDEFLD1(lgamma); X__declspec(__nothrow) long double lgammal(long double ); Nextern _ARMABI float remainderf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float remainderf(float , float ); N_ARMDEFLD2(remainder); X__declspec(__nothrow) long double remainderl(long double , long double ); Nextern _ARMABI float rintf(float /*x*/); Xextern __declspec(__nothrow) float rintf(float ); N_ARMDEFLD1(rint); X__declspec(__nothrow) long double rintl(long double ); N N#endif N N#if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) X#if (0L && !0L) || 0L S/* S * Functions new in C99. S */ Sextern _ARMABI double exp2(double /*x*/); /* * 2.^x. */ Sextern _ARMABI float exp2f(float /*x*/); S_ARMDEFLD1(exp2); Sextern _ARMABI double fdim(double /*x*/, double /*y*/); Sextern _ARMABI float fdimf(float /*x*/, float /*y*/); S_ARMDEFLD2(fdim); S#ifdef __FP_FAST_FMA S#define FP_FAST_FMA S#endif S#ifdef __FP_FAST_FMAF S#define FP_FAST_FMAF S#endif S#ifdef __FP_FAST_FMAL S#define FP_FAST_FMAL S#endif Sextern _ARMABI double fma(double /*x*/, double /*y*/, double /*z*/); Sextern _ARMABI float fmaf(float /*x*/, float /*y*/, float /*z*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) \ S { return (long double)fma((double)__x, (double)__y, (double)__z); } X_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } S#endif Sextern _ARMABI_FPEXCEPT double fmax(double /*x*/, double /*y*/); Sextern _ARMABI_FPEXCEPT float fmaxf(float /*x*/, float /*y*/); S_ARMDEFLD2(fmax); Sextern _ARMABI_FPEXCEPT double fmin(double /*x*/, double /*y*/); Sextern _ARMABI_FPEXCEPT float fminf(float /*x*/, float /*y*/); S_ARMDEFLD2(fmin); Sextern _ARMABI double log2(double /*x*/); /* * log base 2 of x. */ Sextern _ARMABI float log2f(float /*x*/); S_ARMDEFLD1(log2); Sextern _ARMABI long lrint(double /*x*/); Sextern _ARMABI long lrintf(float /*x*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI long lrintl(long double __x) \ S { return lrint((double)__x); } X_ARMABI_INLINE _ARMABI long lrintl(long double __x) { return lrint((double)__x); } S#endif Sextern _ARMABI __LONGLONG llrint(double /*x*/); Sextern _ARMABI __LONGLONG llrintf(float /*x*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) \ S { return llrint((double)__x); } X_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) { return llrint((double)__x); } S#endif Sextern _ARMABI long lround(double /*x*/); Sextern _ARMABI long lroundf(float /*x*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI long lroundl(long double __x) \ S { return lround((double)__x); } X_ARMABI_INLINE _ARMABI long lroundl(long double __x) { return lround((double)__x); } S#endif Sextern _ARMABI __LONGLONG llround(double /*x*/); Sextern _ARMABI __LONGLONG llroundf(float /*x*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) \ S { return llround((double)__x); } X_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) { return llround((double)__x); } S#endif Sextern _ARMABI_PURE double nan(const char */*tagp*/); Sextern _ARMABI_PURE float nanf(const char */*tagp*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) \ S { return (long double)nan(__t); } X_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) { return (long double)nan(__t); } S#endif S#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) Sextern _ARMABI_PURE double nans(const char */*tagp*/); Sextern _ARMABI_PURE float nansf(const char */*tagp*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) \ S { return (long double)nans(__t); } X_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) { return (long double)nans(__t); } S#endif S#endif Sextern _ARMABI_FPEXCEPT double nearbyint(double /*x*/); Sextern _ARMABI_FPEXCEPT float nearbyintf(float /*x*/); S_ARMDEFLD1(nearbyint); Sextern double remquo(double /*x*/, double /*y*/, int */*quo*/); Sextern float remquof(float /*x*/, float /*y*/, int */*quo*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) \ S { return (long double)remquo((double)__x, (double)__y, __q); } X_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } S#endif Sextern _ARMABI_FPEXCEPT double round(double /*x*/); Sextern _ARMABI_FPEXCEPT float roundf(float /*x*/); S_ARMDEFLD1(round); Sextern _ARMABI double tgamma(double /*x*/); /* * The gamma function of x. */ Sextern _ARMABI float tgammaf(float /*x*/); S_ARMDEFLD1(tgamma); Sextern _ARMABI_FPEXCEPT double trunc(double /*x*/); Sextern _ARMABI_FPEXCEPT float truncf(float /*x*/); S_ARMDEFLD1(trunc); N#endif N N#undef _ARMDEFLD1 N#undef _ARMDEFLD1P N#undef _ARMDEFLD2 N N#if defined(__cplusplus) && ((!defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)) || defined(__ARMCOMPILER_LIBCXX)) X#if 0L && ((!0L || 0L) || 0L) S extern "C++" { S inline int (fpclassify)(double __x) { return fpclassify(__x); } S inline bool (isfinite)(double __x) { return isfinite(__x); } S inline bool (isgreater)(double __x, double __y) { return isgreater(__x, __y); } S inline bool (isgreaterequal)(double __x, double __y) { return isgreaterequal(__x, __y); } S inline bool (isinf)(double __x) { return isinf(__x); } S inline bool (isless)(double __x, double __y) { return isless(__x, __y); } S inline bool (islessequal)(double __x, double __y) { return islessequal(__x, __y); } S inline bool (islessgreater)(double __x, double __y) { return islessgreater(__x, __y); } S inline bool (isnan)(double __x) { return isnan(__x); } S inline bool (isnormal)(double __x) { return isnormal(__x); } S inline bool (isunordered)(double __x, double __y) { return isunordered(__x, __y); } S S } N#endif N N#if defined(__cplusplus) && !defined(__ARMCOMPILER_LIBCXX) X#if 0L && !0L S extern "C++" { S inline float abs(float __x) { return fabsf(__x); } S inline float acos(float __x) { return acosf(__x); } S inline float asin(float __x) { return asinf(__x); } S inline float atan(float __x) { return atanf(__x); } S inline float atan2(float __y, float __x) { return atan2f(__y,__x); } S inline float ceil(float __x) { return ceilf(__x); } S inline float cos(float __x) { return cosf(__x); } S inline float cosh(float __x) { return coshf(__x); } S inline float exp(float __x) { return expf(__x); } S inline float fabs(float __x) { return fabsf(__x); } S inline float floor(float __x) { return floorf(__x); } S inline float fmod(float __x, float __y) { return fmodf(__x, __y); } S float frexp(float __x, int* __exp) __attribute__((__nonnull__(2))); S inline float frexp(float __x, int* __exp) { return frexpf(__x, __exp); } S inline float ldexp(float __x, int __exp) { return ldexpf(__x, __exp);} S inline float log(float __x) { return logf(__x); } S inline float log10(float __x) { return log10f(__x); } S float modf(float __x, float* __iptr) __attribute__((__nonnull__(2))); S inline float modf(float __x, float* __iptr) { return modff(__x, __iptr); } S inline float pow(float __x, float __y) { return powf(__x,__y); } S inline float pow(float __x, int __y) { return powf(__x, (float)__y); } S inline float sin(float __x) { return sinf(__x); } S inline float sinh(float __x) { return sinhf(__x); } S inline float sqrt(float __x) { return sqrtf(__x); } S inline float _sqrt(float __x) { return _sqrtf(__x); } S inline float tan(float __x) { return tanf(__x); } S inline float tanh(float __x) { return tanhf(__x); } S S inline double abs(double __x) { return fabs(__x); } S inline double pow(double __x, int __y) S { return pow(__x, (double) __y); } S S#ifdef __HAVE_LONGDOUBLE S inline long double abs(long double __x) S { return (long double)fabsl(__x); } S inline long double acos(long double __x) S { return (long double)acosl(__x); } S inline long double asin(long double __x) S { return (long double)asinl(__x); } S inline long double atan(long double __x) S { return (long double)atanl(__x); } S inline long double atan2(long double __y, long double __x) S { return (long double)atan2l(__y, __x); } S inline long double ceil(long double __x) S { return (long double)ceill( __x); } S inline long double cos(long double __x) S { return (long double)cosl(__x); } S inline long double cosh(long double __x) S { return (long double)coshl(__x); } S inline long double exp(long double __x) S { return (long double)expl(__x); } S inline long double fabs(long double __x) S { return (long double)fabsl(__x); } S inline long double floor(long double __x) S { return (long double)floorl(__x); } S inline long double fmod(long double __x, long double __y) S { return (long double)fmodl(__x, __y); } S long double frexp(long double __x, int* __p) __attribute__((__nonnull__(2))); S inline long double frexp(long double __x, int* __p) S { return (long double)frexpl(__x, __p); } S inline long double ldexp(long double __x, int __exp) S { return (long double)ldexpl(__x, __exp); } S inline long double log(long double __x) S { return (long double)logl(__x); } S inline long double log10(long double __x) S { return (long double)log10l(__x); } S long double modf(long double __x, long double* __p) __attribute__((__nonnull__(2))); S inline long double modf(long double __x, long double* __p) S { return (long double)modfl(__x, __p); } S inline long double pow(long double __x, long double __y) S { return (long double)powl(__x, __y); } S inline long double pow(long double __x, int __y) S { return (long double)powl(__x, __y); } S inline long double sin(long double __x) S { return (long double)sinl(__x); } S inline long double sinh(long double __x) S { return (long double)sinhl(__x); } S inline long double sqrt(long double __x) S { return (long double)sqrtl(__x); } S inline long double _sqrt(long double __x) S { return (long double)_sqrt((double) __x); } S inline long double tan(long double __x) S { return (long double)tanl(__x); } S inline long double tanh(long double __x) S { return (long double)tanhl(__x); } S#endif S S#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) S inline float acosh(float __x) { return acoshf(__x); } S inline float asinh(float __x) { return asinhf(__x); } S inline float atanh(float __x) { return atanhf(__x); } S inline float cbrt(float __x) { return cbrtf(__x); } S inline float erf(float __x) { return erff(__x); } S inline float erfc(float __x) { return erfcf(__x); } S inline float expm1(float __x) { return expm1f(__x); } S inline float log1p(float __x) { return log1pf(__x); } S inline float hypot(float __x, float __y) { return hypotf(__x, __y); } S inline float lgamma(float __x) { return lgammaf(__x); } S inline float remainder(float __x, float __y) { return remainderf(__x, __y); } S inline float rint(float __x) { return rintf(__x); } S#endif S S#ifdef __USE_C99_MATH S inline float exp2(float __x) { return exp2f(__x); } S inline float fdim(float __x, float __y) { return fdimf(__x, __y); } S inline float fma(float __x, float __y, float __z) { return fmaf(__x, __y, __z); } S inline float fmax(float __x, float __y) { return fmaxf(__x, __y); } S inline float fmin(float __x, float __y) { return fminf(__x, __y); } S inline float log2(float __x) { return log2f(__x); } S inline _ARMABI long lrint(float __x) { return lrintf(__x); } S inline _ARMABI __LONGLONG llrint(float __x) { return llrintf(__x); } S inline _ARMABI long lround(float __x) { return lroundf(__x); } S inline _ARMABI __LONGLONG llround(float __x) { return llroundf(__x); } S inline _ARMABI_FPEXCEPT float nearbyint(float __x) { return nearbyintf(__x); } S inline float remquo(float __x, float __y, int *__q) { return remquof(__x, __y, __q); } S inline _ARMABI_FPEXCEPT float round(float __x) { return roundf(__x); } S inline float tgamma(float __x) { return tgammaf(__x); } S inline _ARMABI_FPEXCEPT float trunc(float __x) { return truncf(__x); } S S inline int (fpclassify)(float __x) { return fpclassify(__x); } S inline bool (isfinite)(float __x) { return isfinite(__x); } S inline bool (isgreater)(float __x, float __y) { return isgreater(__x, __y); } S inline bool (isgreaterequal)(float __x, float __y) { return isgreaterequal(__x, __y); } S inline bool (isinf)(float __x) { return isinf(__x); } S inline bool (isless)(float __x, float __y) { return isless(__x, __y); } S inline bool (islessequal)(float __x, float __y) { return islessequal(__x, __y); } S inline bool (islessgreater)(float __x, float __y) { return islessgreater(__x, __y); } S inline bool (isnan)(float __x) { return isnan(__x); } S inline bool (isnormal)(float __x) { return isnormal(__x); } S inline bool (isunordered)(float __x, float __y) { return isunordered(__x, __y); } S S#ifdef __HAVE_LONGDOUBLE S inline long double acosh(long double __x) { return acoshl(__x); } S inline long double asinh(long double __x) { return asinhl(__x); } S inline long double atanh(long double __x) { return atanhl(__x); } S inline long double cbrt(long double __x) { return cbrtl(__x); } S inline long double erf(long double __x) { return erfl(__x); } S inline long double erfc(long double __x) { return erfcl(__x); } S inline long double expm1(long double __x) { return expm1l(__x); } S inline long double log1p(long double __x) { return log1pl(__x); } S inline long double hypot(long double __x, long double __y) { return hypotl(__x, __y); } S inline long double lgamma(long double __x) { return lgammal(__x); } S inline long double remainder(long double __x, long double __y) { return remainderl(__x, __y); } S inline long double rint(long double __x) { return rintl(__x); } S inline long double exp2(long double __x) { return exp2l(__x); } S inline long double fdim(long double __x, long double __y) { return fdiml(__x, __y); } S inline long double fma(long double __x, long double __y, long double __z) { return fmal(__x, __y, __z); } S inline long double fmax(long double __x, long double __y) { return fmaxl(__x, __y); } S inline long double fmin(long double __x, long double __y) { return fminl(__x, __y); } S inline long double log2(long double __x) { return log2l(__x); } S inline _ARMABI long lrint(long double __x) { return lrintl(__x); } S inline _ARMABI __LONGLONG llrint(long double __x) { return llrintl(__x); } S inline _ARMABI long lround(long double __x) { return lroundl(__x); } S inline _ARMABI __LONGLONG llround(long double __x) { return llroundl(__x); } S inline _ARMABI_FPEXCEPT long double nearbyint(long double __x) { return nearbyintl(__x); } S inline long double remquo(long double __x, long double __y, int *__q) { return remquol(__x, __y, __q); } S inline _ARMABI_FPEXCEPT long double round(long double __x) { return roundl(__x); } S inline long double tgamma(long double __x) { return tgammal(__x); } S inline _ARMABI_FPEXCEPT long double trunc(long double __x) { return truncl(__x); } S inline int (fpclassify)(long double __x) { return fpclassify(__x); } S inline bool (isfinite)(long double __x) { return isfinite(__x); } S inline bool (isgreater)(long double __x, long double __y) { return isgreater(__x, __y); } S inline bool (isgreaterequal)(long double __x, long double __y) { return isgreaterequal(__x, __y); } S inline bool (isinf)(long double __x) { return isinf(__x); } S inline bool (isless)(long double __x, long double __y) { return isless(__x, __y); } S inline bool (islessequal)(long double __x, long double __y) { return islessequal(__x, __y); } S inline bool (islessgreater)(long double __x, long double __y) { return islessgreater(__x, __y); } S inline bool (isnan)(long double __x) { return isnan(__x); } S inline bool (isnormal)(long double __x) { return isnormal(__x); } S inline bool (isunordered)(long double __x, long double __y) { return isunordered(__x, __y); } S#endif S S#undef fpclassify S#undef isfinite S#undef isgreater S#undef isgreaterequal S#undef isinf S#undef isless S#undef islessequal S#undef islessgreater S#undef isnan S#undef isnormal S#undef isunordered S S#endif S S } N#endif N N #ifdef __cplusplus S } /* extern "C" */ S } /* namespace std */ N #endif N #endif /* __MATH_DECLS */ N N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L S #define _AEABI_PORTABLE N #endif N N #if defined(__cplusplus) && !defined(__MATH_NO_EXPORTS) X #if 0L && !0L S using ::std::__use_accurate_range_reduction; S #ifndef __ARMCOMPILER_LIBCXX S using ::std::abs; S #endif S using ::std::acos; S using ::std::asin; S using ::std::atan2; S using ::std::atan; S using ::std::ceil; S using ::std::cos; S using ::std::cosh; S using ::std::exp; S using ::std::fabs; S using ::std::floor; S using ::std::fmod; S using ::std::frexp; S using ::std::ldexp; S using ::std::log10; S using ::std::log; S using ::std::modf; S using ::std::pow; S using ::std::sin; S using ::std::sinh; S using ::std::sqrt; S using ::std::_sqrt; S using ::std::_sqrtf; S using ::std::tan; S using ::std::tanh; S using ::std::_fabsf; S /* C99 float and long double versions in already-C89-reserved namespace */ S using ::std::acosf; S using ::std::acosl; S using ::std::asinf; S using ::std::asinl; S using ::std::atan2f; S using ::std::atan2l; S using ::std::atanf; S using ::std::atanl; S using ::std::ceilf; S using ::std::ceill; S using ::std::cosf; S using ::std::coshf; S using ::std::coshl; S using ::std::cosl; S using ::std::expf; S using ::std::expl; S using ::std::fabsf; S using ::std::fabsl; S using ::std::floorf; S using ::std::floorl; S using ::std::fmodf; S using ::std::fmodl; S using ::std::frexpf; S using ::std::frexpl; S using ::std::ldexpf; S using ::std::ldexpl; S using ::std::log10f; S using ::std::log10l; S using ::std::logf; S using ::std::logl; S using ::std::modff; S using ::std::modfl; S using ::std::powf; S using ::std::powl; S using ::std::sinf; S using ::std::sinhf; S using ::std::sinhl; S using ::std::sinl; S using ::std::sqrtf; S using ::std::sqrtl; S using ::std::tanf; S using ::std::tanhf; S using ::std::tanhl; S using ::std::tanl; S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) S /* C99 additions which for historical reasons appear in non-strict mode */ S using ::std::acosh; S using ::std::asinh; S using ::std::atanh; S using ::std::cbrt; S using ::std::copysign; S using ::std::copysignf; S using ::std::erf; S using ::std::erfc; S using ::std::expm1; S using ::std::hypot; S using ::std::ilogb; S using ::std::ilogbf; S using ::std::ilogbl; S using ::std::lgamma; S using ::std::log1p; S using ::std::logb; S using ::std::logbf; S using ::std::logbl; S using ::std::nextafter; S using ::std::nextafterf; S using ::std::nextafterl; S using ::std::nexttoward; S using ::std::nexttowardf; S using ::std::nexttowardl; S using ::std::remainder; S using ::std::rint; S using ::std::scalbln; S using ::std::scalblnf; S using ::std::scalblnl; S using ::std::scalbn; S using ::std::scalbnf; S using ::std::scalbnl; S using ::std::math_errhandling; S using ::std::acoshf; S using ::std::acoshl; S using ::std::asinhf; S using ::std::asinhl; S using ::std::atanhf; S using ::std::atanhl; S using ::std::copysignl; S using ::std::cbrtf; S using ::std::cbrtl; S using ::std::erff; S using ::std::erfl; S using ::std::erfcf; S using ::std::erfcl; S using ::std::expm1f; S using ::std::expm1l; S using ::std::log1pf; S using ::std::log1pl; S using ::std::hypotf; S using ::std::hypotl; S using ::std::lgammaf; S using ::std::lgammal; S using ::std::remainderf; S using ::std::remainderl; S using ::std::rintf; S using ::std::rintl; S /* New in C99. */ S using ::std::float_t; S using ::std::double_t; S #endif S #if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) S /* Functions new in C99. */ S using ::std::exp2; S using ::std::exp2f; S using ::std::exp2l; S using ::std::fdim; S using ::std::fdimf; S using ::std::fdiml; S using ::std::fma; S using ::std::fmaf; S#ifdef __HAVE_LONGDOUBLE S using ::std::fmal; S#endif S using ::std::fmax; S using ::std::fmaxf; S using ::std::fmaxl; S using ::std::fmin; S using ::std::fminf; S using ::std::fminl; S using ::std::log2; S using ::std::log2f; S using ::std::log2l; S using ::std::lrint; S using ::std::lrintf; S#ifdef __HAVE_LONGDOUBLE S using ::std::lrintl; S#endif S using ::std::llrint; S using ::std::llrintf; S#ifdef __HAVE_LONGDOUBLE S using ::std::llrintl; S#endif S using ::std::lround; S using ::std::lroundf; S#ifdef __HAVE_LONGDOUBLE S using ::std::lroundl; S#endif S using ::std::llround; S using ::std::llroundf; S#ifdef __HAVE_LONGDOUBLE S using ::std::llroundl; S#endif S using ::std::nan; S using ::std::nanf; S#ifdef __HAVE_LONGDOUBLE S using ::std::nanl; S#endif S using ::std::nearbyint; S using ::std::nearbyintf; S using ::std::nearbyintl; S using ::std::remquo; S using ::std::remquof; S#ifdef __HAVE_LONGDOUBLE S using ::std::remquol; S#endif S using ::std::round; S using ::std::roundf; S using ::std::roundl; S using ::std::tgamma; S using ::std::tgammaf; S using ::std::tgammal; S using ::std::trunc; S using ::std::truncf; S using ::std::truncl; S #endif S S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) S using ::std::fpclassify; S using ::std::isfinite; S using ::std::isgreater; S using ::std::isgreaterequal; S using ::std::isinf; S using ::std::isless; S using ::std::islessequal; S using ::std::islessgreater; S using ::std::isnan; S using ::std::isnormal; S using ::std::isunordered; S #endif N #endif N N#undef __LONGLONG N N#endif /* __math_h */ N N/* end of math.h */ L 12 "..\user\src\swj.c" 2 N N#include "datahand.h" L 1 "..\user\inc\datahand.h" 1 N#ifndef DATAHAND_H N#define DATAHAND_H N N#include "def.h" L 1 "..\user\inc\def.h" 1 N#ifndef DEF_H N#define DEF_H N N N#define u8 unsigned char N#define u16 unsigned short N#define u32 unsigned int N N#endif N L 5 "..\user\inc\datahand.h" 2 N N/*充放电保护状态位*/ Nextern u8 Chg_Flag; //充电保护 1保护 Xextern unsigned char Chg_Flag; Nextern u8 Out_flag; //放电保护 1保护 Xextern unsigned char Out_flag; Nextern u8 Chg_Lock; //充电保护 互锁 Xextern unsigned char Chg_Lock; Nextern u8 Out_Lock; //放电保护 互锁 Xextern unsigned char Out_Lock; N N/*全局变量*/ Nextern u8 Cell_Soc; //电池SOC Xextern unsigned char Cell_Soc; Nextern float IntVolume; //初始化容量 Nextern float OutSOC_xs; //放电SOC系数 Nextern float ChgSOC_xs; //充电SOC系数 Nextern float SOH_xs; //SOH系数 Nextern float Q_hs; //实际容量和标称容量换算 Nextern u16 Cell_usnum; //电池循环次数 Xextern unsigned short Cell_usnum; Nextern u32 Cell_Outrl; //电池循环放电总容量 Xextern unsigned int Cell_Outrl; Nextern u8 Off_lint; //掉线故障次数 Xextern unsigned char Off_lint; Nextern u8 Out_Dea; //放电失效次数 Xextern unsigned char Out_Dea; Nextern u8 Chg_Dea; //充电失效次数 Xextern unsigned char Chg_Dea; Nextern u8 Cell_Tmp; //电池超温次数 Xextern unsigned char Cell_Tmp; Nextern u8 Pow_Tmp; //功率板超温次数 Xextern unsigned char Pow_Tmp; Nextern u8 Chg_Moshit; //充电Mos管故障次数 Xextern unsigned char Chg_Moshit; Nextern u8 Out_Moshit; //放电MOs管故障次数 Xextern unsigned char Out_Moshit; Nextern float Curr_Res; //电阻校准值 N///////////////////////////////////////////////////////////////////////// N Nextern u8 ChgMos_bit_last; Xextern unsigned char ChgMos_bit_last; Nextern u8 ChgMos_bit; //充电MOS管切换标识 Xextern unsigned char ChgMos_bit; Nextern u8 OutMos_bit_last; Xextern unsigned char OutMos_bit_last; Nextern u8 OutMos_bit; //放电MOS管切换标识 Xextern unsigned char OutMos_bit; N Nextern u16 Out_curr; //放电电流 单位：0.01A Xextern unsigned short Out_curr; Nextern u8 SOCinit; Xextern unsigned char SOCinit; Nextern u8 SOCinit_bit; Xextern unsigned char SOCinit_bit; N N/*故障标识*/ Nextern u16 Hitsturt; Xextern unsigned short Hitsturt; Nextern u8 HitFlag; Xextern unsigned char HitFlag; N N/*低功耗相关标识*/ Nextern u8 dgpow_bit; //1开启低功耗 Xextern unsigned char dgpow_bit; Nextern u8 dgpow_Time_1; //低功耗开启时一小时读取一次数据 Xextern unsigned char dgpow_Time_1; Nextern u8 dgpow_count; //低功耗延时计数 Xextern unsigned char dgpow_count; Nextern u8 dgPowL_TC; //退出标识 Xextern unsigned char dgPowL_TC; N N/*变量声明*/ N/*数据来源*/ Nextern unsigned char Data_Source; //0空闲 1上位机 2蓝牙 Nextern unsigned char Bluetooth_bit; //蓝牙标志 Nextern unsigned short MCU_Count; //接收MCU数目索引 N N/*电压ADC值*/ Nextern unsigned short sub_val_adc; Nextern unsigned char Ledvol_bit; N N/*鸣器提示音标识位*/ Nextern unsigned char Beep_Flag; N N/*函数声明*/ N/* N*函数名：MCUdata_Hand N*函数参数：wu N*函数返回值：wu N*函数功能：接收MCU数据进行分类上传 N*/ N Nextern void MCUdata_Hand(void); N N#endif N N N L 14 "..\user\src\swj.c" 2 N#include "gpioinit.h" L 1 "..\user\inc\gpioinit.h" 1 N#ifndef _GPIOINIT_H_ N#define _GPIOINIT_H_ N N Nextern void base_gpio(void); N N#endif L 15 "..\user\src\swj.c" 2 N#include "perconfig.h" L 1 "..\user\inc\perconfig.h" 1 N#ifndef _PERCONFIG_H_ N#define _PERCONFIG_H_ N#include "stm32f10x.h" N Nextern u8 GPS_bit; //GPS标识 Xextern unsigned char GPS_bit; Nextern u8 Blu_bit; //蓝牙标识 Xextern unsigned char Blu_bit; N N N/*函数功能：外设初始化函数*/ Nextern void allBaseInit(void); N N/*串口3初始化配置_115200*/ Nextern void USART1_Config_115200(void); //115200bps@22.1184MHz N N/*串口3初始化初始化_9600*/ Nextern void USART1_Config_9600(void); //9600bps@22.1184MHz N N N#endif L 16 "..\user\src\swj.c" 2 N#include "delay.h" L 1 "..\user\inc\delay.h" 1 N#ifndef _DELAY_H_ N#define _DELAY_H_ N N#include "stm32f10x.h" N Nvoid Delay_init(void); //滴答定时器初始化 Nvoid Delay_us(u32 nus); //us级别延时 Xvoid Delay_us(unsigned int nus); Nvoid Delay_ms(u32 nms); //ms级别延时 Xvoid Delay_ms(unsigned int nms); Nvoid delay_ms(u16 time); //毫秒级别简单延时 Xvoid delay_ms(unsigned short time); N#endif L 17 "..\user\src\swj.c" 2 N#include "basetime.h" L 1 "..\user\inc\basetime.h" 1 N#ifndef _BASETIME_H_ N#define _BASETIME_H_ N N#include "stdBool.h" N#include "stm32f10x.h" N Nextern unsigned long int beginTime2; N Ntypedef struct N{ N unsigned long int beginTime2; /*开始时间*/ N unsigned long int timeOut; /*超时计数*/ N N bool isRun; X _Bool isRun; N}Timer; N Nextern Timer time_1000; N/*************************define**********************/ N#define FStopTimer(x) x->isRun = false; N N//等待毫秒级别延时 Nextern void waitTimeMS(unsigned long int time); N N//开始一个定时器 Nextern void startTimeMs(Timer* timer,unsigned long int time); N N//定时器计数是否到达 Nbool isTimerOut(Timer* timer); X_Bool isTimerOut(Timer* timer); N N N#endif L 18 "..\user\src\swj.c" 2 N#include "usart.h" L 1 "..\user\inc\usart.h" 1 N#ifndef _USART_H_ N#define _USART_H_ N N N/*发送函数实现串口1发送一个字节*/ Nextern void Send_byte_usart1(char date); N N/*发送函数实现串口2发送一个字节*/ Nextern void Send_byte_usart2(char date); N N/*********************************************************************/ N/*上位机-字符串、数组发送*/ N/*发送一个字符串*/ Nextern void Send_string_GPS(unsigned char *sl); N/*发送一个数组*/ Nextern void Send_TString_GPS(unsigned char* sll,unsigned short num); N N/********************************************************************************************************/ N/*保护板-字符串、数组发送*/ N/*发送一个字符串*/ Nextern void Send_string_BMS_TT(unsigned char *sl); N/*发送一个数组*/ Nextern void Send_TString_BMS_TT(unsigned char* sll,unsigned short num); N N N#endif N L 19 "..\user\src\swj.c" 2 N#include "iobind.h" L 1 "..\user\inc\iobind.h" 1 N#ifndef _IOBIND_H_ N#define _IOBIND_H_ N#include "button/iobutton.h" N#include "stm32f10x_conf.h" N N/*反馈脚*/ Nextern IoButtonType Check[]; N N/*IIC 时钟端口*/ Nextern IOControlInfo SDA_1; Nextern IOControlInfo SCL_1; Nextern IOControlInfo SDA_2; Nextern IOControlInfo SCL_2; N N/*从芯片隔离控制端*/ Nextern IOControlInfo En5V_I2C; N N/*MOS管脚控制端*/ Nextern IOControlInfo DS_M; Nextern IOControlInfo CH_M; N N/*初始化拉高控制端*/ Nextern IOControlInfo MKX; N N/*485控制端*/ Nextern IOControlInfo En_485; N N N/* 输入检测标志位 -状态位*/ N#define FLAGSIZE 4 Nextern bool All_Flag[FLAGSIZE]; Xextern _Bool All_Flag[4]; N N#define Key_p_Flag All_Flag[0] //GPS\BUl选择管脚 N#define GPS_Tt_Flag All_Flag[1] //GPS\铁塔选择管脚 N#define DS_MCU_Flag All_Flag[2] //放电控制反馈脚 N#define CH_MCU_Flag All_Flag[3] //充电控制反馈脚 N N/*输入检测*/ N#define Check_SIZE 4 N#define MCU_AI0 Check[0].io N#define MCU_AI1 Check[1].io N#define MCU_AI2 Check[2].io N#define MCU_AI3 Check[3].io N N#define IONUMBER_AI0 0 N#define IONUMBER_AI1 1 N#define IONUMBER_AI2 2 N#define IONUMBER_AI3 3 N N N/*******************************************/ N/*io口寄存器关联变量初始化*/ Nextern void InitAllIO(void); N N/*输入检测初始化*/ Nextern void InputStructAssignment(void); N N//每运行一次该函数，按钮增加一次单位次数 Nextern void FButtonTasks(void); N N#endif N L 20 "..\user\src\swj.c" 2 N#include "joinbind.h" L 1 "..\user\inc\joinbind.h" 1 N#ifndef _JOINBIND_H_ N#define _JOINBIND_H_ N N#define ALLTIMERSIZE 6 N#define TIMERNUMBER1 0 N#define TIMERNUMBER2 1 N#define TIMERNUMBER3 2 N#define TIMERNUMBER4 3 N#define TIMERNUMBER5 4 N#define TIMERNUMBER6 5 N N#define timer0 ALLtimers[TIMERNUMBER1] N#define timer1 ALLtimers[TIMERNUMBER2] N#define timer2 ALLtimers[TIMERNUMBER3] N#define timer3 ALLtimers[TIMERNUMBER4] N#define timer4 ALLtimers[TIMERNUMBER5] N#define timer5 ALLtimers[TIMERNUMBER6] N N N/****************************函数*******************************/ N/*定时回调函数-5ms*/ Nextern void TimeOut0_5(void* sender); N N/*定时回调函数-100ms*/ Nextern void TimeOut1_100(void* sender); N N/*定时回调函数-180ms*/ Nextern void TimeOut2_180(void* sender); N N/*定时回调函数-250ms*/ Nextern void TimeOut3_250(void* sender); N N/*定时回调函数-500ms*/ Nextern void TimeOut4_500(void* sender); N N/*定时回调函数-1000ms*/ Nextern void TimeOut5_1000(void* sender); N N/*定时器回调函数绑定初始化*/ Nextern void timerbind(void); N N#endif N N L 21 "..\user\src\swj.c" 2 N N#include "Stmtype.h" L 1 "..\user\inc\Stmtype.h" 1 N#ifndef __STM_TYPE_H N#define __STM_TYPE_H N N#include N Ntypedef unsigned char U8; Ntypedef unsigned short U16; Ntypedef unsigned int U32; Ntypedef signed char S8; Ntypedef signed short S16; Ntypedef signed int S32; Ntypedef bool BOOL; Xtypedef _Bool BOOL; N N N N#endif L 23 "..\user\src\swj.c" 2 N#include "def.h" N#include "swj.h" L 1 "..\user\inc\swj.h" 1 N/* N*串口2发送 N*波特率 115200 N*高字节先发送原则 N N*V20200325_更新一些描述信息，更改0xA10改为0xD2,专用充电器开关指令 N*V20200325_确定传送的数据波特率115200 N*V20200329_更新优化指令表，重新定义数据标识码 N N*通信使用2G的GPRS中TCP传输，4G中GAT1，SOCKET接口方式，RS2332TTL串口 N N*充电均衡---- 充电状态下进行放电均衡---/ N*/ N N#ifndef __SWJ_H N#define __SWJ_H N N#include "Stmtype.h" N#include "def.h" N#include "stm32f10x.h" N N/*****************************************宏定义*************************************************/ N#define S_DATA_LEN 400 //数据缓存长度 N N/*起始帧数据*/ N#define START_FRAME 0x4e57 //起始标识 N#define END_FRAME 0x68 //结束标识 N N/*除去数据域固定长度*/ N#define S_GD_LEN 0x14 //除数据域固定长度为20 N N/*命令字说明*/ N#define ACTIVACE_ORDE 0x01 //激活指令 N#define WRITE_ORDE 0x02 //写指令 N#define REV_ORDE 0x03 //读指令 N#define CONF_ORDE 0x04 //控制选择指令_只写 N#define PASS_ORDE 0x05 //对密码指令 N#define REV_ALLORDE 0x06 //读全部指令 N#define WRI_ALLORDE 0x07 //写全部指令 N#define REV_309EEPROM 0x08 //读309EEPROM全部数据 N#define WRI_309EEPROM 0x09 //写309EEPROM全部数据 N#define REV_309RAM 0x0A //读309RAM全部数据 N#define STOP_309_WR 0x0B //防止309读写干扰指令 N N N/*309EEPROM数据标识符*/ N#define DATA_EEPROM_SCONF1 0x00 //系统配置寄存器1 RW N#define DATA_EEPROM_SCONF2 0x01 //系统配置寄存器2 RW N#define DATA_EEPROM_SCONF3 0x02 //系统配置寄存器2 RW N#define DATA_EEPROM_OV 0x03 //异常高压保护电压 RW N#define DATA_EEPROM_OVTIME 0x04 //异常高压保护延时 RW N#define DATA_EEPROM_GOV 0x05 //过压保护电压 RW N#define DATA_EEPROM_GOVTIME 0x06 //过压保护延时 RW N#define DATA_EEPROM_GOVSF 0x07 //过压保护释放电压 RW N#define DATA_EEPROM_BALV 0x08 //平衡开启电压设置寄存器 RW N#define DATA_EEPROM_QOVSF 0x09 //欠压保护释放电压 RW N#define DATA_EEPROM_QOV 0x0A //欠压保护电压 RW N#define DATA_EEPROM_QOVTIME 0x0B //欠压保护延时 RW N#define DATA_EEPROM_YCVOL 0x0C //预充电开启电压 RW N#define DATA_EEPROM_DVOL 0x0D //低压禁止充电电压 RW N#define DATA_EEPROM_COJCVOL 0x0E //充放电状态监测电压 RW N#define DATA_EEPROM_OCD1_VOL 0x0F //放电过流1保护电压 RW N#define DATA_EEPROM_OCD1_TIME 0x10 //放电过流1保护延时 RW N#define DATA_EEPROM_OCD2_VOL 0x11 //放电过流2保护电压 RW N#define DATA_EEPROM_OCD2_TIME 0x12 //放电过流2保护延时 RW N#define DATA_EEPROM_DLUVOL 0x13 //短路保护电压 RW N#define DATA_EEPROM_DLUVOL_TIME 0x14 //短路保护延时 RW N#define DATA_EEPROM_CHG_CURR 0x15 //充电过流保护电压 RW N#define DATA_EEPROM_CHG_TIME 0x16 //充电过流保护延时 RW N#define DATA_EEPROM_CHG_MOS 0x17 //充电MOS管开启延时 RW N#define DATA_EEProM_GCURRZ 0x18 //过流自恢复延时 RW N#define DATA_EEPROM_OTC 0x19 //充电高温保护 RW N#define DATA_EEPROM_OTCR 0x1A //充电高温保护释放 RW N#define DATA_EEPROM_UTC 0x1B //充电低温保护 RW N#define DATA_EEPROM_UTCR 0x1C //充电低温保护释放 RW N#define DATA_EEPROM_OTD 0x1D //放电高温保护 RW N#define DATA_EEPROM_OTDR 0x1E //放电高温保护释放 RW N#define DATA_EEPROM_UTD 0x1F //放电低温保护 RW N#define DATA_EEPROM_UTDR 0x20 //放电低温保护释放 RW N#define DATA_EEPROM_NTCX 0x21 //热敏电阻选择 RW N#define DATA_EEPROM_JPGN 0x22 //晶片功能 RW N#define DATA_EEPROM_CELLTYPE 0x23 //电池类型 RW N#define DATA_EEPROM_CELLNUM 0x24 //电池节数 RW N N N/*309RAM数据标识符*/ N#define DATA_MTP_CONF 0x30 //系统配置寄存器 R N#define DATA_MTP_BALANCEH 0x31 //平衡寄存器 R N#define DATA_MTP_BSTATUS1 0x32 //系统状态寄存器 1 R N#define DATA_MTP_BSTATUS2 0x33 //系统状态寄存器 2 R N#define DATA_MTP_BSTATUS3 0x34 //系统状态寄存器 3 R N#define DATA_MTP_TEMP1 0x35 //T1温度寄存器 R N#define DATA_MTP_TEMP2 0x36 //T2温度 R N#define DATA_MTP_TEMP3 0x37 //T3温度 R N#define DATA_MTP_CUR 0x38 //电流寄存器 R N#define DATA_MTP_CELL1 0x39 //电芯电压1 R N#define DATA_MTP_CELL2 0x3A //电芯电压2 R N#define DATA_MTP_CELL3 0x3B //电芯电压3 R N#define DATA_MTP_CELL4 0x3C //电芯电压4 R N#define DATA_MTP_CELL5 0x3D //电芯电压5 R N#define DATA_MTP_CELL6 0x3E //电芯电压6 R N#define DATA_MTP_CELL7 0x3F //电芯电压7 R N#define DATA_MTP_CELL8 0x40 //电芯电压8 R N#define DATA_MTP_CELL9 0x41 //电芯电压9 R N#define DATA_MTP_CELL10 0x42 //电芯电压10 R N#define DATA_MTP_CELL11 0x43 //电芯电压11 R N#define DATA_MTP_CELL12 0x44 //电芯电压12 R N#define DATA_MTP_CELL13 0x45 //电芯电压13 R N#define DATA_MTP_CELL14 0x46 //电芯电压14 R N#define DATA_MTP_CELL15 0x47 //电芯电压15 R N#define DATA_MTP_CELL16 0x48 //电芯电压16 R N#define DATA_MTP_CELL17 0x49 //电芯电压17 R N#define DATA_MTP_CELL18 0x4A //电芯电压18 R N#define DATA_MTP_CELL19 0x4B //电芯电压19 R N#define DATA_MTP_CELL20 0x4C //电芯电压20 R N#define DATA_MTP_CELL21 0x4D //电芯电压21 R N#define DATA_MTP_CELL22 0x4E //电芯电压22 R N#define DATA_MTP_CELL23 0x4F //电芯电压23 R N#define DATA_MTP_CELL24 0x50 //电芯电压24 R N#define DATA_MTP_ADC2 0x51 //CADC电流寄存器 N#define DATA_MTP_BFLAG1 0x52 //系统标志寄存器 1 R N#define DATA_MTP_BFLAG2 0x53 //系统标志寄存器 2 R N#define DATA_MTP_RSTSTAT 0x54 //看门狗寄存器 N N#define DATA_MTP_TEMP1_NUM 0x55 //T1温度 R N#define DATA_MTP_TEMP2_NUM 0x56 //T2温度 R N#define DATA_MTP_TEMP3_NUM 0x57 //T3温度 R N#define DATA_MTP_CELL1_NUM 0x58 //电芯电压1 R N#define DATA_MTP_CELL2_NUM 0x59 //电芯电压2 R N#define DATA_MTP_CELL3_NUM 0x5A //电芯电压3 R N#define DATA_MTP_CELL4_NUM 0x5B //电芯电压4 R N#define DATA_MTP_CELL5_NUM 0x5C //电芯电压5 R N#define DATA_MTP_CELL6_NUM 0x5D //电芯电压6 R N#define DATA_MTP_CELL7_NUM 0x5E //电芯电压7 R N#define DATA_MTP_CELL8_NUM 0x5F //电芯电压8 R N#define DATA_MTP_CELL9_NUM 0x60 //电芯电压9 R N#define DATA_MTP_CELL10_NUM 0x61 //电芯电压10 R N#define DATA_MTP_CELL11_NUM 0x62 //电芯电压11 R N#define DATA_MTP_CELL12_NUM 0x63 //电芯电压12 R N#define DATA_MTP_CELL13_NUM 0x64 //电芯电压13 R N#define DATA_MTP_CELL14_NUM 0x65 //电芯电压14 R N#define DATA_MTP_CELL15_NUM 0x66 //电芯电压15 R N#define DATA_MTP_CELL16_NUM 0x67 //电芯电压16 R N#define DATA_MTP_CELL17_NUM 0x68 //电芯电压17 R N#define DATA_MTP_CELL18_NUM 0x69 //电芯电压18 R N#define DATA_MTP_CELL19_NUM 0x6A //电芯电压19 R N#define DATA_MTP_CELL20_NUM 0x6B //电芯电压20 R N#define DATA_MTP_CELL21_NUM 0x6C //电芯电压21 R N#define DATA_MTP_CELL22_NUM 0x6D //电芯电压22 R N#define DATA_MTP_CELL23_NUM 0x6E //电芯电压23 R N#define DATA_MTP_CELL24_NUM 0x6F //电芯电压24 R N#define DATA_MTP_ZVOL 0x70 //总电压 R N#define DATA_MTP_VOLVC 0x71 //压差 R N N#define RANJIANYINJIAN 0xD0 //软件版硬件版选择 W N#define CONF_309NUM 0xD1 //309控制芯片数目 W N N#define PASS_YAZ 0xE0 //密码验证 N#define XIUG_PASS_CHU 0xE1 //修改密码 输入初始化密码 N#define XIUG_PASS_NEW 0xE2 //修改密码 输入新密码 N N N/*309地址*/ N/*SH367309 EEPROM寄存器数据*/ N#define EEPROM_SCONF1 0x00 //系统配置寄存器1 RW N#define EEPROM_SCONF2 0x01 //系统配置EEPROM寄存器2 RW N#define EEPROM_OVH_OVL 0x02 //过充电保护延时设置 RW N#define EEPROM_OVRH_OVRL 0x04 //过放电保护延时设置 RW N#define EEPROM_UV 0x06 //过放电保护电压设置 RW N#define EEPROM_UVR 0x07 //过放电恢复电压设置 RW N#define EEPROM_BALV 0x08 //平衡开启电压设置寄存器 RW N#define EEPrOM_PREV 0x09 //预充电电压设置寄存器 RW N#define EEPROM_LOV 0x0a //低电压禁止充电电压设置寄存器 RW N#define EEPROM_PFV 0x0b //二次过充电保护电压设置寄存器 RW N#define EEPROM_OCD1V_OCD1T 0x0c //放电过流1设置寄存器 RW N#define EEPROM_OCD2V_OCD2T 0x0d //放电过流2设置寄存器 RW N#define EEPROM_SCV_SCT 0x0e //短路保护设置寄存器 RW N#define EEPROM_OCCV_OCCT 0x0f //充电过流设置寄存器 RW N#define EEPROM_MOST 0x10 //电流保护自动恢复/二次过充电保护延时设置寄存器 RW N#define EEPROM_OTC 0x11 //充电高温保护设置寄存器 RW N#define EEPROM_OTCR 0x12 //充电高温保护释放设置寄存器 RW N#define EEPROM_UTC 0x13 //充电低温保护设置寄存器 RW N#define EEPROM_UTCR 0x14 //充电低温保护释放设置寄存器 RW N#define EEPROM_OTD 0x15 //放电高温保护设置寄存器 RW N#define EEPROM_OTDR 0x16 //放电高温保护释放设置寄存器 RW N#define EEPROM_UTD 0x17 //放电低温保护设置寄存器 RW N#define EEPROM_UTDR 0x18 //放电低温保护释放设置寄存器 RW N#define EEPROM_TR 0x19 //温度内部参考电阻系数寄存器 R N N N N/*SH367309 ARM寄存器地址*/ N#define MTP_CONF 0x40 //系统配置寄存器 RW N#define MTP_BALANCEH 0x41 //平衡寄存器 16_9 RW N#define MTP_BALANCEL 0x42 //平衡寄存器 8_1 RW N#define MTP_BSTATUS1 0x43 //系统状态寄存器 1 R N#define MTP_BSTATUS2 0x44 //系统状态寄存器 2 R N#define MTP_BSTATUS3 0x45 //系统状态寄存器 3 R N#define MTP_TEMP1 0x46 //T1温度寄存器 R N#define MTP_TEMP2 0x48 //T2温度 R N#define MTP_TEMP3 0x4A //T3温度 R N#define MTP_CUR 0x4C //电流寄存器 R N#define MTP_CELL1 0x4E //电芯电压1 R N#define MTP_CELL2 0x50 //电芯电压2 R N#define MTP_CELL3 0x52 //电芯电压3 R N#define MTP_CELL4 0x54 //电芯电压4 R N#define MTP_CELL5 0x56 //电芯电压5 R N#define MTP_CELL6 0x58 //电芯电压6 R N#define MTP_CELL7 0x5A //电芯电压7 R N#define MTP_CELL8 0x5C //电芯电压8 R N#define MTP_CELL9 0x5E //电芯电压9 R N#define MTP_CELL10 0x60 //电芯电压10 R N#define MTP_CELL11 0x62 //电芯电压11 R N#define MTP_CELL12 0x64 //电芯电压12 R N#define MTP_CELL13 0x66 //电芯电压13 R N#define MTP_CELL14 0x68 //电芯电压14 R N#define MTP_CELL15 0x6A //电芯电压15 R N#define MTP_CELL16 0x6C //电芯电压16 R N#define MTP_ADC2 0x6E //CADC电流寄存器 N#define MTP_BFLAG1 0x70 //系统标志寄存器 1 R N#define MTP_BFLAG2 0x71 //系统标志寄存器 2 R N#define MTP_RSTSTAT 0x72 //看门狗寄存器 N N N/*接收GPS的数据缓存*/ Ntypedef struct N{ N u8 gps_Rev_start; //接收一帧数据完成标志位 X unsigned char gps_Rev_start; N u8 gps_Rev_buf[355]; //数据缓存 X unsigned char gps_Rev_buf[355]; N u16 gps_Rev_buftmp; //数据索引 X unsigned short gps_Rev_buftmp; N}GPS_Buf; N N N/*帧格式*/ Ntypedef struct N{ N u16 start_frame; //起始帧 0x4e 0x57 X unsigned short start_frame; N u16 Len_frame; //帧长度 除去起始符所有数据字节 X unsigned short Len_frame; N u32 Bms_number; //终端号 FF FF FF FF 最高8位管理备用号 低24位是终端号（最高一字节是保留默认00，低三字节是唯一的ID） X unsigned int Bms_number; N u8 orde; //命令字 X unsigned char orde; N u8 farm_sor; //帧来源 0:BMS,1:蓝牙,2:GPS,3:PC上位机 X unsigned char farm_sor; N u8 Type; //传输类型 0:读数据,1:应答帧,2:主动上传 X unsigned char Type; N u8 s_data[S_DATA_LEN]; //数据域 BMS设置数据标识码 X unsigned char s_data[400]; N u32 Recnumber; //记录号 高一字节是随机码无意义(保留加密用)，低三字节是记录序号 X unsigned int Recnumber; N u8 end_signs; //结束标识 0x68 X unsigned char end_signs; N u32 check_sum; //校验和 累加和 X unsigned int check_sum; N}Data_frame; N N N//////////////////////////////////// N/*309数据*/ N/*EEPROM寄存器读写数据*/ Ntypedef struct N{ N N /*********************************系统配置*****************************************/ N union N { N u16 datas; X unsigned short datas; N struct N { N u16 bit0 :1; //0位：预充电控制 1:ON 0:OFF X unsigned short bit0 :1; N u16 bit1 :1; //1位：MOS管恢复控制 1:ON 0:OFF X unsigned short bit1 :1; N u16 bit2 :1; //2位：过流MOS管控制 1:ON 0:OFF X unsigned short bit2 :1; N u16 bit3 :1; //3位：MCU控制平衡 1:ON 0:OFF X unsigned short bit3 :1; N u16 bit4 :1; //4位：禁止异常高压 1:ON 0:OFF X unsigned short bit4 :1; N u16 bit5 :1; //5位：禁止低压充电 1:ON 0:OFF X unsigned short bit5 :1; N u16 bit6 :1; //6位：过流保护定时恢复 1:ON 0:OFF X unsigned short bit6 :1; N u16 bit7 :1; //7位：锁定负载 1:ON 0:OFF X unsigned short bit7 :1; N u16 bit8 :1; //8位：欠压开关CHG 1:ON 0:OFF X unsigned short bit8 :1; N u16 bit9 :1; // X unsigned short bit9 :1; N u16 bit10 :1;// X unsigned short bit10 :1; N u16 bit11 :1;// X unsigned short bit11 :1; N u16 bit12 :1;// X unsigned short bit12 :1; N u16 bit13 :1;// X unsigned short bit13 :1; N u16 bit14 :1;// X unsigned short bit14 :1; N u16 bit15 :1;// X unsigned short bit15 :1; N }bits; N }Sconf1; //读写系统配置寄存器1 N //////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 LDRT1_0 :2; //负载释放延时设置控制位 X unsigned char LDRT1_0 :2; N /* N LDRT[1:0] = 00: 负载释放延时 = 100mS N LDRT[1:0] = 01: 负载释放延时 = 500mS N LDRT[1:0] = 10: 负载释放延时 = 1000mS N LDRT[1:0] = 11: 贺头叛邮?= 2000mS N */ N u8 res :6; //保留 X unsigned char res :6; N }bits; N }Sconf2; //读写系统配置寄存器2 N //////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 CTLC1_0 :2; //CTL管脚功能设置控制位 X unsigned char CTLC1_0 :2; N /* N CTLC[1:0]=00：充放电和预充电MOSFET由内部逻辑控制， CTL管脚输入无效 N CTLC[1:0]=01： 控制充电和预充电MOSFET。 CTL输入VL-CTL电平时强制关闭充电和 N 预充电MOSFET； CTL输入VH-CTL电平时充电和预充电MOSFET由内 N 部逻辑控制 N CTLC[1:0]=10： 控制放电MOSFET。 CTL输入VL-CTL电平时强制关闭放电MOSFET； N CTL输入VH-CTL电平时，放电MOSFET由内部逻辑控制 N CTLC[1:0]=11： 控制充放电和预充电MOSFET。 CTL输入VL-CTL电平时强制关闭充放 N 电和预充电MOSFET； CTL输入VH-CTL电平时，充放电和预充电 N MOSFET哨部逻辑控制 N */ N u8 res :6; //保留 X unsigned char res :6; N }bits; N }Sconf3; //读写系统配置寄存器3 N N N /*********************************电压保护*****************************************/ N u16 ycGVol; //读写异常高压保护电压 单位：MV X unsigned short ycGVol; N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 time :2; X unsigned char time :2; N /* N [1:0]位： N [1:0] = 00：异常高压保护延时=8S N [1:0] = 01：异常高压保护延时= 16S N [1:0] = 10：异常高压保护延时= 32S N [1:0] = 11：异常高压保护延时= 64S N */ N u8 res :6; //保留 X unsigned char res :6; N }bits; N }ycGVolTime; //读写异常高压保护延时 N N N u16 GVol; //读写过压保护电压 单位：MV X unsigned short GVol; N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 time :4; X unsigned char time :4; N /* N OVT[3:0] = 0000： 过充电保护延时 = 100mS N OVT[3:0] = 0001： 过充电保护延时 = 200mS N OVT[3:0] = 0010： 过充电保护延时 = 300mS N OVT[3:0] = 0011： 过充电保护延时 = 400mS N OVT[3:0] = 0100： 过充电保护延时 = 600mS N OVT[3:0] = 0101： 过充电保护延时 = 800mS N OVT[3:0] = 0110： 过充电保护延时 = 1S N OVT[3:0] = 0111： 过充电保护延时 = 2S N OVT[3:0] = 1000： 过充电保护延时 = 3S N OVT[3:0] = 1001： 过充电保护延时 = 4S N OVT[3:0] = 1010： 过充电保护延时 = 6S N OVT[3:0] = 1011： 过充电保护延时 = 8S N OVT[3:0] = 1100： 过充电保护延时 = 10S N OVT[3:0] = 1101： 过充电保护延时 = 20S N OVT[3:0] = 1110： 过充电保护延时 = 30S N OVT[3:0] = 1111： 过充电保护延时 = 40S N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }GVolTime; //读写高压保护延时 单位：MV N N u16 GVolSf;//读写过压保护释放电压 单位：MV X unsigned short GVolSf; N N u16 Balv; //读写平衡开启电压 单位：MV X unsigned short Balv; N N u16 QVolSf; //读写欠压保护释放电压 单位：MV X unsigned short QVolSf; N N u16 QVol; //读写欠压保护电压 单位：MV X unsigned short QVol; N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 time :4; X unsigned char time :4; N /* N UVT[3:0] = 0000： 过放电保护延时 = 100mS N UVT[3:0] = 0001： 过放电保护延时 = 200mS N UVT[3:0] = 0010： 过放电保护延时 = 300mS N UVT[3:0] = 0011： 过放电保护延时 = 400mS N UVT[3:0] = 0100： 过放电保护延时 = 600mS N UVT[3:0] = 0101： 过放电保护延时 = 800mS N UVT[3:0] = 0110： 过放电保护延时 = 1S N UVT[3:0] = 0111： 过放电保护延时 = 2S N UVT[3:0] = 1000： 过放电保护延时 = 3S N UVT[3:0] = 1001： 过放电保护延时 = 4S N UVT[3:0] = 1010： 过放电保护延时 = 6S N UVT[3:0] = 1011： 过放电保护延时 = 8S N UVT[3:0] = 1100： 过放电保护延时 = 10S N UVT[3:0] = 1101： 过放电保护延时 = 20S N UVT[3:0] = 1110： 过放电保护延时 = 30S N UVT[3:0] = 1111： 过放电保护延时 = 40S N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }QVolTime; //读写欠压保护延时 单位：MV N N u16 Prev; //读写预充电电压 预充电电压， 单位：MV X unsigned short Prev; N N u16 Lovstop; //读写低电压禁止充电电压 低电压禁止充电电压， 单位：MV X unsigned short Lovstop; N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 jcvol :2; X unsigned char jcvol :2; N /* N CHS [1:0] = 00： 充放电状态检测电压 = 200uV N CHS [1:0] = 01： 充放电状态检测电压 = 500uV N CHS [1:0] = 10： 充放电状态检测电压 = 1000uV N CHS [1:0] = 11： 充放电状态检测电压 = 2000uV N */ N u8 res :6; //保留 X unsigned char res :6; N }bits; N }ChgOut_Vol; //读写充放电检测电压 N N /*********************************电流保护*****************************************/ N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCD1V3_0 :4; //放电过流1保护电压 X unsigned char OCD1V3_0 :4; N /* N OCD1V[3:0] = 0000：放电过流1保护电压 = 20mV N OCD1V[3:0] = 0001：放电过流1保护电压 = 30mV N OCD1V[3:0] = 0010：放电过流1保护电压 = 40mV N OCD1V[3:0] = 0011：放电过流1保护电压 = 50mV N OCD1V[3:0] = 0100： 放电过流1保护电压 = 60mV N OCD1V[3:0] = 0101：放电过流1保护电压 = 70mV N OCD1V[3:0] = 0110：放电过流1保护电压 = 80mV N OCD1V[3:0] = 0111：放电过流1保护电压 = 90mV N OCD1V[3:0] = 1000：放电过流1保护电压 = 100mV N OCD1V[3:0] = 1001：放电过流1保护电压 = 110mV N OCD1V[3:0] = 1010：放电过流1保护电压 = 120mV N OCD1V[3:0] = 1011：放电过流1保护电压 = 130mV N OCD1V[3:0] = 1100：放电过流1保护电压 = 140mV N OCD1V[3:0] = 1101：放电过流1保护电压 = 160mV N OCD1V[3:0] = 1110：放电过流1保护电压 = 180mV N OCD1V[3:0] = 1111悍诺绻?保护电压 = 200mV N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Ocd1V_ocd1t; //读写放电过流1保护电压 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 CD1T3_0 :4; //放电过流1保护延时 X unsigned char CD1T3_0 :4; N /* N OCD1T[3:0] = 0000：放电过流1保护延时 = 50mS N OCD1T[3:0] = 0001：放电过流1保护延时 = 100mS N OCD1T[3:0] = 0010：放电过流1保护延时 = 200mS N OCD1T[3:0] = 0011：放电过流1保护延时 = 400mS N OCD1T[3:0] = 0100：放电过流1保护延时 = 600mS N OCD1T[3:0] = 0101：放电过流1保护延时 = 800mS N OCD1T[3:0] = 0110：放电过流1保护延时 = 1S N OCD1T[3:0] = 0111：放电过流1保护延时 = 2S N OCD1T[3:0] = 1000：放电过流1保护延时 = 4S N OCD1T[3:0] = 1001：放电过流1保护延时 = 6S N OCD1T[3:0] = 1010：放电过流1保护延时 = 8S N OCD1T[3:0] = 1011：放电过流1保护延时 = 10S N OCD1T[3:0] = 1100：放电过流1保护延时 = 15S N OCD1T[3:0] = 1101：放电过流1保护延时 = 20S N OCD1T[3:0] = 1110：放电过流1保护延时 = 30S N OCD1T[3:0] = 1111：放电过流1保护延时 = 40S N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Ocd1V_ocd1t_Time; //读写放电过流1保护延时 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCD2V3_0 :4; //放电过流2保护电压 X unsigned char OCD2V3_0 :4; N /* N OCD2V[3:0] = 0000：放电过流2保护电压 = 30mV N OCD2V[3:0] = 0001：放电过流2保护电压 = 40mV N OCD2V[3:0] = 0010：放电过流2保护电压 = 50mV N OCD2V[3:0] = 0011：放电过流2保护电压 = 60mV N OCD2V[3:0] = 0100：放电过流2保护电压 = 70mV N OCD2V[3:0] = 0101：放电过流2保护电压 = 80mV N OCD2V[3:0] = 0110：放电过流2保护电压 = 90mV N OCD2V[3:0] = 0111：放电过流2保护电压 = 100mV N OCD2V[3:0] = 1000：放电过流2保护电压 = 120mV N OCD2V[3:0] = 1001：放电过流2保护电压 = 140mV N OCD2V[3:0] = 1010：放电过流2保护电压 = 160mV N OCD2V[3:0] = 1011：放电过流2保护电压 = 180mV N OCD2V[3:0] = 1100：放电过流2保护电压 = 200mV N OCD2V[3:0] = 1101：放电过流2保护电压 = 300mV N OCD2V[3:0] = 1110：放电过流2保护电压 = 400mV N OCD2V[3:0] = 1111：放电过流2保护电压 = 500mV N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Ocd2V_ocd2t; //读写放电过流2保护电压 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCD2T3_0 :4; //放电过流2保护电压 X unsigned char OCD2T3_0 :4; N /* N OCD2T[3:0] = 0000：放电过流2保护延时 = 10mS N OCD2T[3:0] = 0001：放电过流2保护延时 = 20mS N OCD2T[3:0] = 0010：放电过流2保护延时 = 40mS N OCD2T[3:0] = 0011：放电过流2保护延时 = 60mS N OCD2T[3:0] = 0100：放电过流2保护延时 = 80mS N OCD2T[3:0] = 0101：放电过流2保护延时 = 100mS N OCD2T[3:0] = 0110：放电过流2保护延时 = 200mS N OCD2T[3:0] = 0111：放电过流2保护延时 = 400mS N OCD2T[3:0] = 1000：放电过流2保护延时 = 600mS N OCD2T[3:0] = 1001：放电过流2保护延时 = 800mS N OCD2T[3:0] = 1010：放电过流2保护延时 = 1S N OCD2T[3:0] = 1011：放电过流2保护延时 = 2S N OCD2T[3:0] = 1100：放电过流2保护延时 = 4S N OCD2T[3:0] = 1101：放电过流2保护延时 = 8S N OCD2T[3:0] = 1110：放电过流2保护延时 = 10S N OCD2T[3:0] = 1111悍诺绻?保护延时 = 20S N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Ocd2V_ocd2t_Time; //读写放电过流2保护延时 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 SCV_3_0 :4; //短路保护保护电压 X unsigned char SCV_3_0 :4; N /* N SCV[3:0] = 0000：短路保护电压 = 50mV N SCV[3:0] = 0001：短路保护电压 = 80mV N SCV[3:0] = 0010：短路保护电压 = 110mV N SCV[3:0] = 0011：短路保护电压 = 140mV N SCV[3:0] = 0100：短路保护电压 = 170mV N SCV[3:0] = 0101：短路保护电压 = 200mV N SCV[3:0] = 0110：短路保护电压 = 230mV N SCV[3:0] = 0111：短路保护电压 = 260mV N SCV[3:0] = 1000：短路保护电压 = 290mV N SCV[3:0] = 1001：短路保护电压 = 320mV N SCV[3:0] = 1010：短路保护电压 = 350mV N SCV[3:0] = 1011：短路保护电压 = 400mV N SCV[3:0] = 1100：短路保护电压 = 500mV N SCV[3:0] = 1101：短路保护电压 = 600mV N SCV[3:0] = 1110：短路保护电压 = 800mV N SCV[3:0] = 1111：短路保护电压 = 1000mV N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Scv_sct; //读写短路保护电压 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 SCV_3_0 :4; //短路保护保护电压 X unsigned char SCV_3_0 :4; N /* N SCT[3:0] = 0000：短路保护延时 = 0uS N SCT[3:0] = 0001：短路保护延时 = 64uS N SCT[3:0] = 0010：短路保护延时 = 128uS N SCT[3:0] = 0011：短路保护延时 = 192uS N SCT[3:0] = 0100：短路保护延时 = 256uS N SCT[3:0] = 0101：短路保护延时 = 320uS N SCT[3:0] = 0110：短路保护延时 = 384uS N SCT[3:0] = 0111：短路保护延时 = 448uS N SCT[3:0] = 1000：短路保护延时 = 512uS N SCT[3:0] = 1001：短路保护延时 = 576uS N SCT[3:0] = 1010：短路保护延时 = 640uS N SCT[3:0] = 1011：短路保护延时 = 704uS N SCT[3:0] = 1100：短路保护延时 = 768uS N SCT[3:0] = 1101：短路保护延时 = 832uS N SCT[3:0] = 1110：短路保护延时 = 896uS N SCT[3:0] = 1111：短路保护延时 = 960uS N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Scv_sct_Time; //读写短路保护延时 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCCV3_0 :4; //充电过流保护电压 X unsigned char OCCV3_0 :4; N /* N OCCV[3:0] = 0000：充电过流保护电压 = 20mV N OCCV[3:0] = 0001：充电过流保护电压 = 30mV N OCCV[3:0] = 0010：充电过流保护电压 = 40mV N OCCV[3:0] = 0011：充电过流保护电压 = 50mV N OCCV[3:0] = 0100：充电过流保护电压 = 60mV N OCCV[3:0] = 0101：充电过流保护电压 = 70mV N OCCV[3:0] = 0110：充电过流保护电压 = 80mV N OCCV[3:0] = 0111：充电过流保护电压 = 90mV N OCCV[3:0] = 1000：充电过流保护电压 = 100mV N OCCV[3:0] = 1001：充电过流保护电压 = 110mV N OCCV[3:0] = 1010：充电过流保护电压 = 120mV N OCCV[3:0] = 1011：充电过流保护电压 = 130mV N OCCV[3:0] = 1100：充电过流保护电压 = 140mV N OCCV[3:0] = 1101：充电过流保护电压 = 160mV N OCCV[3:0] = 1110：充电过流保护电压 = 180mV N OCCV[3:0] = 1111：充电过流保护电压 = 200mV N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Occv_occt; //读写充电过流保护电压 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCCT3_0 :4; //充电过流保护延时 X unsigned char OCCT3_0 :4; N /* N OCCT[3:0] = 0000：充电过流保护延时 = 10mS N OCCT[3:0] = 0001：充电过流保护延时 = 20mS N OCCT[3:0] = 0010：充电过流保护延时 = 40mS N OCCT[3:0] = 0011：充电过流保护延时 = 60mS N OCCT[3:0] = 0100：充电过流保护延时 = 80mS N OCCT[3:0] = 0101：充电过流保护延时 = 100mS N OCCT[3:0] = 0110：充电过流保护延时 = 200mS N OCCT[3:0] = 0111：充电过流保护延时 = 400mS N OCCT[3:0] = 1000：充电过流保护延时 = 600mS N OCCT[3:0] = 1001：充电过流保护延时 = 800mS N OCCT[3:0] = 1010：充电过流保护延时 = 1S N OCCT[3:0] = 1011：充电过流保护延时 = 2S N OCCT[3:0] = 1100：充电过流保护延时 = 4S N OCCT[3:0] = 1101：充电过流保护延时 = 8S N OCCT[3:0] = 1110：充电过流保护延时 = 10S N OCCT[3:0] = 1111：充电过流保护延时 = 20S N */ N u8 res :4; //保留 X unsigned char res :4; N }bits; N }Occv_occt_Time; //读写充电过流保护延时 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 MOST1_0 :2; //充放电MOSFET开启延时 X unsigned char MOST1_0 :2; N /* N MOST[1:0] = 00： 充放电MOSFET开启延时 = 64uS N MOST[1:0] = 01： 充放电MOSFET开启延时 = 128uS N MOST[1:0] = 10： 充放电MOSFET开启延时 = 256uS N MOST[1:0] = 11： 充放电MOSFET开启延时 = 512uS N */ N u8 res :6; //保留 X unsigned char res :6; N }bits; N }ChgMos_Time; //读写充电MOS管开启延时 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCRT1_0 :2; //充放电过流自恢复延时 X unsigned char OCRT1_0 :2; N /* N OCRT[1:0] = 00：充放电过流自动恢复延时 = 8S N OCRT[1:0] = 01：充放电过流自动恢复延时 = 16S N OCRT[1:0] = 10：充放电过流自动恢复延时 = 32S N OCRT[1:0] = 11：充放电过流自动恢复延时 = 64S N */ N u8 res :6; //保留 X unsigned char res :6; N }bits; N }GCurr_Time; //读写过流自恢复延时 N N N N /*********************************温度保护*****************************************/ N char Otc; //读写充电高温保护 充电高温保护阈值 N N char Otcr; //读写充电高温保护释放 充电高温保护释放阈值 N N char Utc; //读写充电低温保护 充电低温保护阈值 N N char Utcr; //读写充电低温保护释放 充电低温保护释放阈值 N N char Otd; //读写放电高温保护 放电高温保护阈值 N N char Otdr; //读写放电高温保护释放 放电高温保护释放阈值 N N char Utd; //读写放电低温保护 放电低温保护阈值 N N char Utdr; //读写放电低温保护释放 放电低温保护释放阈值 N N u8 NTC_x; //热敏电阻选择 X unsigned char NTC_x; N N /*********************************产品信息*****************************************/ N u8 cpdata; //产品信息 X unsigned char cpdata; N u8 cell_type; //电池类型 0：磷酸铁锂，1：三元，2：钛酸锂 X unsigned char cell_type; N u8 Cell_Num; //电池节数 X unsigned char Cell_Num; N N}EEPROMWriRevdata; N N///////////////////////////////////////////////////////////////////////////////////////////////// N///////////////////////////////////////////////////////////////////////////////////////////////// N/*309RAM数据只读*/ Ntypedef struct N{ N union N { N u8 datas; X unsigned char datas; N struct N { N u8 IDLE :1; //IDLE设置控制位 0： SH367309不进入IDLE状态 1： SH367309将进入IDLE状态，唤醒后硬件自动清零 X unsigned char IDLE :1; N u8 SLEEP :1; //SLEEP设置控制位 0： SH367309不进入SLEEP状态 1： SH367309将进入SLEEP状态，唤醒后硬件自动清零 X unsigned char SLEEP :1; N u8 ENWDT :1; //看门狗设置控制位 0： SH367309关闭看门狗模块 1： SH367309开启看门狗模块 X unsigned char ENWDT :1; N u8 CADCON :1; //CADC设置控制位 0： SH367309关闭CADC 1： SH367309开启CADC进行电流采集 X unsigned char CADCON :1; N u8 CHGMOS :1; //充电MOSFET控制位 0： 充电MOSFET关闭 1：充电MOSFET由硬件保护模块决定 X unsigned char CHGMOS :1; N u8 DSGMOS :1; //放电MOSFET控制位 0：放电MOSFET关闭 1：放电MOSFET由硬件保护模块决定 X unsigned char DSGMOS :1; N u8 PCHMOS :1; //预充电MOSFET控制位 0：预充电MOSFET关闭 1：预充电MOSFET由硬件保护模块决定 X unsigned char PCHMOS :1; N u8 OCRC :1; //过流保护控制位 过流保护状态清除需在OCRC位连续写： 0-1-0 X unsigned char OCRC :1; N }bits; N }Conf; //系统配置 N N union N { N U32 datas; N struct N { N U32 CB1 :1; //0：关闭CellN平衡回路 1：开启CellN平衡回路 N U32 CB2 :1; N U32 CB3 :1; N U32 CB4 :1; N U32 CB5 :1; N U32 CB6 :1; N U32 CB7 :1; N U32 CB8 :1; N U32 CB9 :1; N U32 CB10 :1; N U32 CB11 :1; N U32 CB12 :1; N U32 CB13 :1; N U32 CB14 :1; N U32 CB15 :1; N U32 CB16 :1; N U32 CB17 :1; //17：关闭CellN平衡回路 1：开启CellN平衡回路 N U32 CB18 :1; N U32 CB19 :1; N U32 CB20 :1; N U32 CB21 :1; N U32 CB22 :1; N U32 CB23 :1; N U32 CB24 :1; N U32 CB25 :1; N U32 CB26 :1; N U32 CB27 :1; N U32 CB28 :1; N U32 CB29 :1; N U32 CB30 :1; N U32 CB31 :1; N U32 CB32 :1; N }bits; N }Balanceh_l; //控制电池阻的平衡回路 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OV :1; // 过压保护状态位 1：发生过压保护 0：未发生过压保护 X unsigned char OV :1; N u8 UV :1; // 欠压保护状态位 1：发生欠压保护 0：未发生欠压保护 X unsigned char UV :1; N u8 OCD1 :1; // 放电过流1保护状态位 1：发生放电过流1保护 0：未发生放电过流1保护 X unsigned char OCD1 :1; N u8 OCD2 :1; // 放电过流2保护状态位 1：发生放电过流2保护 0：未发生放电过流2保护 X unsigned char OCD2 :1; N u8 OCC :1; // 充电过流保护状态位 1：发生充电过流保护 0： 未发生充电过流保护 X unsigned char OCC :1; N u8 SC :1; // 短路保护状态位 1：发生短路保护 0： 未发生短路保护 X unsigned char SC :1; N u8 PF :1; // 二次过充电保护状态位 1：发生二次过充电保护 0：未发生二次过充电保护 X unsigned char PF :1; N u8 WDT :1; // 看门狗状态位 1：看门狗溢出 0：看门狗正常 X unsigned char WDT :1; N }bits; N }Bstrtus1;//系统状态1寄存器 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 UTC :1; //充电低温保护状态位 1：发生充电低温保护 0：未发生充电低温保护 X unsigned char UTC :1; N u8 OTC :1; //充电高温保护状态位 1：发生充电高温保护 0：未发生充电高温保护 X unsigned char OTC :1; N u8 UTD :1; //放电低温保护状态位 1：发生放电低温保护 0：未发生放电低温保护 X unsigned char UTD :1; N u8 OTD :1; //放电高温保护状态位 1：发生放电高温保护 0：未发生放电高温保护 X unsigned char OTD :1; N u8 Ren :4; //保留 X unsigned char Ren :4; N }bits; N }Bstrtus2;//系统状态2寄存器 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 DSG_FET :1; //放电MOSFET开关状态位 1：放电MOSFET开启 0：放电MOSFET关闭 X unsigned char DSG_FET :1; N u8 CHG_FET :1; //充电MOSFET开关状态位 1：充电MOSFET开启 0：充电MOSFET关闭 X unsigned char CHG_FET :1; N u8 PCHG_FET :1; //预充电MOSFET开关状态位 1：预充电MOSFET开启 0：预充电MOSFET关闭 X unsigned char PCHG_FET :1; N u8 L0V :1; //低电压禁止充电状态位 1：发生低电压禁止充电 0：未发生低电压禁止充电 X unsigned char L0V :1; N u8 EEPR_WR :1; //EEPROM写操作状态位 1： EEPROM写操作错误 0： EEPROM写操作正确 X unsigned char EEPR_WR :1; N u8 Ren :1; //保留 X unsigned char Ren :1; N u8 DSGING :1; //放电状态位 1：放电状态 0：非放电状态 X unsigned char DSGING :1; N u8 CHGING :1; //充电状态位 1：充电状态 0：非充电状态 X unsigned char CHGING :1; N }bits; N }Bstrtus3;//系统状态3寄存器 N N u16 TEMP1h_l; //T1温度 X unsigned short TEMP1h_l; N N u16 TEMP2h_l; //T2温度 X unsigned short TEMP2h_l; N N u16 TEMP3h_l; //T3温度 X unsigned short TEMP3h_l; N N u16 Curh_l; //CUR15 X unsigned short Curh_l; N N union N { N u16 cellvol[24]; X unsigned short cellvol[24]; N N struct N { N u16 cell1_vol; //电芯电压1 X unsigned short cell1_vol; N N u16 cell2_vol; //电芯电压2 X unsigned short cell2_vol; N N u16 cell3_vol; //电芯电压3 X unsigned short cell3_vol; N N u16 cell4_vol; //电芯电压4 X unsigned short cell4_vol; N N u16 cell5_vol; //电芯电压5 X unsigned short cell5_vol; N N u16 cell6_vol; //电芯电压6 X unsigned short cell6_vol; N N u16 cell7_vol; //电芯电压7 X unsigned short cell7_vol; N N u16 cell8_vol; //电芯电压8 X unsigned short cell8_vol; N N u16 cell9_vol; //电芯电压9 X unsigned short cell9_vol; N N u16 cell10_vol; //电芯电压10 X unsigned short cell10_vol; N N u16 cell11_vol; //电芯电压11 X unsigned short cell11_vol; N N u16 cell12_vol; //电芯电压12 X unsigned short cell12_vol; N N u16 cell13_vol; //电芯电压13 X unsigned short cell13_vol; N N u16 cell14_vol; //电芯电压14 X unsigned short cell14_vol; N N u16 cell15_vol; //电芯电压15 X unsigned short cell15_vol; N N u16 cell16_vol; //电芯电压16 X unsigned short cell16_vol; N N u16 cell17_vol; //电芯电压17 X unsigned short cell17_vol; N N u16 cell18_vol; //电芯电压18 X unsigned short cell18_vol; N N u16 cell19_vol; //电芯电压19 X unsigned short cell19_vol; N N u16 cell20_vol; //电芯电压20 X unsigned short cell20_vol; N N u16 cell21_vol; //电芯电压21 X unsigned short cell21_vol; N N u16 cell22_vol; //电芯电压22 X unsigned short cell22_vol; N N u16 cell23_vol; //电芯电压23 X unsigned short cell23_vol; N N u16 cell24_vol; //电芯电压24 X unsigned short cell24_vol; N }cellbits; N }Cell; N N u16 CADcdh_l; //电流 X unsigned short CADcdh_l; N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OV_FLG :1; //过压保护标志位 1：发生过过压保护 0：未发生过过压保护 X unsigned char OV_FLG :1; N u8 UV_FLG :1; //欠压保护标志位 1：发生过欠压保护 0：未发生过欠压保护 X unsigned char UV_FLG :1; N u8 OCD_FLG :1; //放电过流保护标志位 1：发生过放电过流保护 0：未发生过放电过流保护 X unsigned char OCD_FLG :1; N u8 LOAD_FLG :1; //LDO3过流标志位 1：发生过过流 0：未发生过过流 X unsigned char LOAD_FLG :1; N u8 OCC_FLG :1; //充电过流保护标志位 1：发生过充电过流保护 0：未发生过充电过流保护 X unsigned char OCC_FLG :1; N u8 SC_FLG :1; //短路保护标志位 1：发生过短路保护 0：未发生过短路保护 X unsigned char SC_FLG :1; N u8 PF_FLG :1; //二次过充电保护标志位 1：发生过二次过充电保护 0：未发生过二次过充电保护 X unsigned char PF_FLG :1; N u8 WDT_FLG :1; //看门狗标志位 1：发生过看门狗溢出 0： 未发生过看门狗溢出 X unsigned char WDT_FLG :1; N }bits; N }Bflag1; //系统标志寄存器1 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 UTC_FLG :1; //充电低温保护标志位 1：发生过充电低温保护 0：未发生过充电低温保护 X unsigned char UTC_FLG :1; N u8 OTC_FLG :1; //充电高温保护标志位 1：发生过充电高温保护 0：未发生过充电高温保护 X unsigned char OTC_FLG :1; N u8 UTD_FLG :1; //放电低温保护标志位 1：发生过放电低温保护 0：未发生过放电低温保护 X unsigned char UTD_FLG :1; N u8 OTD_FLG :1; //放电高温保护标志位 1：发生过放电高温保护 0：未发生过放电高温保护 X unsigned char OTD_FLG :1; N u8 VADC_FLG :1; //VADC中断标志位 1：发生过VADC中断 0：未发生过VADC中断 该bit被读取之后，硬件会自动清零 X unsigned char VADC_FLG :1; N u8 CADC_FLG :1; //CADC中断标志位 1：发生过CADC中断 0：未发生过CADC中断 该bit被读取之后，硬件会自动清零 X unsigned char CADC_FLG :1; N u8 WAKE_FLG :1; //唤醒中断标志位 1：从IDLE状态(检测到充放电电流)或者SLEEP状态(充电器连接)被唤醒 0：未被唤醒 X unsigned char WAKE_FLG :1; N u8 RST_FLG :1; //复位标志位 1：系统复位后，自动置1，需MCU清零 0：未被唤醒 X unsigned char RST_FLG :1; N N }bits; N }Bflag2; //系统标志寄存器2 只能进行写0错做 N N union N { N u8 datas; X unsigned char datas; N struct N { N u8 WDT1_0 :2; //看门狗溢出时间控制位 X unsigned char WDT1_0 :2; N /* N WDT[1-0]=00：看门狗溢出时间为32S； N WDT[1-0]=01：看门狗溢出时间为16S； N WDT[1-0]=10：看门狗溢出时间为8S； N WDT[1-0]=11：看门狗溢出时间为4S； N */ N }bits; N }Rststat; N N char T1_tmp; //T1温度 N char T2_tmp; //T1温度 N char T3_tmp; //T1温度 N N union N { N u16 cellvol[24]; X unsigned short cellvol[24]; N N struct N { N u16 cell1_vol_Z; //电芯电压1 X unsigned short cell1_vol_Z; N N u16 cell2_vol_Z; //电芯电压2 X unsigned short cell2_vol_Z; N N u16 cell3_vol_Z; //电芯电压3 X unsigned short cell3_vol_Z; N N u16 cell4_vol_Z; //电芯电压4 X unsigned short cell4_vol_Z; N N u16 cell5_vol_Z; //电芯电压5 X unsigned short cell5_vol_Z; N N u16 cell6_vol_Z; //电芯电压6 X unsigned short cell6_vol_Z; N N u16 cell7_vol_Z; //电芯电压7 X unsigned short cell7_vol_Z; N N u16 cell8_vol_Z; //电芯电压8 X unsigned short cell8_vol_Z; N N u16 cell9_vol_Z; //电芯电压9 X unsigned short cell9_vol_Z; N N u16 cell10_vol_Z; //电芯电压10 X unsigned short cell10_vol_Z; N N u16 cell11_vol_Z; //电芯电压11 X unsigned short cell11_vol_Z; N N u16 cell12_vol_Z; //电芯电压12 X unsigned short cell12_vol_Z; N N u16 cell13_vol_Z; //电芯电压13 X unsigned short cell13_vol_Z; N N u16 cell14_vol_Z; //电芯电压14 X unsigned short cell14_vol_Z; N N u16 cell15_vol_Z; //电芯电压15 X unsigned short cell15_vol_Z; N N u16 cell16_vol_Z; //电芯电压16 X unsigned short cell16_vol_Z; N N u16 cell17_vol_Z; //电芯电压17 X unsigned short cell17_vol_Z; N N u16 cell18_vol_Z; //电芯电压18 X unsigned short cell18_vol_Z; N N u16 cell19_vol_Z; //电芯电压19 X unsigned short cell19_vol_Z; N N u16 cell20_vol_Z; //电芯电压20 X unsigned short cell20_vol_Z; N N u16 cell21_vol_Z; //电芯电压21 X unsigned short cell21_vol_Z; N N u16 cell22_vol_Z; //电芯电压22 X unsigned short cell22_vol_Z; N N u16 cell23_vol_Z; //电芯电压23 X unsigned short cell23_vol_Z; N N u16 cell24_vol_Z; //电芯电压24 X unsigned short cell24_vol_Z; N }cellbits; N }Cell_Num; N N u16 zvols; //总电压 单位：10MV X unsigned short zvols; N u16 volyc; //压差 单位：MV X unsigned short volyc; N}RAM_RevData; N N////////////////////////////////////////////////////////////////////////// N////////////////////////////////////////////////////////////////////////// N/*数据*/ N/*309实际格式*/ Ntypedef struct N{ N /*EEPROM寄存器数据*/ N struct N { N union N { N u8 datas; X unsigned char datas; N struct N { N u8 cn3_cn0 :4; //串数配置单位 X unsigned char cn3_cn0 :4; N /* N CN[3:0] = 0101： 5串电芯应用 N CN[3:0] = 0110： 6串电芯应用 N CN[3:0] = 0111： 7串电芯应用 N CN[3:0] = 1000： 8串电芯应用 N CN[3:0] = 1001： 9串电芯应用 N CN[3:0] = 1010： 10串电芯应用 N CN[3:0] = 1011： 11串电芯应用 N CN[3:0] = 1100： 12串电芯应用 N CN[3:0] = 1101： 13串电芯应用 N CN[3:0] = 1110： 14串电芯应用 N CN[3:0] = 1111： 15串电芯应用 N CN[3:0] = qita 16串电芯应用 N */ N u8 BAL :1; //平衡功能模块使能控制位 0： 平衡开启由SH367309内部逻辑控制 1： 平衡开启由外部MCU控制，平衡时序仍由SH367309内部逻辑控制 X unsigned char BAL :1; N u8 OCPM :1; //充放电过流MOSFET控制位 0：充电过流只关闭充电MOSFET；放电过流只关闭放电MOSFET 1：充放电过流关闭充放电MOSFET X unsigned char OCPM :1; N u8 ENMOS :1; //充电MOSFET恢复控制位 0：禁用充电MOSFET恢复控制位 1：启用充电MOSFET恢复控制位。当过充电/温度保护关闭充电MOSFET后，如果检过流1或者放电状态，则开启充电MOSFET； X unsigned char ENMOS :1; N u8 ENPCH :1; //预充电模块控制位 0：禁用预充电功能 1：启用预充电功能 X unsigned char ENPCH :1; N }bits; N }Sconf1; //系统配置寄存器1 N //////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 EUVR :1; //过放电恢复设置控制位 0： 过放电保护状态释放与负载释放无关 1： 过放电保护状态释放还需负载释放 X unsigned char EUVR :1; N u8 OCRA :1; //电流恢复设置控制位 0：不允许电流保护定时恢复 1：允许电流保护定时恢复 X unsigned char OCRA :1; N u8 CTLC1_0 :2; //CTL管脚功能设置控制位 X unsigned char CTLC1_0 :2; N /* N CTLC[1:0]=00：充放电和预充电MOSFET由内部逻辑控制， CTL管脚输入无效 N CTLC[1:0]=01： 控制充电和预充电MOSFET。 CTL输入VL-CTL电平时强制关闭充电和 N 预充电MOSFET； CTL输入VH-CTL电平时充电和预充电MOSFET由内 N 部逻辑控制 N CTLC[1:0]=10： 控制放电MOSFET。 CTL输入VL-CTL电平时强制关闭放电MOSFET； N CTL输入VH-CTL电平时，放电MOSFET由内部逻辑控制 N CTLC[1:0]=11： 控制充放电和预充电MOSFET。 CTL输入VL-CTL电平时强制关闭充放 N 电和预充电MOSFET； CTL输入VH-CTL电平时，充放电和预充电 N MOSFET哨部逻辑控制 N */ N u8 DIS_PF :1; //二次过充电模块使能控制位 0：启用二次过充电保护 1：禁止二次过充电保护 X unsigned char DIS_PF :1; N u8 UV_OP :1; //过放电时MOSFET控制位 0： 过放电只关闭放电MOSFET 1： 过放电关闭充放电MOSFET X unsigned char UV_OP :1; N u8 Res :1; //保留 X unsigned char Res :1; N u8 E0VB :1; //禁止低压电芯充电功能设置控制位 0：关闭“禁止低压电芯充电”功能 1：开启“禁止低压电芯充电”功能 X unsigned char E0VB :1; N }bits; N }Sconf2; //系统配置寄存器2 N //////////////////////////////////////////////////////// N union N { N u16 datas; X unsigned short datas; N struct N { N u16 OV9_0 :10; //过充保护电压 计算方式：寄存器值×5mV X unsigned short OV9_0 :10; N u16 LDRT1_0 :2; //负载释放延时设置控制位 X unsigned short LDRT1_0 :2; N /* N LDRT[1:0] = 00: 负载释放延时 = 100mS N LDRT[1:0] = 01: 负载释放延时 = 500mS N LDRT[1:0] = 10: 负载释放延时 = 1000mS N LDRT[1:0] = 11: 贺头叛邮?= 2000mS N */ N u16 OVT3_0 :4; //过充电保护延时设置控制位 X unsigned short OVT3_0 :4; N /* N OVT[3:0] = 0000： 过充电保护延时 = 100mS N OVT[3:0] = 0001： 过充电保护延时 = 200mS N OVT[3:0] = 0010： 过充电保护延时 = 300mS N OVT[3:0] = 0011： 过充电保护延时 = 400mS N OVT[3:0] = 0100： 过充电保护延时 = 600mS N OVT[3:0] = 0101： 过充电保护延时 = 800mS N OVT[3:0] = 0110： 过充电保护延时 = 1S N OVT[3:0] = 0111： 过充电保护延时 = 2S N OVT[3:0] = 1000： 过充电保护延时 = 3S N OVT[3:0] = 1001： 过充电保护延时 = 4S N OVT[3:0] = 1010： 过充电保护延时 = 6S N OVT[3:0] = 1011： 过充电保护延时 = 8S N OVT[3:0] = 1100： 过充电保护延时 = 10S N OVT[3:0] = 1101： 过充电保护延时 = 20S N OVT[3:0] = 1110： 过充电保护延时 = 30S N OVT[3:0] = 1111： 过充电保护延时 = 40S N */ N }bits; N }Ovh_ovl; //过充电保护电压/过充电保护延时/负载释放延时设置寄存器 N ////////////////////////////////////////////////////////////////////// N union N { N u16 datas; X unsigned short datas; N struct N { N u16 OVR9_0 :10; //过充电恢复电压， 计算方式：寄存器值×5mV X unsigned short OVR9_0 :10; N u16 Res :2; //保留 X unsigned short Res :2; N u16 UVT3_0 :4; //过放电保护延时设置控制位 X unsigned short UVT3_0 :4; N /* N UVT[3:0] = 0000： 过放电保护延时 = 100mS N UVT[3:0] = 0001： 过放电保护延时 = 200mS N UVT[3:0] = 0010： 过放电保护延时 = 300mS N UVT[3:0] = 0011： 过放电保护延时 = 400mS N UVT[3:0] = 0100： 过放电保护延时 = 600mS N UVT[3:0] = 0101： 过放电保护延时 = 800mS N UVT[3:0] = 0110： 过放电保护延时 = 1S N UVT[3:0] = 0111： 过放电保护延时 = 2S N UVT[3:0] = 1000： 过放电保护延时 = 3S N UVT[3:0] = 1001： 过放电保护延时 = 4S N UVT[3:0] = 1010： 过放电保护延时 = 6S N UVT[3:0] = 1011： 过放电保护延时 = 8S N UVT[3:0] = 1100： 过放电保护延时 = 10S N UVT[3:0] = 1101： 过放电保护延时 = 20S N UVT[3:0] = 1110： 过放电保护延时 = 30S N UVT[3:0] = 1111： 过放电保护延时 = 40S N */ N }bits; N }Ovrh_ovrl; //过充电恢复电压/过放电保护延时设置 N ///////////////////////////////////////////////////////////////////// N u8 Uv; //过放电保护电压设置 过放电保护电压， 计算方式：寄存器值×20mV X unsigned char Uv; N N u8 Uvr; //过放电恢复电压设置 过放电恢复电压， 计算方式：寄存器值×20mV 且UV＜UVR X unsigned char Uvr; N N u8 Balv; //平衡开启电压设置 平衡开启电压， 计算方式：寄存器值×20mV X unsigned char Balv; N N u8 Prev; //预充电电压设置 预充电电压， 计算方式：寄存器值×20mV X unsigned char Prev; N N u8 Lov; //低电压禁止充电电压 低电压禁止充电电压， 计算方式：寄存器值×20mV X unsigned char Lov; N N u8 Pfv; //二次过充电保护电压 二次过充电保护电压， 计算方式：寄存器值×20mV X unsigned char Pfv; N N ////////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 CD1T3_0 :4; //放电过流1保护延时设置 X unsigned char CD1T3_0 :4; N /* N OCD1T[3:0] = 0000：放电过流1保护延时 = 50mS N OCD1T[3:0] = 0001：放电过流1保护延时 = 100mS N OCD1T[3:0] = 0010：放电过流1保护延时 = 200mS N OCD1T[3:0] = 0011：放电过流1保护延时 = 400mS N OCD1T[3:0] = 0100：放电过流1保护延时 = 600mS N OCD1T[3:0] = 0101：放电过流1保护延时 = 800mS N OCD1T[3:0] = 0110：放电过流1保护延时 = 1S N OCD1T[3:0] = 0111：放电过流1保护延时 = 2S N OCD1T[3:0] = 1000：放电过流1保护延时 = 4S N OCD1T[3:0] = 1001：放电过流1保护延时 = 6S N OCD1T[3:0] = 1010：放电过流1保护延时 = 8S N OCD1T[3:0] = 1011：放电过流1保护延时 = 10S N OCD1T[3:0] = 1100：放电过流1保护延时 = 15S N OCD1T[3:0] = 1101：放电过流1保护延时 = 20S N OCD1T[3:0] = 1110：放电过流1保护延时 = 30S N OCD1T[3:0] = 1111：放电过流1保护延时 = 40S N */ N u8 OCD1V3_0 :4; //放电过流1保护电压 X unsigned char OCD1V3_0 :4; N /* N OCD1V[3:0] = 0000：放电过流1保护电压 = 20mV N OCD1V[3:0] = 0001：放电过流1保护电压 = 30mV N OCD1V[3:0] = 0010：放电过流1保护电压 = 40mV N OCD1V[3:0] = 0011：放电过流1保护电压 = 50mV N OCD1V[3:0] = 0100： 放电过流1保护电压 = 60mV N OCD1V[3:0] = 0101：放电过流1保护电压 = 70mV N OCD1V[3:0] = 0110：放电过流1保护电压 = 80mV N OCD1V[3:0] = 0111：放电过流1保护电压 = 90mV N OCD1V[3:0] = 1000：放电过流1保护电压 = 100mV N OCD1V[3:0] = 1001：放电过流1保护电压 = 110mV N OCD1V[3:0] = 1010：放电过流1保护电压 = 120mV N OCD1V[3:0] = 1011：放电过流1保护电压 = 130mV N OCD1V[3:0] = 1100：放电过流1保护电压 = 140mV N OCD1V[3:0] = 1101：放电过流1保护电压 = 160mV N OCD1V[3:0] = 1110：放电过流1保护电压 = 180mV N OCD1V[3:0] = 1111悍诺绻?保护电压 = 200mV N */ N }bits; N }Ocd1V_ocd1t; //放电过流1设置 N //////////////////////////////////////////////////////////////////////// N union N { N u8 datats; X unsigned char datats; N struct N { N u8 OCD2T3_0 :4; //放电过流2保护延时 X unsigned char OCD2T3_0 :4; N /* N OCD2T[3:0] = 0000：放电过流2保护延时 = 10mS N OCD2T[3:0] = 0001：放电过流2保护延时 = 20mS N OCD2T[3:0] = 0010：放电过流2保护延时 = 40mS N OCD2T[3:0] = 0011：放电过流2保护延时 = 60mS N OCD2T[3:0] = 0100：放电过流2保护延时 = 80mS N OCD2T[3:0] = 0101：放电过流2保护延时 = 100mS N OCD2T[3:0] = 0110：放电过流2保护延时 = 200mS N OCD2T[3:0] = 0111：放电过流2保护延时 = 400mS N OCD2T[3:0] = 1000：放电过流2保护延时 = 600mS N OCD2T[3:0] = 1001：放电过流2保护延时 = 800mS N OCD2T[3:0] = 1010：放电过流2保护延时 = 1S N OCD2T[3:0] = 1011：放电过流2保护延时 = 2S N OCD2T[3:0] = 1100：放电过流2保护延时 = 4S N OCD2T[3:0] = 1101：放电过流2保护延时 = 8S N OCD2T[3:0] = 1110：放电过流2保护延时 = 10S N OCD2T[3:0] = 1111悍诺绻?保护延时 = 20S N */ N u8 OCD2V3_0 :4; //放电过流2保护电压设置 X unsigned char OCD2V3_0 :4; N /* N OCD2V[3:0] = 0000：放电过流2保护电压 = 30mV N OCD2V[3:0] = 0001：放电过流2保护电压 = 40mV N OCD2V[3:0] = 0010：放电过流2保护电压 = 50mV N OCD2V[3:0] = 0011：放电过流2保护电压 = 60mV N OCD2V[3:0] = 0100：放电过流2保护电压 = 70mV N OCD2V[3:0] = 0101：放电过流2保护电压 = 80mV N OCD2V[3:0] = 0110：放电过流2保护电压 = 90mV N OCD2V[3:0] = 0111：放电过流2保护电压 = 100mV N OCD2V[3:0] = 1000：放电过流2保护电压 = 120mV N OCD2V[3:0] = 1001：放电过流2保护电压 = 140mV N OCD2V[3:0] = 1010：放电过流2保护电压 = 160mV N OCD2V[3:0] = 1011：放电过流2保护电压 = 180mV N OCD2V[3:0] = 1100：放电过流2保护电压 = 200mV N OCD2V[3:0] = 1101：放电过流2保护电压 = 300mV N OCD2V[3:0] = 1110：放电过流2保护电压 = 400mV N OCD2V[3:0] = 1111：放电过流2保护电压 = 500mV N */ N }bits; N }Ocd2V_ocd2t; //放电过流2设置 N /////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 SCT3_0 :4; //短路保护延时设置 X unsigned char SCT3_0 :4; N /* N SCT[3:0] = 0000：短路保护延时 = 0uS N SCT[3:0] = 0001：短路保护延时 = 64uS N SCT[3:0] = 0010：短路保护延时 = 128uS N SCT[3:0] = 0011：短路保护延时 = 192uS N SCT[3:0] = 0100：短路保护延时 = 256uS N SCT[3:0] = 0101：短路保护延时 = 320uS N SCT[3:0] = 0110：短路保护延时 = 384uS N SCT[3:0] = 0111：短路保护延时 = 448uS N SCT[3:0] = 1000：短路保护延时 = 512uS N SCT[3:0] = 1001：短路保护延时 = 576uS N SCT[3:0] = 1010：短路保护延时 = 640uS N SCT[3:0] = 1011：短路保护延时 = 704uS N SCT[3:0] = 1100：短路保护延时 = 768uS N SCT[3:0] = 1101：短路保护延时 = 832uS N SCT[3:0] = 1110：短路保护延时 = 896uS N SCT[3:0] = 1111：短路保护延时 = 960uS N */ N u8 SCV_3_0 :4; //短路保护保护电压 X unsigned char SCV_3_0 :4; N /* N SCV[3:0] = 0000：短路保护电压 = 50mV N SCV[3:0] = 0001：短路保护电压 = 80mV N SCV[3:0] = 0010：短路保护电压 = 110mV N SCV[3:0] = 0011：短路保护电压 = 140mV N SCV[3:0] = 0100：短路保护电压 = 170mV N SCV[3:0] = 0101：短路保护电压 = 200mV N SCV[3:0] = 0110：短路保护电压 = 230mV N SCV[3:0] = 0111：短路保护电压 = 260mV N SCV[3:0] = 1000：短路保护电压 = 290mV N SCV[3:0] = 1001：短路保护电压 = 320mV N SCV[3:0] = 1010：短路保护电压 = 350mV N SCV[3:0] = 1011：短路保护电压 = 400mV N SCV[3:0] = 1100：短路保护电压 = 500mV N SCV[3:0] = 1101：短路保护电压 = 600mV N SCV[3:0] = 1110：短路保护电压 = 800mV N SCV[3:0] = 1111：短路保护电压 = 1000mV N */ N }bits; N }Scv_sct; //短路保护设置 N /////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OCCT3_0 :4; //充电过流保护延时 X unsigned char OCCT3_0 :4; N /* N OCCT[3:0] = 0000：充电过流保护延时 = 10mS N OCCT[3:0] = 0001：充电过流保护延时 = 20mS N OCCT[3:0] = 0010：充电过流保护延时 = 40mS N OCCT[3:0] = 0011：充电过流保护延时 = 60mS N OCCT[3:0] = 0100：充电过流保护延时 = 80mS N OCCT[3:0] = 0101：充电过流保护延时 = 100mS N OCCT[3:0] = 0110：充电过流保护延时 = 200mS N OCCT[3:0] = 0111：充电过流保护延时 = 400mS N OCCT[3:0] = 1000：充电过流保护延时 = 600mS N OCCT[3:0] = 1001：充电过流保护延时 = 800mS N OCCT[3:0] = 1010：充电过流保护延时 = 1S N OCCT[3:0] = 1011：充电过流保护延时 = 2S N OCCT[3:0] = 1100：充电过流保护延时 = 4S N OCCT[3:0] = 1101：充电过流保护延时 = 8S N OCCT[3:0] = 1110：充电过流保护延时 = 10S N OCCT[3:0] = 1111：充电过流保护延时 = 20S N */ N u8 OCCV3_0 :4; //充电过流保护电压 X unsigned char OCCV3_0 :4; N /* N OCCV[3:0] = 0000：充电过流保护电压 = 20mV N OCCV[3:0] = 0001：充电过流保护电压 = 30mV N OCCV[3:0] = 0010：充电过流保护电压 = 40mV N OCCV[3:0] = 0011：充电过流保护电压 = 50mV N OCCV[3:0] = 0100：充电过流保护电压 = 60mV N OCCV[3:0] = 0101：充电过流保护电压 = 70mV N OCCV[3:0] = 0110：充电过流保护电压 = 80mV N OCCV[3:0] = 0111：充电过流保护电压 = 90mV N OCCV[3:0] = 1000：充电过流保护电压 = 100mV N OCCV[3:0] = 1001：充电过流保护电压 = 110mV N OCCV[3:0] = 1010：充电过流保护电压 = 120mV N OCCV[3:0] = 1011：充电过流保护电压 = 130mV N OCCV[3:0] = 1100：充电过流保护电压 = 140mV N OCCV[3:0] = 1101：充电过流保护电压 = 160mV N OCCV[3:0] = 1110：充电过流保护电压 = 180mV N OCCV[3:0] = 1111：充电过流保护电压 = 200mV N */ N }bits; N }Occv_occt; //充电过流设置 N ////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 PFT1_0 :2; //二次过充电保护延时 X unsigned char PFT1_0 :2; N /* N PFT[1:0] = 00： 二次过充电保护延时 =8S N PFT[1:0] = 01： 二次过充电保护延时= 16S N PFT[1:0] = 10： 二次过充电保护延时= 32S N PFT[1:0] = 11： 二次过充电保护延时= 64S N */ N u8 OCRT1_0 :2; //充放电过流自恢复延时 X unsigned char OCRT1_0 :2; N /* N OCRT[1:0] = 00：充放电过流自动恢复延时 = 8S N OCRT[1:0] = 01：充放电过流自动恢复延时 = 16S N OCRT[1:0] = 10：充放电过流自动恢复延时 = 32S N OCRT[1:0] = 11：充放电过流自动恢复延时 = 64S N */ N u8 MOST1_0 :2; //充放电MOSFET开启延时 X unsigned char MOST1_0 :2; N /* N MOST[1:0] = 00： 充放电MOSFET开启延时 = 64uS N MOST[1:0] = 01： 充放电MOSFET开启延时 = 128uS N MOST[1:0] = 10： 充放电MOSFET开启延时 = 256uS N MOST[1:0] = 11： 充放电MOSFET开启延时 = 512uS N */ N u8 CHS1_0 :2; //充放电状态检测电压 X unsigned char CHS1_0 :2; N /* N CHS [1:0] = 00： 充放电状态检测电压 = 200uV N CHS [1:0] = 01： 充放电状态检测电压 = 500uV N CHS [1:0] = 10： 充放电状态检测电压 = 1000uV N CHS [1:0] = 11： 充放电状态检测电压 = 2000uV N */ N }bits; N }Most_ocrt_pft; //充放电过流自动恢复/二次过充电保护延时设置 N //////////////////////////////////////////////////////////////////// N N char Otc; //充电高温保护设置 充电高温保护阈值 N N char Otcr; //充电高温保护释放 充电高温保护释放阈值 N N char Utc; //充电低温保护设置 充电低温保护阈值 N N char Utcr; //充电低温保护释放设置 充电低温保护释放阈值 N N char Otd; //放电高温保护设置 放电高温保护阈值 N N char Otdr; //放电高温保护释放设置 放电高温保护释放阈值 N N char Utd; //放电低温保护设置 放电低温保护阈值 N N char Utdr; //放电低温保护释放设置 放电低温保护释放阈值 N N char Tr; //读温度内部参考电阻系数 N }EEPROMWriRev_309; N N //////////////////////////////////////////////////////////////////// N /*RAM寄存器读数据*/ N /*309实际格式*/ N struct N { N union N { N u8 datas; X unsigned char datas; N struct N { N u8 IDLE :1; //IDLE设置控制位 0： SH367309不进入IDLE状态 1： SH367309将进入IDLE状态，唤醒后硬件自动清零 X unsigned char IDLE :1; N u8 SLEEP :1; //SLEEP设置控制位 0： SH367309不进入SLEEP状态 1： SH367309将进入SLEEP状态，唤醒后硬件自动清零 X unsigned char SLEEP :1; N u8 ENWDT :1; //看门狗设置控制位 0： SH367309关闭看门狗模块 1： SH367309开启看门狗模块 X unsigned char ENWDT :1; N u8 CADCON :1; //CADC设置控制位 0： SH367309关闭CADC 1： SH367309开启CADC进行电流采集 X unsigned char CADCON :1; N u8 CHGMOS :1; //充电MOSFET控制位 0： 充电MOSFET关闭 1：充电MOSFET由硬件保护模块决定 X unsigned char CHGMOS :1; N u8 DSGMOS :1; //放电MOSFET控制位 0：放电MOSFET关闭 1：放电MOSFET由硬件保护模块决定 X unsigned char DSGMOS :1; N u8 PCHMOS :1; //预充电MOSFET控制位 0：预充电MOSFET关闭 1：预充电MOSFET由硬件保护模块决定 X unsigned char PCHMOS :1; N u8 OCRC :1; //过流保护控制位 过流保护状态清除需在OCRC位连续写： 0-1-0 X unsigned char OCRC :1; N }bits; N }Conf; //系统配置 N ////////////////////////////////////////////////////////////////////////////////////// N union N { N u16 datas; X unsigned short datas; N struct N { N u16 CB1 :1; //0：关闭CellN平衡回路 1：开启CellN平衡回路 X unsigned short CB1 :1; N u16 CB2 :1; X unsigned short CB2 :1; N u16 CB3 :1; X unsigned short CB3 :1; N u16 CB4 :1; X unsigned short CB4 :1; N u16 CB5 :1; X unsigned short CB5 :1; N u16 CB6 :1; X unsigned short CB6 :1; N u16 CB7 :1; X unsigned short CB7 :1; N u16 CB8 :1; X unsigned short CB8 :1; N u16 CB9 :1; X unsigned short CB9 :1; N u16 CB10 :1; X unsigned short CB10 :1; N u16 CB11 :1; X unsigned short CB11 :1; N u16 CB12 :1; X unsigned short CB12 :1; N u16 CB13 :1; X unsigned short CB13 :1; N u16 CB14 :1; X unsigned short CB14 :1; N u16 CB15 :1; X unsigned short CB15 :1; N u16 CB16 :1; X unsigned short CB16 :1; N }bits; N }Balanceh_l; //控制电池阻的平衡回路 N ////////////////////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OV :1; // 过压保护状态位 1：发生过压保护 0：未发生过压保护 X unsigned char OV :1; N u8 UV :1; // 欠压保护状态位 1：发生欠压保护 0：未发生欠压保护 X unsigned char UV :1; N u8 OCD1 :1; // 放电过流1保护状态位 1：发生放电过流1保护 0：未发生放电过流1保护 X unsigned char OCD1 :1; N u8 OCD2 :1; // 放电过流2保护状态位 1：发生放电过流2保护 0：未发生放电过流2保护 X unsigned char OCD2 :1; N u8 OCC :1; // 充电过流保护状态位 1：发生充电过流保护 0： 未发生充电过流保护 X unsigned char OCC :1; N u8 SC :1; // 短路保护状态位 1：发生短路保护 0： 未发生短路保护 X unsigned char SC :1; N u8 PF :1; // 二次过充电保护状态位 1：发生二次过充电保护 0：未发生二次过充电保护 X unsigned char PF :1; N u8 WDT :1; // 看门狗状态位 1：看门狗溢出 0：看门狗正常 X unsigned char WDT :1; N }bits; N }Bstrtus1;//系统状态1寄存器 N /////////////////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 UTC :1; //充电低温保护状态位 1：发生充电低温保护 0：未发生充电低温保护 X unsigned char UTC :1; N u8 OTC :1; //充电高温保护状态位 1：发生充电高温保护 0：未发生充电高温保护 X unsigned char OTC :1; N u8 UTD :1; //放电低温保护状态位 1：发生放电低温保护 0：未发生放电低温保护 X unsigned char UTD :1; N u8 OTD :1; //放电高温保护状态位 1：发生放电高温保护 0：未发生放电高温保护 X unsigned char OTD :1; N u8 Ren :4; //保留 X unsigned char Ren :4; N }bits; N }Bstrtus2;//系统状态2寄存器 N //////////////////////////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 DSG_FET :1; //放电MOSFET开关状态位 1：放电MOSFET开启 0：放电MOSFET关闭 X unsigned char DSG_FET :1; N u8 CHG_FET :1; //充电MOSFET开关状态位 1：充电MOSFET开启 0：充电MOSFET关闭 X unsigned char CHG_FET :1; N u8 PCHG_FET :1; //预充电MOSFET开关状态位 1：预充电MOSFET开启 0：预充电MOSFET关闭 X unsigned char PCHG_FET :1; N u8 L0V :1; //低电压禁止充电状态位 1：发生低电压禁止充电 0：未发生低电压禁止充电 X unsigned char L0V :1; N u8 EEPR_WR :1; //EEPROM写操作状态位 1： EEPROM写操作错误 0： EEPROM写操作正确 X unsigned char EEPR_WR :1; N u8 Ren :1; //保留 X unsigned char Ren :1; N u8 DSGING :1; //放电状态位 1：放电状态 0：非放电状态 X unsigned char DSGING :1; N u8 CHGING :1; //充电状态位 1：充电状态 0：非充电状态 X unsigned char CHGING :1; N }bits; N N }Bstrtus3;//系统状态3寄存器 N /////////////////////////////////////////////////////////////////////////// N N u16 TEMP1h_l; //T1温度 当转换完成后，数据更新为温度电阻1上的电压分压比对应的数值 X unsigned short TEMP1h_l; N N u16 TEMP2h_l; //T2温度 当转换完成后，数据更新为温度电阻2上的电压分压比对应的数值 X unsigned short TEMP2h_l; N N u16 TEMP3h_l; //T3温度 当转换完成后，数据更新为温度电阻3上的电压分压比对应的数值 X unsigned short TEMP3h_l; N N u16 Curh_l; // CUR15 当转换完成后，数据更新为 为符号位， “1”表示放电； Sense“0” 电阻两端电压对 表示充电。 应的数值 &0xef X unsigned short Curh_l; N N union N { N u16 cellvol[16]; X unsigned short cellvol[16]; N N struct N { N u16 cell1_vol; //电芯电压1 X unsigned short cell1_vol; N N u16 cell2_vol; //电芯电压2 X unsigned short cell2_vol; N N u16 cell3_vol; //电芯电压3 X unsigned short cell3_vol; N N u16 cell4_vol; //电芯电压4 X unsigned short cell4_vol; N N u16 cell5_vol; //电芯电压5 X unsigned short cell5_vol; N N u16 cell6_vol; //电芯电压6 X unsigned short cell6_vol; N N u16 cell7_vol; //电芯电压7 X unsigned short cell7_vol; N N u16 cell8_vol; //电芯电压8 X unsigned short cell8_vol; N N u16 cell9_vol; //电芯电压9 X unsigned short cell9_vol; N N u16 cell10_vol; //电芯电压10 X unsigned short cell10_vol; N N u16 cell11_vol; //电芯电压11 X unsigned short cell11_vol; N N u16 cell12_vol; //电芯电压12 X unsigned short cell12_vol; N N u16 cell13_vol; //电芯电压13 X unsigned short cell13_vol; N N u16 cell14_vol; //电芯电压14 X unsigned short cell14_vol; N N u16 cell15_vol; //电芯电压15 X unsigned short cell15_vol; N N u16 cell16_vol; //电芯电压16 X unsigned short cell16_vol; N }cellbits; N }Cell; N N u16 CADcdh_l; //电流 DATA.15 当转换完成后，数据更新为 为符号位， “1”表示放电； Sense电阻两端电压对应的数值 &0xef X unsigned short CADcdh_l; N N //////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 OV_FLG :1; //过压保护标志位 1：发生过过压保护 0：未发生过过压保护 X unsigned char OV_FLG :1; N u8 UV_FLG :1; //欠压保护标志位 1：发生过欠压保护 0：未发生过欠压保护 X unsigned char UV_FLG :1; N u8 OCD_FLG :1; //放电过流保护标志位 1：发生过放电过流保护 0：未发生过放电过流保护 X unsigned char OCD_FLG :1; N u8 LOAD_FLG :1; //LDO3过流标志位 1：发生过过流 0：未发生过过流 X unsigned char LOAD_FLG :1; N u8 OCC_FLG :1; //充电过流保护标志位 1：发生过充电过流保护 0：未发生过充电过流保护 X unsigned char OCC_FLG :1; N u8 SC_FLG :1; //短路保护标志位 1：发生过短路保护 0：未发生过短路保护 X unsigned char SC_FLG :1; N u8 PF_FLG :1; //二次过充电保护标志位 1：发生过二次过充电保护 0：未发生过二次过充电保护 X unsigned char PF_FLG :1; N u8 WDT_FLG :1; //看门狗标志位 1：发生过看门狗溢出 0： 未发生过看门狗溢出 X unsigned char WDT_FLG :1; N }bits; N }Bflag1; //系统标志寄存器1 N /////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 UTC_FLG :1; //充电低温保护标志位 1：发生过充电低温保护 0：未发生过充电低温保护 X unsigned char UTC_FLG :1; N u8 OTC_FLG :1; //充电高温保护标志位 1：发生过充电高温保护 0：未发生过充电高温保护 X unsigned char OTC_FLG :1; N u8 UTD_FLG :1; //放电低温保护标志位 1：发生过放电低温保护 0：未发生过放电低温保护 X unsigned char UTD_FLG :1; N u8 OTD_FLG :1; //放电高温保护标志位 1：发生过放电高温保护 0：未发生过放电高温保护 X unsigned char OTD_FLG :1; N u8 VADC_FLG :1; //VADC中断标志位 1：发生过VADC中断 0：未发生过VADC中断 该bit被读取之后，硬件会自动清零 X unsigned char VADC_FLG :1; N u8 CADC_FLG :1; //CADC中断标志位 1：发生过CADC中断 0：未发生过CADC中断 该bit被读取之后，硬件会自动清零 X unsigned char CADC_FLG :1; N u8 WAKE_FLG :1; //唤醒中断标志位 1：从IDLE状态(检测到充放电电流)或者SLEEP状态(充电器连接)被唤醒 0：未被唤醒 X unsigned char WAKE_FLG :1; N u8 RST_FLG :1; //复位标志位 1：系统复位后，自动置1，需MCU清零 0：未被唤醒 X unsigned char RST_FLG :1; N N }bits; N }Bflag2; //系统标志寄存器2 只能进行写0错做 N ///////////////////////////////////////////////////////// N union N { N u8 datas; X unsigned char datas; N struct N { N u8 WDT1_0 :2; //看门狗溢出时间控制位 X unsigned char WDT1_0 :2; N /* N WDT[1-0]=00：看门狗溢出时间为32S； N WDT[1-0]=01：看门狗溢出时间为16S； N WDT[1-0]=10：看门狗溢出时间为8S； N WDT[1-0]=11：看门狗溢出时间为4S； N */ N }bits; N }Rststat; N ////////////////////////////////////////////////////////// N }RAM_WrieRev_309; N}Data_309buf; N N N N N N/*******************变量声明**************************/ Nextern GPS_Buf swj_buf; //接收上位机数据缓存 N Nextern EEPROMWriRevdata EEPROM_309data;//309EEPROM数据 Nextern RAM_RevData RAM_309data; //309RAM数据 Nextern Data_309buf data_309_A; //主309相关数据 最多16串数据 Nextern Data_309buf data_309_B; //副309相关数据 最多16串数据 N Nextern u8 Ranjianyinjian;//软件版硬件版选择 0软件 1硬件 Xextern unsigned char Ranjianyinjian; Nextern u8 Conf_309num; //309控制芯片数目 0两个 1一个 Xextern unsigned char Conf_309num; N Nextern unsigned char stop_orde[22]; Nextern unsigned char start_orde[22]; N Nextern const float Rp; //10K NTC电阻常温下标准阻止 Nextern const float T2; //T2 开尔文温度 Nextern const float Bx; //系数B Nextern const float Ka; //绝对温度 N N N/*蓝牙变量声明*/ Nextern GPS_Buf Bluttooth_buf; //接收上位机数据缓存 N N/*定义接收串口2的数据缓存*/ Nextern GPS_Buf MCU_buf; //接收MCU数据缓存 N N/********************函数声明**************************/ N N/* N*函数名：Get_Temp N*函数参数：NTC_Res N*函数返回值：返回温度值 有符号整型 N*函数功能：根据Rt热敏电阻值 算出温度 N*/ Nextern int Get_Temp(u32 NTC_Res); Xextern int Get_Temp(unsigned int NTC_Res); N N/*充放电高温温度转化*/ Nextern float Get_Gtemp(signed char T1); N N// 获取NTC通道上的检测温度，精确到1度 Nextern s16 ClacNTC(u32 val); Xextern s16 ClacNTC(unsigned int val); N Nextern float Ntc_ad(signed char tmp); N N N/* N*函数名 Send_GpsFun N*函数参数： bmsnum 终端号 N orde 命令字 N type 传输类型 N *buff 数据首地址 N len 数据域长度 N Recnumber 记录号 N*函数返回值：wu N*函数功能：发送数据到上位机 N*/ Nextern void Send_GpsFun(u32 bmsnum,u8 orde,u8 type,u8 *buff,u16 len,u32 Recnumber); Xextern void Send_GpsFun(unsigned int bmsnum,unsigned char orde,unsigned char type,unsigned char *buff,unsigned short len,unsigned int Recnumber); N N N/* N*函数名：swjdecodea N*函数参数：wu N*函数功能：gps数据接收处理函数 N*函数返回值：wu N*/ Nextern void swjdecodea(void); N N#endif L 25 "..\user\src\swj.c" 2 N#include "IIc.h" L 1 "..\user\inc\IIc.h" 1 N#ifndef IIC_H N#define IIC_H N N#include "stm32f10x.h" N#include "stm32f10x_conf.h" N#include "Stmtype.h" N#include "def.h" N N//Define For MTP Module(SH367309) N #define MTP_ID 0x34 N N//Define For E2PRom Module N#define E2PROM_ID 0xA0 N N N N/*函数声明*/ N/*309芯片操作函数*/ N/*写数据函数*/ Nextern void MTPWrite_1(U8 SlaveID, U8 WrAddr, U8 WdBuf); Nextern void MTPWrite_2(U8 SlaveID, U8 WrAddr, U8 WdBuf); N N/*读数据函数*/ Nextern void MTPRead_1(U8 SlaveID, U8 RrAddr, U8 Length, U8 *RdBuf); Nextern void MTPRead_2(U8 SlaveID, U8 RrAddr, U8 Length, U8 *RdBuf); N N/*重置芯片函数*/ Nextern void ResetAFE_1(void); Nextern void ResetAFE_2(void); N N N/*发送集成函数*/ Nextern void MTPWrite_fun_1(U8 WrAddr, U8 Length, U8 *WrBuf); N N/*读集成数据*/ Nextern void MTPRead_fun_1(U8 RdAddr, U8 Length, U8 *RdBuf); N N/*发送集成函数*/ Nextern void MTPWrite_fun_2(U8 WrAddr, U8 Length, U8 *WrBuf); N N/*读集成数据*/ Nextern void MTPRead_fun_2(U8 RdAddr, U8 Length, U8 *RdBuf); N N N#endif L 26 "..\user\src\swj.c" 2 N N#define START_VALUE_NTC (s32)(-40) N#define END_VALUE_NTC (s32)(121) N#define countof(arr) (sizeof(arr)/sizeof(arr[0])) N N/*热敏系数表 10K 3435*/ Nconst s32 NTC10KTab[] = N{ N/* -9度 -8度 -7度 -6度 -5度 -4度 -3度 -2度 -1度 0度 */ N/*-40*/ 184726, N/*-30*/ 175139, 166083, 157544, 149489, 141889, 134716, 127944, 121548, 115506, 109797, N/*-20*/ 104401, 99299, 94473, 92908, 89908, 81498, 77625, 73957, 70483, 67190, N/*-10*/ 64068, 61109, 58301, 55637, 53110, 50711, 48432, 46269, 44214, 42261, N/*0*/ 40403, 38639, 36960, 35362, 33959, 32397, 31020, 29709, 28462, N/* 0度 1度 2度 3度 4度 5度 6度 7度 8度 9度 */ N/*0*/ 27766, 26592, 25482, 24424, 23415, 22346, 21430, 20560, 19535, 18742, N/*10*/ 18016, 17269, 16583, 15928, 15302, 14704, 14134, 13588, 13067, 12568, N/*20*/ 12092, 11636, 11199, 10782, 10382, 10000, 9633, 9282, 8946, 8623, N/*30*/ 8314, 8018, 7734, 7461, 7199, 6948, 6707, 6476, 6254, 6040, N/*40*/ 5835, 5638, 5449, 5267, 5091, 4923, 4761, 4605, 4455, 4311, N/*50*/ 4168, 4038, 3909, 3785, 3665, 3550, 3439, 3332, 3229, 3129, N/*60*/ 3033, 2941, 2851, 2765, 2682, 2602, 2524, 2449, 2377, 2307, N/*70*/ 2240, 2175, 2112, 2051, 1992, 1935, 1880, 1827, 1776, 1726, N/*80*/ 1678, 1632, 1587, 1543, 1501, 1461, 1421, 1383, 1356, 1335, N/*90*/ 1315, 1221, 1188, 1158, 1127, 1099, 1071, 1043, 1016, 982, N/*100*/ 966, 941, 917, 894, 873, 851, 831, 812, 792, 772, N/*110*/ 753, 735, 718, 701, 684, 666, 652, 631, 622, 607, N/*120*/ 593, 580 N}; N Nbool Activate = 1; //激活标志位 X_Bool Activate = 1; NGPS_Buf swj_buf={0}; //接收上位机数据缓存 N NEEPROMWriRevdata EEPROM_309data={0};//309EEPROM数据 NRAM_RevData RAM_309data={0}; //309RAM数据 NData_309buf data_309_A = {0}; //主309相关数据 最多16串数据 NData_309buf data_309_B = {0}; //副309相关数据 最多16串数据 N N/*控制选择指令*/ Nu8 Ranjianyinjian = 0;//软件版硬件版选择 0软件 1硬件 Xunsigned char Ranjianyinjian = 0; Nu8 Conf_309num = 2; //309控制芯片数目 Xunsigned char Conf_309num = 2; N N/*跟保护板通信防干扰指令*/ //4E 57 00 14 00 00 00 00 0B 00 00 01 01 00 00 00 00 68 00 00 01 2E N //4E 57 00 14 00 00 00 00 0B 00 00 01 00 00 00 00 00 68 00 00 01 2D Nunsigned char stop_orde[22]={0x4E,0x57,0x00,0x14,0x00,0x00,0x00,0x00,0x0B,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x68,0x00,0x00,0x01,0x2E}; Nunsigned char start_orde[22]={0x4E,0x57,0x00,0x14,0x00,0x00,0x00,0x00,0x0B,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x68,0x00,0x00,0x01,0x2D}; N N/* N*函数名：Get_Temp N*函数参数：NTC_Res N*函数返回值：返回温度值 有符号整型 N*函数功能：根据Rt热敏电阻值 算出温度 N*/ Nconst float Rp = 10000.0; //10K NTC电阻常温下标准阻止 Nconst float T2 = (273.15+25.0);//T2 开尔文温度 Nconst float Bx = 3435.0; //系数B Nconst float Ka = 273.15; //绝对温度 N N Nint Get_Temp(u32 NTC_Res) Xint Get_Temp(unsigned int NTC_Res) N{ N int tmp; N float Rt; N float temp; N N Rt = NTC_Res; N N //like this R=10000, T2=273.15+25,B=3435, RT=10000*EXP(3435*(1/T1-1/(273.15+25)), N temp = Rt/Rp; N temp = log(temp);//ln(Rt/Rp) N temp/=Bx;//ln(Rt/Rp)/B N temp+=(1/T2); N temp = 1/(temp); N temp-=Ka; N N if(temp < 0 && temp >= -10) N temp = temp - 2; N else if(temp < -10 && temp >= -20) N temp = temp - 3; N else if(temp < -20 && temp >= -30) N temp = temp - 4; N else if(temp < -30 && temp >= -40) N temp = temp - 5; N N tmp = temp; N return tmp; N} N N/*充放电高温温度转化*/ Nfloat Get_Gtemp(signed char T1) N{ N float zuz = 0; N if((T1 < 0) && (T1 >= -10)) N T1 = T1 + 2; N else if((T1 < -10) && (T1 >= -20)) N T1 = T1 + 3; N else if((T1 < -20) && (T1 >= -30)) N T1 = T1 + 4; N else if((T1 < -30) && (T1 >= -40)) N T1 = T1 + 5; N N zuz = Rp * exp((Bx*(1/(Ka+T1)-1/T2))); N zuz = zuz / 1000.0; N return zuz; N} N N N// 获取NTC通道上的检测温度，精确到1度 Ns16 ClacNTC(u32 val) Xs16 ClacNTC(unsigned int val) N{ N s32 i; N N if (val > NTC10KTab[0]) //最低温 N return START_VALUE_NTC; X return (s32)(-40); N if (val < NTC10KTab[countof(NTC10KTab)-1]) //最高温 X if (val < NTC10KTab[(sizeof(NTC10KTab)/sizeof(NTC10KTab[0]))-1]) N return ((s16)countof(NTC10KTab)+START_VALUE_NTC); X return ((s16)(sizeof(NTC10KTab)/sizeof(NTC10KTab[0]))+(s32)(-40)); N N for (i=0; i NTC10KTab[i+1]) && (val < NTC10KTab[i])) N return (i+START_VALUE_NTC); X return (i+(s32)(-40)); N } W "..\user\src\swj.c" 151 1 missing return statement at end of non-void function "ClacNTC" N} N Nfloat Ntc_ad(signed char tmp) N{ N N if(tmp < START_VALUE_NTC) X if(tmp < (s32)(-40)) N return NTC10KTab[0] / 1000.0; N else if(tmp > END_VALUE_NTC) X else if(tmp > (s32)(121)) N return NTC10KTab[121-START_VALUE_NTC] / 1000.0; X return NTC10KTab[121-(s32)(-40)] / 1000.0; N else N return NTC10KTab[tmp-START_VALUE_NTC] / 1000.0; X return NTC10KTab[tmp-(s32)(-40)] / 1000.0; N} N N N/* N*函数名 Send_GpsFun N*函数参数： bmsnum 终端号 N orde 命令字 N type 传输类型 N *buff 数据首地址 N len 数据域长度 N Recnumber 记录号 N*函数返回值：wu N*函数功能：发送数据到上位机 N*/ Nvoid Send_GpsFun(u32 bmsnum,u8 orde,u8 type,u8 *buff,u16 len,u32 Recnumber) Xvoid Send_GpsFun(unsigned int bmsnum,unsigned char orde,unsigned char type,unsigned char *buff,unsigned short len,unsigned int Recnumber) N{ N u16 index; X unsigned short index; N u8 sendbuf[420] = {0}; X unsigned char sendbuf[420] = {0}; N Data_frame data_frame; N N data_frame.start_frame = START_FRAME; X data_frame.start_frame = 0x4e57; N data_frame.Len_frame = S_GD_LEN + len - 2; X data_frame.Len_frame = 0x14 + len - 2; N data_frame.Bms_number = bmsnum; N data_frame.orde = orde; N data_frame.farm_sor = 0x00; N data_frame.Type = type; N memcpy(data_frame.s_data,buff,len); N data_frame.Recnumber = Recnumber; N data_frame.end_signs = END_FRAME; X data_frame.end_signs = 0x68; N data_frame.check_sum = 0; N N sendbuf[0] = (data_frame.start_frame >> 8); N sendbuf[1] = data_frame.start_frame; N sendbuf[2] = (data_frame.Len_frame >> 8); N sendbuf[3] = data_frame.Len_frame; N sendbuf[4] = (data_frame.Bms_number >> 24); N sendbuf[5] = (data_frame.Bms_number >> 16); N sendbuf[6] = (data_frame.Bms_number >> 8); N sendbuf[7] = data_frame.Bms_number; N sendbuf[8] = data_frame.orde; N sendbuf[9] = data_frame.farm_sor; N sendbuf[10]= data_frame.Type; N memcpy(&sendbuf[11],data_frame.s_data,len); N sendbuf[11 + len] = (data_frame.Recnumber >> 24); N sendbuf[12 + len] = (data_frame.Recnumber >> 16); N sendbuf[13 + len] = (data_frame.Recnumber >> 8); N sendbuf[14 + len] = data_frame.Recnumber; N sendbuf[15 + len] = data_frame.end_signs; N N for(index = 0; index < S_GD_LEN + len - 4; index++) X for(index = 0; index < 0x14 + len - 4; index++) N { N data_frame.check_sum += sendbuf[index]; N } N sendbuf[16 + len] = 0x00; N sendbuf[17 + len] = 0x00; N sendbuf[18 + len] = (data_frame.check_sum >> 8); N sendbuf[19 + len] = data_frame.check_sum; N N /*发送数据*/ W "..\user\src\swj.c" 221 2 function "Send_TString_Upper" declared implicitly N Send_TString_Upper(sendbuf,(u16)(S_GD_LEN + len)); X Send_TString_Upper(sendbuf,(unsigned short)(0x14 + len)); N} N N N/* N*函数名：swjdecodea N*函数参数：wu N*函数功能：swj数据接收处理函数 N*函数返回值：wu N*/ Nvoid swjdecodea(void) N{ N u16 data_len = 0; //长度 X unsigned short data_len = 0; N u32 crc_sum = 0; //累加和 X unsigned int crc_sum = 0; N u32 Bms_num = 0; //BMS终端号 X unsigned int Bms_num = 0; N u16 index; X unsigned short index; N N u8 orde = 0; //命令字 X unsigned char orde = 0; N u8 b_addr = 0; //标识码 X unsigned char b_addr = 0; N u8 Type = 0; //传输类型 X unsigned char Type = 0; N u32 recnum = 0; //记录号 X unsigned int recnum = 0; N N u8 sendbuffer[300]; //发送数据缓存 X unsigned char sendbuffer[300]; N u16 send_len = 0; //数据域长度 X unsigned short send_len = 0; N N /*309相关变量*/ N u8 send_309_buf_A[2]={0}; //309读写缓存数据 X unsigned char send_309_buf_A[2]={0}; N u8 send_309_buf_B[2]={0}; //309读写缓存数据 X unsigned char send_309_buf_B[2]={0}; N u8 Rev_309_buf_A[2]={0}; X unsigned char Rev_309_buf_A[2]={0}; N u8 Rev_309_buf_B[2]={0}; X unsigned char Rev_309_buf_B[2]={0}; N u8 addr_309 = 0; //309读写起始地址 X unsigned char addr_309 = 0; N u8 len_309 = 0; //309读写长度 X unsigned char len_309 = 0; N u8 Rw309_Flag = 0; //读写309标志 X unsigned char Rw309_Flag = 0; N N /*温度相关变量*/ N float Rref = 0; //内部参考电阻(单位：KΩ) N float Rt1 = 0; //热敏电阻阻值(单位：KΩ) N N /*串数相关变量*/ N u8 A_Cellnum = 0; //主309 芯片电池串数 X unsigned char A_Cellnum = 0; N u8 B_Cellnum = 0; //副309 芯片电池串数 X unsigned char B_Cellnum = 0; N N /*接收一帧报文成功*/ N if(swj_buf.gps_Rev_start == 1) N { N swj_buf.gps_Rev_start = 0; //清除标志位 N Data_Source = 1; N N data_len = (u16)((swj_buf.gps_Rev_buf[2] << 8) | swj_buf.gps_Rev_buf[3]); X data_len = (unsigned short)((swj_buf.gps_Rev_buf[2] << 8) | swj_buf.gps_Rev_buf[3]); N N for(index = 0; index < data_len + 2 - 4; index++) N { N crc_sum += swj_buf.gps_Rev_buf[index]; N } N N /*条件约束*/ N if((u16)crc_sum == (u16)((swj_buf.gps_Rev_buf[data_len + 2 - 2] << 8) | swj_buf.gps_Rev_buf[data_len + 2 - 1])) X if((unsigned short)crc_sum == (unsigned short)((swj_buf.gps_Rev_buf[data_len + 2 - 2] << 8) | swj_buf.gps_Rev_buf[data_len + 2 - 1])) N { N /*获取BMS终端号*/ N Bms_num = (u32)(((swj_buf.gps_Rev_buf[4] << 8) | (swj_buf.gps_Rev_buf[5])) * 65536 + ((swj_buf.gps_Rev_buf[6] << 8) | swj_buf.gps_Rev_buf[7])); X Bms_num = (unsigned int)(((swj_buf.gps_Rev_buf[4] << 8) | (swj_buf.gps_Rev_buf[5])) * 65536 + ((swj_buf.gps_Rev_buf[6] << 8) | swj_buf.gps_Rev_buf[7])); N N /*获取命令字*/ N orde = swj_buf.gps_Rev_buf[8]; N N /*获取标识码*/ N b_addr = swj_buf.gps_Rev_buf[11]; N N /*获取记录号*/ N recnum = (u32)(((swj_buf.gps_Rev_buf[data_len + 2 - 5 - 4] << 8) | (swj_buf.gps_Rev_buf[data_len + 2 - 5 - 3])) * 65536 + ((swj_buf.gps_Rev_buf[data_len + 2 - 5 - 2] << 8) | swj_buf.gps_Rev_buf[data_len + 2 - 5 - 1])); X recnum = (unsigned int)(((swj_buf.gps_Rev_buf[data_len + 2 - 5 - 4] << 8) | (swj_buf.gps_Rev_buf[data_len + 2 - 5 - 3])) * 65536 + ((swj_buf.gps_Rev_buf[data_len + 2 - 5 - 2] << 8) | swj_buf.gps_Rev_buf[data_len + 2 - 5 - 1])); N N switch(orde) N { N case ACTIVACE_ORDE: //激活指令 从休眠中退出 X case 0x01: N { N Type = 0x01; //应答 N sendbuffer[0] = b_addr; N send_len = 1; N Activate = 1; N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N Beep_Flag = 1; N } N break; N case WRITE_ORDE: //写指令 X case 0x02: N if(Activate == 1) N { N N Type = 0x01; //应答 N N memset(sendbuffer,0,sizeof(sendbuffer)); //数据清零 N N /*判断是否为读写309地址*/ N if(b_addr <= 0x6F) N { W "..\user\src\swj.c" 314 8 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(stop_orde,22); //发送给MCU停止对309读写 N Delay_ms(100); N } N N switch(b_addr) N { N /*309EEPROM写数据*/ N case DATA_EEPROM_SCONF1: X case 0x00: N EEPROM_309data.Sconf1.datas = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Sconf1.bits.ENPCH = EEPROM_309data.Sconf1.bits.bit0; N data_309_A.EEPROMWriRev_309.Sconf1.bits.ENMOS = EEPROM_309data.Sconf1.bits.bit1; N data_309_A.EEPROMWriRev_309.Sconf1.bits.OCPM = EEPROM_309data.Sconf1.bits.bit2; N data_309_A.EEPROMWriRev_309.Sconf1.bits.BAL = EEPROM_309data.Sconf1.bits.bit3; N data_309_A.EEPROMWriRev_309.Sconf2.bits.DIS_PF = EEPROM_309data.Sconf1.bits.bit4; N data_309_A.EEPROMWriRev_309.Sconf2.bits.E0VB = EEPROM_309data.Sconf1.bits.bit5; N data_309_A.EEPROMWriRev_309.Sconf2.bits.OCRA = EEPROM_309data.Sconf1.bits.bit6; N data_309_A.EEPROMWriRev_309.Sconf2.bits.EUVR = EEPROM_309data.Sconf1.bits.bit7; N data_309_A.EEPROMWriRev_309.Sconf2.bits.UV_OP = EEPROM_309data.Sconf1.bits.bit8; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Sconf1.datas; N send_309_buf_A[1]=data_309_A.EEPROMWriRev_309.Sconf2.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Sconf1.datas; N send_309_buf_B[1]=data_309_A.EEPROMWriRev_309.Sconf2.datas; N addr_309 = EEPROM_SCONF1; X addr_309 = 0x00; N len_309 = 2; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_SCONF2: X case 0x01: N EEPROM_309data.Sconf2.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.LDRT1_0 = EEPROM_309data.Sconf2.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas >> 8; N send_309_buf_A[1]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas >> 8; N send_309_buf_B[1]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N addr_309 = EEPROM_OVH_OVL; X addr_309 = 0x02; N len_309 = 2; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_SCONF3: X case 0x02: N EEPROM_309data.Sconf3.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Sconf2.bits.CTLC1_0 = EEPROM_309data.Sconf3.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Sconf2.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Sconf2.datas; N addr_309 = EEPROM_SCONF2; X addr_309 = 0x01; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OV: X case 0x03: N EEPROM_309data.ycGVol = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Pfv = EEPROM_309data.ycGVol / 20; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Pfv; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Pfv; N addr_309 = EEPROM_PFV; X addr_309 = 0x0b; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OVTIME: X case 0x04: N EEPROM_309data.ycGVolTime.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.PFT1_0 = EEPROM_309data.ycGVolTime.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N addr_309 = EEPROM_MOST; X addr_309 = 0x10; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_GOV: X case 0x05: N EEPROM_309data.GVol = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OV9_0 = EEPROM_309data.GVol / 5; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas >> 8; N send_309_buf_A[1]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas >> 8; N send_309_buf_B[1]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N addr_309 = EEPROM_OVH_OVL; X addr_309 = 0x02; N len_309 = 2; N Rw309_Flag = 1; N N N break; N case DATA_EEPROM_GOVTIME: X case 0x06: N EEPROM_309data.GVolTime.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OVT3_0 = EEPROM_309data.GVolTime.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas >> 8; N send_309_buf_A[1]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas >> 8; N send_309_buf_B[1]=data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N addr_309 = EEPROM_OVH_OVL; X addr_309 = 0x02; N len_309 = 2; N Rw309_Flag = 1; N N N break; N case DATA_EEPROM_GOVSF: X case 0x07: N EEPROM_309data.GVolSf = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.OVR9_0 = EEPROM_309data.GVolSf / 5; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas >> 8; N send_309_buf_A[1]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas >> 8; N send_309_buf_B[1]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas; N addr_309 = EEPROM_OVRH_OVRL; X addr_309 = 0x04; N len_309 = 2; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_BALV: X case 0x08: N EEPROM_309data.Balv = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Balv = EEPROM_309data.Balv / 20; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Balv; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Balv; N addr_309 = EEPROM_BALV; X addr_309 = 0x08; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_QOVSF: X case 0x09: N EEPROM_309data.QVolSf = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Uvr = EEPROM_309data.QVolSf / 20; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Uvr; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Uvr; N addr_309 = EEPROM_UVR; X addr_309 = 0x07; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_QOV: X case 0x0A: N EEPROM_309data.QVol = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Uv = EEPROM_309data.QVol / 20; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Uv; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Uv; N addr_309 = EEPROM_UV; X addr_309 = 0x06; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_QOVTIME: X case 0x0B: N EEPROM_309data.QVolTime.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.UVT3_0 = EEPROM_309data.QVolTime.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas >> 8; N send_309_buf_A[1]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas >> 8; N send_309_buf_B[1]=data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas; N addr_309 = EEPROM_OVRH_OVRL; X addr_309 = 0x04; N len_309 = 2; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_YCVOL: X case 0x0C: N EEPROM_309data.Prev = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Prev = EEPROM_309data.Prev / 20; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Prev; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Prev; N addr_309 = EEPrOM_PREV; X addr_309 = 0x09; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_DVOL: X case 0x0D: N EEPROM_309data.Lovstop = (swj_buf.gps_Rev_buf[12] << 8) | swj_buf.gps_Rev_buf[13]; N data_309_A.EEPROMWriRev_309.Lov = EEPROM_309data.Lovstop / 20; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Lov; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Lov; N addr_309 = EEPROM_LOV; X addr_309 = 0x0a; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_COJCVOL: X case 0x0E: N EEPROM_309data.ChgOut_Vol.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.CHS1_0 = EEPROM_309data.ChgOut_Vol.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N addr_309 = EEPROM_MOST; X addr_309 = 0x10; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OCD1_VOL: X case 0x0F: N EEPROM_309data.Ocd1V_ocd1t.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.OCD1V3_0 = EEPROM_309data.Ocd1V_ocd1t.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas; N addr_309 = EEPROM_OCD1V_OCD1T; X addr_309 = 0x0c; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OCD1_TIME: X case 0x10: N EEPROM_309data.Ocd1V_ocd1t_Time.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.CD1T3_0 = EEPROM_309data.Ocd1V_ocd1t_Time.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas; N addr_309 = EEPROM_OCD1V_OCD1T; X addr_309 = 0x0c; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OCD2_VOL: X case 0x11: N EEPROM_309data.Ocd2V_ocd2t.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2V3_0 = EEPROM_309data.Ocd2V_ocd2t.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats; N addr_309 = EEPROM_OCD2V_OCD2T; X addr_309 = 0x0d; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OCD2_TIME: X case 0x12: N EEPROM_309data.Ocd2V_ocd2t_Time.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2T3_0 = EEPROM_309data.Ocd2V_ocd2t_Time.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats; N addr_309 = EEPROM_OCD2V_OCD2T; X addr_309 = 0x0d; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_DLUVOL: X case 0x13: N EEPROM_309data.Scv_sct.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCV_3_0 = EEPROM_309data.Scv_sct.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Scv_sct.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Scv_sct.datas; N addr_309 = EEPROM_SCV_SCT; X addr_309 = 0x0e; N len_309 = 1; N Rw309_Flag = 1; N N N break; N case DATA_EEPROM_DLUVOL_TIME: X case 0x14: N EEPROM_309data.Scv_sct_Time.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCT3_0 = EEPROM_309data.Scv_sct_Time.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Scv_sct.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Scv_sct.datas; N addr_309 = EEPROM_SCV_SCT; X addr_309 = 0x0e; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_CHG_CURR: X case 0x15: N EEPROM_309data.Occv_occt.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCV3_0 = EEPROM_309data.Occv_occt.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Occv_occt.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Occv_occt.datas; N addr_309 = EEPROM_OCCV_OCCT; X addr_309 = 0x0f; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_CHG_TIME: X case 0x16: N EEPROM_309data.Occv_occt_Time.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCT3_0 = EEPROM_309data.Occv_occt_Time.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Occv_occt.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Occv_occt.datas; N addr_309 = EEPROM_OCCV_OCCT; X addr_309 = 0x0f; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_CHG_MOS: X case 0x17: N EEPROM_309data.ChgMos_Time.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.MOST1_0 = EEPROM_309data.ChgMos_Time.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N addr_309 = EEPROM_MOST; X addr_309 = 0x10; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEProM_GCURRZ: X case 0x18: N EEPROM_309data.GCurr_Time.datas = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.OCRT1_0 = EEPROM_309data.GCurr_Time.datas; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N addr_309 = EEPROM_MOST; X addr_309 = 0x10; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OTC: X case 0x19: N //////////////////////////////////////////////////////////////////////////////////////////////// N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N EEPROM_309data.Otc = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Otc = Ntc_ad(EEPROM_309data.Otc) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otc)); N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Otc; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Otc; N addr_309 = EEPROM_OTC; X addr_309 = 0x11; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OTCR: X case 0x1A: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Otcr = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Otcr = Ntc_ad(EEPROM_309data.Otcr) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otcr)); N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Otcr; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Otcr; N addr_309 = EEPROM_OTCR; X addr_309 = 0x12; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_UTC: X case 0x1B: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Utc = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Utc = (Ntc_ad(EEPROM_309data.Utc) / (Rref + Ntc_ad(EEPROM_309data.Utc)) - 0.5) * 512.0; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Utc; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Utc; N addr_309 = EEPROM_UTC; X addr_309 = 0x13; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_UTCR: X case 0x1C: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Utcr = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Utcr = (Ntc_ad(EEPROM_309data.Utcr) / (Rref + Ntc_ad(EEPROM_309data.Utcr)) - 0.5) * 512.0; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Utcr; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Utcr; N addr_309 = EEPROM_UTCR; X addr_309 = 0x14; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OTD: X case 0x1D: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Otd = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Otd = Ntc_ad(EEPROM_309data.Otd) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otd)); N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Otd; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Otd; N addr_309 = EEPROM_OTD; X addr_309 = 0x15; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_OTDR: X case 0x1E: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Otdr = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Otdr = Ntc_ad(EEPROM_309data.Otdr) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otdr)); N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Otdr; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Otdr; N addr_309 = EEPROM_OTDR; X addr_309 = 0x16; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_UTD: X case 0x1F: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Utd = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Utd = (Ntc_ad(EEPROM_309data.Utd) / (Rref + Ntc_ad(EEPROM_309data.Utd)) - 0.5) * 512.0; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Utd; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Utd; N addr_309 = EEPROM_UTD; X addr_309 = 0x17; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_UTDR: X case 0x20: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N EEPROM_309data.Utdr = swj_buf.gps_Rev_buf[12]; N data_309_A.EEPROMWriRev_309.Utdr = (Ntc_ad(EEPROM_309data.Utdr) / (Rref + Ntc_ad(EEPROM_309data.Utdr)) - 0.5) * 512.0; N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Utdr; N send_309_buf_B[0]=data_309_A.EEPROMWriRev_309.Utdr; N addr_309 = EEPROM_UTDR; X addr_309 = 0x18; N len_309 = 1; N Rw309_Flag = 1; N N break; N case DATA_EEPROM_NTCX: X case 0x21: N EEPROM_309data.NTC_x = swj_buf.gps_Rev_buf[12]; //保留 N Rw309_Flag = 1; N break; N case DATA_EEPROM_JPGN: X case 0x22: N EEPROM_309data.cpdata = swj_buf.gps_Rev_buf[12];//保留 N Rw309_Flag = 1; N break; N case DATA_EEPROM_CELLTYPE: X case 0x23: N EEPROM_309data.cell_type = swj_buf.gps_Rev_buf[12];//保留 N Rw309_Flag = 1; N break; N case DATA_EEPROM_CELLNUM: X case 0x24: N EEPROM_309data.Cell_Num = swj_buf.gps_Rev_buf[12]; N N if(Conf_309num==1) N { N if(EEPROM_309data.Cell_Num >= 16) N EEPROM_309data.Cell_Num = 0; N data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 = EEPROM_309data.Cell_Num; N } N else if(Conf_309num==2) N { N data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 = 9; N data_309_B.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 = EEPROM_309data.Cell_Num - 9; N } N N send_309_buf_A[0]=data_309_A.EEPROMWriRev_309.Sconf1.datas; N send_309_buf_B[0]=data_309_B.EEPROMWriRev_309.Sconf1.datas; N addr_309 = EEPROM_SCONF1; X addr_309 = 0x00; N len_309 = 1; N Rw309_Flag = 1; N N break; N default: N /*MCU数据*/ N if(Ranjianyinjian == 0) W "..\user\src\swj.c" 794 10 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(swj_buf.gps_Rev_buf,data_len+2); N break; N } N N if(Rw309_Flag == 1) N { N /*写单个309EEPRO数据*/ N if(Conf_309num==1) N { E "..\user\src\swj.c" 803 16 identifier "VPOR_A" is undefined N SETIO(VPOR_A); N Delay_ms(100); N MTPWrite_fun_1(addr_309, len_309, &send_309_buf_A[0]); N ResetAFE_1(); N RESETIO(VPOR_A); X ((*VPOR_A . outputIO) &= (~VPOR_A . validBit)); N } N else if(Conf_309num==2) N { E "..\user\src\swj.c" 811 9 identifier "VPOR_A" is undefined N SETIO(VPOR_A); E "..\user\src\swj.c" 812 9 identifier "VPOR_B" is undefined N SETIO(VPOR_B); N Delay_ms(100); N MTPWrite_fun_1(addr_309, len_309, &send_309_buf_A[0]); N ResetAFE_1(); N MTPWrite_fun_2(addr_309, len_309, &send_309_buf_B[0]); N ResetAFE_2(); N RESETIO(VPOR_A); X ((*VPOR_A . outputIO) &= (~VPOR_A . validBit)); N RESETIO(VPOR_B); X ((*VPOR_B . outputIO) &= (~VPOR_B . validBit)); N } N N Rw309_Flag = 0; N sendbuffer[0] = b_addr; N send_len = 1; W "..\user\src\swj.c" 825 8 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(start_orde,22); //发送给MCU开始对309读写 N /*发送数据*/ N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N } N Beep_Flag = 1; N } N break; N case REV_ORDE: //读指令 X case 0x03: N if(Activate == 1) N { N Type = 0x01; //读数据应答 N memset(sendbuffer,0,sizeof(sendbuffer)); //数据清零 N N /*判断是否为读写309地址*/ N if(b_addr <= 0x6f) N { W "..\user\src\swj.c" 841 9 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(stop_orde,22); //发送给MCU停止对309读写 N Delay_ms(100); N } N N switch(b_addr) N { N /*读单个309EEPROM数据*/ N case DATA_EEPROM_SCONF1: X case 0x00: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_SCONF1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N data_309_A.EEPROMWriRev_309.Sconf2.datas = Rev_309_buf_A[1]; N N EEPROM_309data.Sconf1.bits.bit0 = data_309_A.EEPROMWriRev_309.Sconf1.bits.ENPCH; N EEPROM_309data.Sconf1.bits.bit1 = data_309_A.EEPROMWriRev_309.Sconf1.bits.ENMOS; N EEPROM_309data.Sconf1.bits.bit2 = data_309_A.EEPROMWriRev_309.Sconf1.bits.OCPM; N EEPROM_309data.Sconf1.bits.bit3 = data_309_A.EEPROMWriRev_309.Sconf1.bits.BAL; N EEPROM_309data.Sconf1.bits.bit4 = data_309_A.EEPROMWriRev_309.Sconf2.bits.DIS_PF; N EEPROM_309data.Sconf1.bits.bit5 = data_309_A.EEPROMWriRev_309.Sconf2.bits.E0VB; N EEPROM_309data.Sconf1.bits.bit6 = data_309_A.EEPROMWriRev_309.Sconf2.bits.OCRA; N EEPROM_309data.Sconf1.bits.bit7 = data_309_A.EEPROMWriRev_309.Sconf2.bits.EUVR; N EEPROM_309data.Sconf1.bits.bit8 = data_309_A.EEPROMWriRev_309.Sconf2.bits.UV_OP; N N sendbuffer[1] = EEPROM_309data.Sconf1.datas >> 8; N sendbuffer[2] = EEPROM_309data.Sconf1.datas; N send_len = 3; N N break; N case DATA_EEPROM_SCONF2: X case 0x01: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OVH_OVL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x02, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovh_ovl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N N EEPROM_309data.Sconf2.datas = data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.LDRT1_0; N N sendbuffer[1] = EEPROM_309data.Sconf2.datas; N send_len = 2; N N break; N case DATA_EEPROM_SCONF3: X case 0x02: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_SCONF2, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x01, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf2.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Sconf3.datas = data_309_A.EEPROMWriRev_309.Sconf2.bits.CTLC1_0; N N sendbuffer[1] = EEPROM_309data.Sconf3.datas; N send_len = 2; N N break; N case DATA_EEPROM_OV: X case 0x03: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_PFV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0b, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Pfv = Rev_309_buf_A[0]; N N EEPROM_309data.ycGVol = data_309_A.EEPROMWriRev_309.Pfv * 20; N N sendbuffer[1] = EEPROM_309data.ycGVol >> 8; N sendbuffer[2] = EEPROM_309data.ycGVol; N send_len = 3; N N break; N case DATA_EEPROM_OVTIME: X case 0x04: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.PFT1_0 = Rev_309_buf_A[0]; N N EEPROM_309data.ycGVolTime.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.PFT1_0; N N sendbuffer[1] = EEPROM_309data.ycGVolTime.datas; N send_len = 2; N N break; N case DATA_EEPROM_GOV: X case 0x05: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OVH_OVL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x02, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovh_ovl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N N EEPROM_309data.GVol = data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OV9_0 * 5; N N sendbuffer[1] = EEPROM_309data.GVol >> 8; N sendbuffer[2] = EEPROM_309data.GVol; N send_len = 3; N N break; N case DATA_EEPROM_GOVTIME: X case 0x06: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OVH_OVL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x02, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovh_ovl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N N EEPROM_309data.GVolTime.datas = data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OVT3_0; N N sendbuffer[1] = EEPROM_309data.GVolTime.datas; N send_len = 2; N N break; N case DATA_EEPROM_GOVSF: X case 0x07: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OVRH_OVRL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x04, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N N EEPROM_309data.GVolSf = data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.OVR9_0 * 5; N N sendbuffer[1] = EEPROM_309data.GVolSf >> 8; N sendbuffer[2] = EEPROM_309data.GVolSf; N send_len = 3; N N break; N case DATA_EEPROM_BALV: X case 0x08: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_BALV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x08, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Balv = Rev_309_buf_A[0]; N N EEPROM_309data.Balv = data_309_A.EEPROMWriRev_309.Balv * 20; N N sendbuffer[1] = EEPROM_309data.Balv >> 8; N sendbuffer[2] = EEPROM_309data.Balv; N send_len = 3; N N break; N case DATA_EEPROM_QOVSF: X case 0x09: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_UVR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x07, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Uvr = Rev_309_buf_A[0]; N N EEPROM_309data.QVolSf = data_309_A.EEPROMWriRev_309.Uvr * 20; N N sendbuffer[1] = EEPROM_309data.QVolSf >> 8; N sendbuffer[2] = EEPROM_309data.QVolSf; N send_len = 3; N N break; N case DATA_EEPROM_QOV: X case 0x0A: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_UV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x06, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Uv = Rev_309_buf_A[0]; N N EEPROM_309data.QVol = data_309_A.EEPROMWriRev_309.Uv * 20; N N sendbuffer[1] = EEPROM_309data.QVol >> 8; N sendbuffer[2] = EEPROM_309data.QVol; N send_len = 3; N N break; N case DATA_EEPROM_QOVTIME: X case 0x0B: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OVRH_OVRL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x04, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas = Rev_309_buf_A[0]<<8 | Rev_309_buf_A[1]; N N EEPROM_309data.QVolTime.datas = data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.UVT3_0; N N sendbuffer[1] = EEPROM_309data.QVolTime.datas; N send_len = 2; N N break; N case DATA_EEPROM_YCVOL: X case 0x0C: N Rw309_Flag = 1; N MTPRead_fun_1( EEPrOM_PREV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x09, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Prev = Rev_309_buf_A[0]; N N EEPROM_309data.Prev = data_309_A.EEPROMWriRev_309.Prev * 20; N N sendbuffer[1] = EEPROM_309data.Prev >> 8; N sendbuffer[2] = EEPROM_309data.Prev; N send_len = 3; N N break; N case DATA_EEPROM_DVOL: X case 0x0D: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_LOV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0a, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Lov = Rev_309_buf_A[0]; N N EEPROM_309data.Lovstop = data_309_A.EEPROMWriRev_309.Lov * 20; N N sendbuffer[1] = EEPROM_309data.Lovstop >> 8; N sendbuffer[2] = EEPROM_309data.Lovstop; N send_len = 3; N N break; N case DATA_EEPROM_COJCVOL: X case 0x0E: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas = Rev_309_buf_A[0]; N N EEPROM_309data.ChgOut_Vol.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.CHS1_0; N N sendbuffer[1] = EEPROM_309data.ChgOut_Vol.datas; N send_len = 2; N N break; N case DATA_EEPROM_OCD1_VOL: X case 0x0F: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OCD1V_OCD1T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0c, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Ocd1V_ocd1t.datas = data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.OCD1V3_0; N N sendbuffer[1] = EEPROM_309data.Ocd1V_ocd1t.datas; N send_len = 2; N N break; N case DATA_EEPROM_OCD1_TIME: X case 0x10: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OCD1V_OCD1T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0c, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Ocd1V_ocd1t_Time.datas = data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.CD1T3_0; N N sendbuffer[1] = EEPROM_309data.Ocd1V_ocd1t_Time.datas; N send_len = 2; N N break; N case DATA_EEPROM_OCD2_VOL: X case 0x11: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OCD2V_OCD2T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0d, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats = Rev_309_buf_A[0]; N N EEPROM_309data.Ocd2V_ocd2t.datas = data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2V3_0; N N sendbuffer[1] = EEPROM_309data.Ocd2V_ocd2t.datas; N send_len = 2; N N break; N case DATA_EEPROM_OCD2_TIME: X case 0x12: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OCD2V_OCD2T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0d, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats = Rev_309_buf_A[0]; N N EEPROM_309data.Ocd2V_ocd2t_Time.datas = data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2T3_0; N N sendbuffer[1] = EEPROM_309data.Ocd2V_ocd2t_Time.datas; N send_len = 2; N N break; N case DATA_EEPROM_DLUVOL: X case 0x13: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_SCV_SCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0e, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Scv_sct.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Scv_sct.datas = data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCV_3_0; N N sendbuffer[1] = EEPROM_309data.Scv_sct.datas; N send_len = 2; N N break; N case DATA_EEPROM_DLUVOL_TIME: X case 0x14: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_SCV_SCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0e, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Scv_sct.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Scv_sct_Time.datas = data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCT3_0; N N sendbuffer[1] = EEPROM_309data.Scv_sct_Time.datas; N send_len = 2; N N break; N case DATA_EEPROM_CHG_CURR: X case 0x15: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OCCV_OCCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0f, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Occv_occt.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Occv_occt.datas = data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCV3_0; N N sendbuffer[1] = EEPROM_309data.Occv_occt.datas; N send_len = 2; N N break; N case DATA_EEPROM_CHG_TIME: X case 0x16: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OCCV_OCCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0f, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Occv_occt.datas = Rev_309_buf_A[0]; N N EEPROM_309data.Occv_occt_Time.datas = data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCT3_0; N N sendbuffer[1] = EEPROM_309data.Occv_occt_Time.datas; N send_len = 2; N N break; N case DATA_EEPROM_CHG_MOS: X case 0x17: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas = Rev_309_buf_A[0]; N N EEPROM_309data.ChgMos_Time.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.MOST1_0; N N sendbuffer[1] = EEPROM_309data.ChgMos_Time.datas; N send_len = 2; N N break; N case DATA_EEProM_GCURRZ: X case 0x18: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas = Rev_309_buf_A[0]; N N EEPROM_309data.GCurr_Time.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.OCRT1_0; N N sendbuffer[1] = EEPROM_309data.GCurr_Time.datas; N send_len = 2; N N break; N case DATA_EEPROM_OTC: X case 0x19: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OTC, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x11, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otc = Rev_309_buf_A[0]; N N EEPROM_309data.Otc = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otc * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otc)*1000)); X EEPROM_309data.Otc = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otc * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otc)*1000)); N N sendbuffer[1] = EEPROM_309data.Otc; N send_len = 2; N N break; N case DATA_EEPROM_OTCR: X case 0x1A: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OTCR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x12, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otcr = Rev_309_buf_A[0]; N N EEPROM_309data.Otcr = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otcr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otcr)*1000)); X EEPROM_309data.Otcr = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otcr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otcr)*1000)); N N sendbuffer[1] = EEPROM_309data.Otcr; N send_len = 2; N N break; N case DATA_EEPROM_UTC: X case 0x1B: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_UTC, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x13, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utc = Rev_309_buf_A[0]; N N EEPROM_309data.Utc = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utc+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utc)*1000)); X EEPROM_309data.Utc = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utc+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utc)*1000)); N N sendbuffer[1] = EEPROM_309data.Utc; N send_len = 2; N N break; N case DATA_EEPROM_UTCR: X case 0x1C: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_UTCR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x14, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utcr = Rev_309_buf_A[0]; N N EEPROM_309data.Utcr = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utcr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utcr)*1000)); X EEPROM_309data.Utcr = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utcr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utcr)*1000)); N N sendbuffer[1] = EEPROM_309data.Utcr; N send_len = 2; N N break; N case DATA_EEPROM_OTD: X case 0x1D: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OTD, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x15, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otd = Rev_309_buf_A[0]; N N EEPROM_309data.Otd = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otd * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otd)*1000)); X EEPROM_309data.Otd = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otd * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otd)*1000)); N N sendbuffer[1] = EEPROM_309data.Otd; N send_len = 2; N N break; N case DATA_EEPROM_OTDR: X case 0x1E: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_OTDR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x16, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otdr = Rev_309_buf_A[0]; N N EEPROM_309data.Otdr = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otdr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otdr)*1000)); X EEPROM_309data.Otdr = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otdr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otdr)*1000)); N N sendbuffer[1] = EEPROM_309data.Otdr; N send_len = 2; N N break; N case DATA_EEPROM_UTD: X case 0x1F: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_UTD, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x17, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utd = Rev_309_buf_A[0]; N N EEPROM_309data.Utd = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utd+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utd)*1000)); X EEPROM_309data.Utd = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utd+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utd)*1000)); N N sendbuffer[1] = EEPROM_309data.Utd; N send_len = 2; N N break; N case DATA_EEPROM_UTDR: X case 0x20: N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_UTDR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x18, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utdr = Rev_309_buf_A[0]; N N EEPROM_309data.Utdr = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utdr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utdr)*1000)); X EEPROM_309data.Utdr = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utdr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utdr)*1000)); N N sendbuffer[1] = EEPROM_309data.Utdr; N send_len = 2; N N break; N case DATA_EEPROM_NTCX: X case 0x21: N Rw309_Flag = 1; N sendbuffer[1] = EEPROM_309data.NTC_x; N send_len = 2; N break; N case DATA_EEPROM_JPGN: X case 0x22: N Rw309_Flag = 1; N sendbuffer[1] = EEPROM_309data.cpdata; N send_len = 2; N break; N case DATA_EEPROM_CELLTYPE: X case 0x23: N Rw309_Flag = 1; N if(EEPROM_309data.GVol >= 4000) N EEPROM_309data.cell_type = 1; N else if(EEPROM_309data.GVol >= 3450) N EEPROM_309data.cell_type = 0; N else N EEPROM_309data.cell_type = 2; N sendbuffer[1] = EEPROM_309data.cell_type; N send_len = 2; N break; N case DATA_EEPROM_CELLNUM: X case 0x24: N Rw309_Flag = 1; N if(Conf_309num==1) N { N MTPRead_fun_1( EEPROM_SCONF1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N EEPROM_309data.Cell_Num = data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0; N if(EEPROM_309data.Cell_Num<5) N EEPROM_309data.Cell_Num = 16; N } N else if(Conf_309num==2) N { N MTPRead_fun_1( EEPROM_SCONF1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N MTPRead_fun_2( EEPROM_SCONF1, 1, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x00, 1, &Rev_309_buf_B[0]); N data_309_B.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_B[0]; N EEPROM_309data.Cell_Num = data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 + data_309_B.EEPROMWriRev_309.Sconf1.bits.cn3_cn0; N } N N sendbuffer[1] = EEPROM_309data.Cell_Num; N send_len = 2; N N break; N N /*309RAM读单个数据*/ N case DATA_MTP_CONF: X case 0x30: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CONF, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x40, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Conf.datas = Rev_309_buf_A[0]; N N RAM_309data.Conf.datas = data_309_A.RAM_WrieRev_309.Conf.datas; N N sendbuffer[1] = RAM_309data.Conf.datas; N send_len = 2; N N break; N case DATA_MTP_BALANCEH: X case 0x31: N Rw309_Flag = 1; N if(Conf_309num==1) N { N MTPRead_fun_1( MTP_BALANCEH, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x41, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Balanceh_l.datas = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N RAM_309data.Balanceh_l.datas = 0; N RAM_309data.Balanceh_l.datas = data_309_A.RAM_WrieRev_309.Balanceh_l.datas; N } N else if(Conf_309num==2) N { N MTPRead_fun_1( MTP_BALANCEH, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x41, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Balanceh_l.datas = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N MTPRead_fun_2( MTP_BALANCEH, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x41, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Balanceh_l.datas = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N MTPRead_fun_1( EEPROM_SCONF1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N RAM_309data.Balanceh_l.datas = 0; N RAM_309data.Balanceh_l.datas = (data_309_B.RAM_WrieRev_309.Balanceh_l.datas << data_309_A.EEPROMWriRev_309.Sconf1.datas) | data_309_A.RAM_WrieRev_309.Balanceh_l.datas; N } N N sendbuffer[1] = RAM_309data.Balanceh_l.datas >> 24; N sendbuffer[2] = RAM_309data.Balanceh_l.datas >> 16; N sendbuffer[3] = RAM_309data.Balanceh_l.datas >> 8; N sendbuffer[4] = RAM_309data.Balanceh_l.datas; N send_len = 5; N N break; N case DATA_MTP_BSTATUS1: X case 0x32: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_BSTATUS1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x43, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus1.datas = Rev_309_buf_A[0]; N N RAM_309data.Bstrtus1.datas = data_309_A.RAM_WrieRev_309.Bstrtus1.datas; N N sendbuffer[1] = RAM_309data.Bstrtus1.datas; N send_len = 2; N N break; N case DATA_MTP_BSTATUS2: X case 0x33: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_BSTATUS2, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x44, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus2.datas = Rev_309_buf_A[0]; N N RAM_309data.Bstrtus2.datas = data_309_A.RAM_WrieRev_309.Bstrtus2.datas; N N sendbuffer[1] = RAM_309data.Bstrtus2.datas; N send_len = 2; N N break; N case DATA_MTP_BSTATUS3: X case 0x34: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_BSTATUS3, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x45, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus3.datas = Rev_309_buf_A[0]; N N RAM_309data.Bstrtus3.datas = data_309_A.RAM_WrieRev_309.Bstrtus3.datas; N N sendbuffer[1] = RAM_309data.Bstrtus3.datas; N send_len = 2; N N break; N case DATA_MTP_TEMP1: X case 0x35: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_TEMP1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x46, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP1h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.TEMP1h_l = data_309_A.RAM_WrieRev_309.TEMP1h_l; N N sendbuffer[1] = RAM_309data.TEMP1h_l >> 8; N sendbuffer[2] = RAM_309data.TEMP1h_l; N send_len = 3; N N break; N case DATA_MTP_TEMP2: X case 0x36: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_TEMP2, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x48, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP2h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.TEMP2h_l = data_309_A.RAM_WrieRev_309.TEMP2h_l; N N sendbuffer[1] = RAM_309data.TEMP2h_l >> 8; N sendbuffer[2] = RAM_309data.TEMP2h_l; N send_len = 3; N N break; N case DATA_MTP_TEMP3: X case 0x37: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_TEMP3, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4A, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP3h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.TEMP3h_l = data_309_A.RAM_WrieRev_309.TEMP3h_l; N N sendbuffer[1] = RAM_309data.TEMP3h_l >> 8; N sendbuffer[2] = RAM_309data.TEMP3h_l; N send_len = 3; N N break; N case DATA_MTP_CUR: X case 0x38: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CUR, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4C, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Curh_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Curh_l = data_309_A.RAM_WrieRev_309.Curh_l; N N sendbuffer[1] = RAM_309data.Curh_l >> 8; N sendbuffer[2] = RAM_309data.Curh_l; N send_len = 3; N N break; N case DATA_MTP_CELL1: X case 0x39: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4E, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell1_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[0] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell1_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[0] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[0]; N send_len = 3; N N break; N case DATA_MTP_CELL2: X case 0x3A: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL2, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x50, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell2_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[1] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell2_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[1] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[1]; N send_len = 3; N N break; N case DATA_MTP_CELL3: X case 0x3B: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL3, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x52, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell3_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[2] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell3_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[2] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[2]; N send_len = 3; N N break; N case DATA_MTP_CELL4: X case 0x3C: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL4, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x54, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell4_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[3] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell4_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[3] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[3]; N send_len = 3; N N break; N case DATA_MTP_CELL5: X case 0x3D: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL5, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x56, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell5_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[4] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell5_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[4] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[4]; N send_len = 3; N N break; N case DATA_MTP_CELL6: X case 0x3E: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL6, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x58, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell6_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[5] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell6_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[5] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[5]; N send_len = 3; N N break; N case DATA_MTP_CELL7: X case 0x3F: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL7, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x5A, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell7_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[6] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell7_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[6] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[6]; N send_len = 3; N N break; N case DATA_MTP_CELL8: X case 0x40: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL8, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x5C, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell8_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[7] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell8_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[7] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[7]; N send_len = 3; N N break; N case DATA_MTP_CELL9: X case 0x41: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL9, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x5E, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell9_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell.cellvol[8] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell9_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[8] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[8]; N send_len = 3; N N break; N case DATA_MTP_CELL10: X case 0x42: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL1, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x4E, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell1_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[9] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell1_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[9] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[9]; N send_len = 3; N N break; N case DATA_MTP_CELL11: X case 0x43: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL2, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x50, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell2_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[10] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell2_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[10] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[10]; N send_len = 3; N N break; N case DATA_MTP_CELL12: X case 0x44: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL3, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x52, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell3_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[11] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell3_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[11] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[11]; N send_len = 3; N break; N case DATA_MTP_CELL13: X case 0x45: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL4, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x54, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell4_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[12] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell4_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[12] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[12]; N send_len = 3; N break; N case DATA_MTP_CELL14: X case 0x46: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL5, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x56, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell5_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[13] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell5_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[13] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[13]; N send_len = 3; N break; N case DATA_MTP_CELL15: X case 0x47: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL6, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x58, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell6_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[14] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell6_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[14] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[14]; N send_len = 3; N break; N case DATA_MTP_CELL16: X case 0x48: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL7, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x5A, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell7_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[15] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell7_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[15] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[15]; N send_len = 3; N break; N case DATA_MTP_CELL17: X case 0x49: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL8, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x5C, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell8_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[16] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell8_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[16] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[16]; N send_len = 3; N break; N case DATA_MTP_CELL18: X case 0x4A: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL9, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x5E, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell9_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[17] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell9_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[17] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[17]; N send_len = 3; N break; N case DATA_MTP_CELL19: X case 0x4B: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL10, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x60, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell10_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[18] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell10_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[18] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[18]; N send_len = 3; N break; N case DATA_MTP_CELL20: X case 0x4C: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL11, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x62, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell11_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell.cellvol[19] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell11_vol; N N sendbuffer[1] = RAM_309data.Cell.cellvol[19] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[19]; N send_len = 3; N break; N case DATA_MTP_CELL21: X case 0x4D: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell.cellvol[20] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[20]; N send_len = 3; N break; N case DATA_MTP_CELL22: X case 0x4E: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell.cellvol[21] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[21]; N send_len = 3; N break; N case DATA_MTP_CELL23: X case 0x4F: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell.cellvol[22] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[22]; N send_len = 3; N break; N case DATA_MTP_CELL24: X case 0x50: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell.cellvol[23] >> 8; N sendbuffer[2] = RAM_309data.Cell.cellvol[23]; N send_len = 3; N break; N case DATA_MTP_ADC2: X case 0x51: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_ADC2, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x6E, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.CADcdh_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.CADcdh_l = data_309_A.RAM_WrieRev_309.CADcdh_l; N N sendbuffer[1] = RAM_309data.CADcdh_l >> 8; N sendbuffer[2] = RAM_309data.CADcdh_l; N send_len = 3; N N break; N case DATA_MTP_BFLAG1: X case 0x52: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_BFLAG1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x70, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bflag1.datas = Rev_309_buf_A[0]; N N RAM_309data.Bflag1.datas = data_309_A.RAM_WrieRev_309.Bflag1.datas; N N sendbuffer[1] = RAM_309data.Bflag1.datas; N send_len = 2; N N break; N case DATA_MTP_BFLAG2: X case 0x53: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_BFLAG2, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x71, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bflag2.datas = Rev_309_buf_A[0]; N N RAM_309data.Bflag2.datas = data_309_A.RAM_WrieRev_309.Bflag2.datas; N N sendbuffer[1] = RAM_309data.Bflag2.datas; N send_len = 2; N N break; N case DATA_MTP_RSTSTAT: X case 0x54: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_RSTSTAT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x72, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Rststat.datas = Rev_309_buf_A[0]; N N RAM_309data.Rststat.datas = data_309_A.RAM_WrieRev_309.Rststat.datas; N N sendbuffer[1] = RAM_309data.Rststat.datas; N send_len = 2; N N break; N case DATA_MTP_TEMP1_NUM: X case 0x55: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N N MTPRead_fun_1( MTP_TEMP1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x46, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP1h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N Rt1 = (float)(data_309_A.RAM_WrieRev_309.TEMP1h_l * 1.0) /(float)(32768 - data_309_A.RAM_WrieRev_309.TEMP1h_l) * Rref; N RAM_309data.T1_tmp = Get_Temp((u32)(Rt1 * 1000)); X RAM_309data.T1_tmp = Get_Temp((unsigned int)(Rt1 * 1000)); N N sendbuffer[1] = RAM_309data.T1_tmp >> 8; N sendbuffer[2] = RAM_309data.T1_tmp; N send_len = 3; N N break; N case DATA_MTP_TEMP2_NUM: X case 0x56: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N N MTPRead_fun_1( MTP_TEMP2, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x48, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP2h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N Rt1 = (float)(data_309_A.RAM_WrieRev_309.TEMP2h_l * 1.0) /(float)(32768 - data_309_A.RAM_WrieRev_309.TEMP2h_l) * Rref; N RAM_309data.T2_tmp = Get_Temp((u32)(Rt1 * 1000)); X RAM_309data.T2_tmp = Get_Temp((unsigned int)(Rt1 * 1000)); N N sendbuffer[1] = RAM_309data.T2_tmp >> 8; N sendbuffer[2] = RAM_309data.T2_tmp; N send_len = 3; N N break; N case DATA_MTP_TEMP3_NUM: X case 0x57: N Rw309_Flag = 1; N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N N MTPRead_fun_1( MTP_TEMP3, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4A, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP3h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N Rt1 = (float)(data_309_A.RAM_WrieRev_309.TEMP3h_l * 1.0) /(float)(32768 - data_309_A.RAM_WrieRev_309.TEMP3h_l) * Rref; N RAM_309data.T3_tmp = Get_Temp((u32)(Rt1 * 1000)); X RAM_309data.T3_tmp = Get_Temp((unsigned int)(Rt1 * 1000)); N N sendbuffer[1] = RAM_309data.T3_tmp >> 8; N sendbuffer[2] = RAM_309data.T3_tmp; N send_len = 3; N N break; N case DATA_MTP_CELL1_NUM: X case 0x58: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4E, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell1_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[0] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell1_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[0] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[0]; N send_len = 3; N N break; N case DATA_MTP_CELL2_NUM: X case 0x59: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL2, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x50, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell2_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[1] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell2_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[1] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[1]; N send_len = 3; N N break; N case DATA_MTP_CELL3_NUM: X case 0x5A: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL3, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x52, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell3_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[2] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell3_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[2] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[2]; N send_len = 3; N N break; N case DATA_MTP_CELL4_NUM: X case 0x5B: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL4, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x54, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell4_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[3] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell4_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[3] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[3]; N send_len = 3; N N break; N case DATA_MTP_CELL5_NUM: X case 0x5C: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL5, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x56, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell5_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[4] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell5_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[4] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[4]; N send_len = 3; N N break; N case DATA_MTP_CELL6_NUM: X case 0x5D: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL6, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x58, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell6_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[5] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell6_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[5] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[5]; N send_len = 3; N N break; N case DATA_MTP_CELL7_NUM: X case 0x5E: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL7, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x5A, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell7_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[6] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell7_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[6] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[6]; N send_len = 3; N N break; N case DATA_MTP_CELL8_NUM: X case 0x5F: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL8, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x5C, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell8_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[7] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell8_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[7] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[7]; N send_len = 3; N N break; N case DATA_MTP_CELL9_NUM: X case 0x60: N Rw309_Flag = 1; N MTPRead_fun_1( MTP_CELL9, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x5E, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Cell.cellbits.cell9_vol = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N N RAM_309data.Cell_Num.cellvol[8] = data_309_A.RAM_WrieRev_309.Cell.cellbits.cell9_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[8] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[8]; N send_len = 3; N N break; N case DATA_MTP_CELL10_NUM: X case 0x61: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL1, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x4E, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell1_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[9] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell1_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[9] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[9]; N send_len = 3; N N break; N case DATA_MTP_CELL11_NUM: X case 0x62: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL2, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x50, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell2_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[10] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell2_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[10] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[10]; N send_len = 3; N N break; N case DATA_MTP_CELL12_NUM: X case 0x63: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL3, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x52, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell3_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[11] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell3_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[11] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[11]; N send_len = 3; N N break; N case DATA_MTP_CELL13_NUM: X case 0x64: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL4, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x54, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell4_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[12] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell4_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[12] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[12]; N send_len = 3; N N break; N case DATA_MTP_CELL14_NUM: X case 0x65: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL5, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x56, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell5_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[13] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell5_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[13] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[13]; N send_len = 3; N N break; N case DATA_MTP_CELL15_NUM: X case 0x66: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL6, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x58, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell6_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[14] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell6_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[14] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[14]; N send_len = 3; N N break; N case DATA_MTP_CELL16_NUM: X case 0x67: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL7, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x5A, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell7_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[15] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell7_vol / 6.403 ; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[15] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[15]; N send_len = 3; N N break; N case DATA_MTP_CELL17_NUM: X case 0x68: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL8, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x5C, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell8_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[16] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell8_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[16] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[16]; N send_len = 3; N N break; N case DATA_MTP_CELL18_NUM: X case 0x69: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL9, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x5E, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell9_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[17] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell9_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[17] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[17]; N send_len = 3; N N break; N case DATA_MTP_CELL19_NUM: X case 0x6A: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL10, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x60, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell10_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[18] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell10_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[18] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[18]; N send_len = 3; N N break; N case DATA_MTP_CELL20_NUM: X case 0x6B: N Rw309_Flag = 1; N MTPRead_fun_2( MTP_CELL11, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x62, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Cell.cellbits.cell11_vol = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N N RAM_309data.Cell_Num.cellvol[19] = data_309_B.RAM_WrieRev_309.Cell.cellbits.cell11_vol / 6.403; N N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[19] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[19]; N send_len = 3; N N break; N case DATA_MTP_CELL21_NUM: X case 0x6C: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[20] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[20]; N send_len = 3; N break; N case DATA_MTP_CELL22_NUM: X case 0x6D: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[21] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[21]; N send_len = 3; N break; N case DATA_MTP_CELL23_NUM: X case 0x6E: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[22] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[22]; N send_len = 3; N break; N case DATA_MTP_CELL24_NUM: X case 0x6F: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.Cell_Num.cellvol[23] >> 8; N sendbuffer[2] = RAM_309data.Cell_Num.cellvol[23]; N send_len = 3; N break; N case DATA_MTP_ZVOL: //总电压 X case 0x70: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.zvols >> 8; N sendbuffer[2] = RAM_309data.zvols; N send_len = 3; N break; N case DATA_MTP_VOLVC: //压差 X case 0x71: N Rw309_Flag = 1; N sendbuffer[1] = RAM_309data.volyc >> 8; N sendbuffer[2] = RAM_309data.volyc; N send_len = 3; N break; N default: N if(Ranjianyinjian == 0) W "..\user\src\swj.c" 2079 10 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(swj_buf.gps_Rev_buf,data_len+2); N break; N } N N if(Rw309_Flag == 1) N { N Rw309_Flag = 0; N sendbuffer[0] = b_addr; W "..\user\src\swj.c" 2087 9 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(start_orde,22); //发送给MCU开始对309读写 N /*发送数据*/ N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N } N Beep_Flag = 1; N } N break; N case CONF_ORDE: //控制选择指令_只写 X case 0x04: N switch(b_addr) N { N case RANJIANYINJIAN: X case 0xD0: N Ranjianyinjian = swj_buf.gps_Rev_buf[12]; N break; N case CONF_309NUM: X case 0xD1: N Conf_309num = swj_buf.gps_Rev_buf[12]; N break; N } N N sendbuffer[0] = b_addr; N send_len = 1; N /*发送数据*/ N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N Beep_Flag = 1; N break; N case PASS_ORDE: //对密码指令 X case 0x05: N N break; N case REV_ALLORDE: //读MCU全部指令 X case 0x06: N if(Activate == 1) N { N if(Ranjianyinjian == 0) N { W "..\user\src\swj.c" 2119 8 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(swj_buf.gps_Rev_buf,data_len+2); N Beep_Flag = 1; N } N } N break; N case WRI_ALLORDE: //写全部指令 X case 0x07: N if(Activate == 1) N { N if(Ranjianyinjian == 0) N { W "..\user\src\swj.c" 2129 8 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(swj_buf.gps_Rev_buf,data_len+2); N Beep_Flag = 1; N } N } N break; N case REV_309EEPROM: //读309EEPROM全部数据 X case 0x08: N if(Activate == 1) N { N// u32 temp = 0; W "..\user\src\swj.c" 2138 7 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(stop_orde,22); //发送给MCU停止对309读写 N Delay_ms(100); N N MTPRead_fun_1( EEPROM_SCONF1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N data_309_A.EEPROMWriRev_309.Sconf2.datas = Rev_309_buf_A[1]; N N EEPROM_309data.Sconf1.bits.bit0 = data_309_A.EEPROMWriRev_309.Sconf1.bits.ENPCH; N EEPROM_309data.Sconf1.bits.bit1 = data_309_A.EEPROMWriRev_309.Sconf1.bits.ENMOS; N EEPROM_309data.Sconf1.bits.bit2 = data_309_A.EEPROMWriRev_309.Sconf1.bits.OCPM; N EEPROM_309data.Sconf1.bits.bit3 = data_309_A.EEPROMWriRev_309.Sconf1.bits.BAL; N EEPROM_309data.Sconf1.bits.bit4 = data_309_A.EEPROMWriRev_309.Sconf2.bits.DIS_PF; N EEPROM_309data.Sconf1.bits.bit5 = data_309_A.EEPROMWriRev_309.Sconf2.bits.E0VB; N EEPROM_309data.Sconf1.bits.bit6 = data_309_A.EEPROMWriRev_309.Sconf2.bits.OCRA; N EEPROM_309data.Sconf1.bits.bit7 = data_309_A.EEPROMWriRev_309.Sconf2.bits.EUVR; N EEPROM_309data.Sconf1.bits.bit8 = data_309_A.EEPROMWriRev_309.Sconf2.bits.UV_OP; N N MTPRead_fun_1( EEPROM_OVH_OVL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x02, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovh_ovl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N EEPROM_309data.Sconf2.datas = data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.LDRT1_0; N N MTPRead_fun_1( EEPROM_SCONF2, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x01, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf2.datas = Rev_309_buf_A[0]; N EEPROM_309data.Sconf3.datas = data_309_A.EEPROMWriRev_309.Sconf2.bits.CTLC1_0; N N MTPRead_fun_1( EEPROM_PFV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0b, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Pfv = Rev_309_buf_A[0]; N EEPROM_309data.ycGVol = data_309_A.EEPROMWriRev_309.Pfv * 20; N N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.PFT1_0 = Rev_309_buf_A[0]; N EEPROM_309data.ycGVolTime.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.PFT1_0; N N MTPRead_fun_1( EEPROM_OVH_OVL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x02, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovh_ovl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N EEPROM_309data.GVol = data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OV9_0 * 5; N N MTPRead_fun_1( EEPROM_OVH_OVL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x02, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovh_ovl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N EEPROM_309data.GVolTime.datas = data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OVT3_0; N N MTPRead_fun_1( EEPROM_OVRH_OVRL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x04, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas = Rev_309_buf_A[0] << 8 | Rev_309_buf_A[1]; N EEPROM_309data.GVolSf = data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.OVR9_0 * 5; N N MTPRead_fun_1( EEPROM_BALV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x08, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Balv = Rev_309_buf_A[0]; N EEPROM_309data.Balv = data_309_A.EEPROMWriRev_309.Balv * 20; N N MTPRead_fun_1( EEPROM_UVR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x07, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Uvr = Rev_309_buf_A[0]; N EEPROM_309data.QVolSf = data_309_A.EEPROMWriRev_309.Uvr * 20; N N MTPRead_fun_1( EEPROM_UV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x06, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Uv = Rev_309_buf_A[0]; N EEPROM_309data.QVol = data_309_A.EEPROMWriRev_309.Uv * 20; N N MTPRead_fun_1( EEPROM_OVRH_OVRL, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x04, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas = Rev_309_buf_A[0]<<8 | Rev_309_buf_A[1]; N EEPROM_309data.QVolTime.datas = data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.UVT3_0; N N MTPRead_fun_1( EEPrOM_PREV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x09, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Prev = Rev_309_buf_A[0]; N EEPROM_309data.Prev = data_309_A.EEPROMWriRev_309.Prev * 20; N N MTPRead_fun_1( EEPROM_LOV, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0a, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Lov = Rev_309_buf_A[0]; N EEPROM_309data.Lovstop = data_309_A.EEPROMWriRev_309.Lov * 20; N N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas = Rev_309_buf_A[0]; N EEPROM_309data.ChgOut_Vol.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.CHS1_0; N N MTPRead_fun_1( EEPROM_OCD1V_OCD1T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0c, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas = Rev_309_buf_A[0]; N EEPROM_309data.Ocd1V_ocd1t.datas = data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.OCD1V3_0; N N MTPRead_fun_1( EEPROM_OCD1V_OCD1T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0c, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas = Rev_309_buf_A[0]; N EEPROM_309data.Ocd1V_ocd1t_Time.datas = data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.CD1T3_0; N N MTPRead_fun_1( EEPROM_OCD2V_OCD2T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0d, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats = Rev_309_buf_A[0]; N EEPROM_309data.Ocd2V_ocd2t.datas = data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2V3_0; N N MTPRead_fun_1( EEPROM_OCD2V_OCD2T, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0d, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats = Rev_309_buf_A[0]; N EEPROM_309data.Ocd2V_ocd2t_Time.datas = data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2T3_0; N N MTPRead_fun_1( EEPROM_SCV_SCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0e, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Scv_sct.datas = Rev_309_buf_A[0]; N EEPROM_309data.Scv_sct.datas = data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCV_3_0; N N MTPRead_fun_1( EEPROM_SCV_SCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0e, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Scv_sct.datas = Rev_309_buf_A[0]; N EEPROM_309data.Scv_sct_Time.datas = data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCT3_0; N N MTPRead_fun_1( EEPROM_OCCV_OCCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0f, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Occv_occt.datas = Rev_309_buf_A[0]; N EEPROM_309data.Occv_occt.datas = data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCV3_0; N N MTPRead_fun_1( EEPROM_OCCV_OCCT, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x0f, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Occv_occt.datas = Rev_309_buf_A[0]; N EEPROM_309data.Occv_occt_Time.datas = data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCT3_0; N N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas = Rev_309_buf_A[0]; N EEPROM_309data.ChgMos_Time.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.MOST1_0; N N MTPRead_fun_1( EEPROM_MOST, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x10, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas = Rev_309_buf_A[0]; N EEPROM_309data.GCurr_Time.datas = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.OCRT1_0; N N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N N MTPRead_fun_1( EEPROM_OTC, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x11, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otc = Rev_309_buf_A[0]; N EEPROM_309data.Otc = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otc * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otc)*1000.0)); X EEPROM_309data.Otc = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otc * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otc)*1000.0)); N// temp = (data_309_A.EEPROMWriRev_309.Otc * Rref)/(512-data_309_A.EEPROMWriRev_309.Otc)*1000.0; N// Send_byte_usart2(0xFF); N// Send_byte_usart2(temp>>24); N// Send_byte_usart2(temp>>16); N// Send_byte_usart2(temp>>8); N// Send_byte_usart2(temp); N// Send_byte_usart2(0xFF); N N MTPRead_fun_1( EEPROM_OTCR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x12, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otcr = Rev_309_buf_A[0]; N EEPROM_309data.Otcr = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otcr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otcr)*1000.0)); X EEPROM_309data.Otcr = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otcr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otcr)*1000.0)); N// temp = (data_309_A.EEPROMWriRev_309.Otcr * Rref)/(512-data_309_A.EEPROMWriRev_309.Otcr)*1000.0; N// Send_byte_usart2(0xFF); N// Send_byte_usart2(temp>>24); N// Send_byte_usart2(temp>>16); N// Send_byte_usart2(temp>>8); N// Send_byte_usart2(temp); N// Send_byte_usart2(0xFF); N N MTPRead_fun_1( EEPROM_UTC, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x13, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utc = Rev_309_buf_A[0]; N EEPROM_309data.Utc = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utc+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utc)*1000.0)); X EEPROM_309data.Utc = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utc+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utc)*1000.0)); N// temp = ((data_309_A.EEPROMWriRev_309.Utc+256) * Rref)/(256-data_309_A.EEPROMWriRev_309.Utc)*1000; N// Send_byte_usart2(0xFF); N// Send_byte_usart2(temp>>24); N// Send_byte_usart2(temp>>16); N// Send_byte_usart2(temp>>8); N// Send_byte_usart2(temp); N// Send_byte_usart2(0xFF); N N MTPRead_fun_1( EEPROM_UTCR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x14, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utcr = Rev_309_buf_A[0]; N EEPROM_309data.Utcr = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utcr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utcr)*1000.0)); X EEPROM_309data.Utcr = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utcr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utcr)*1000.0)); N N MTPRead_fun_1( EEPROM_OTD, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x15, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otd = Rev_309_buf_A[0]; N EEPROM_309data.Otd = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otd * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otd)*1000.0)); X EEPROM_309data.Otd = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otd * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otd)*1000.0)); N N MTPRead_fun_1( EEPROM_OTDR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x16, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Otdr = Rev_309_buf_A[0]; N EEPROM_309data.Otdr = ClacNTC((u32)((data_309_A.EEPROMWriRev_309.Otdr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otdr)*1000.0)); X EEPROM_309data.Otdr = ClacNTC((unsigned int)((data_309_A.EEPROMWriRev_309.Otdr * Rref)/(512.0-data_309_A.EEPROMWriRev_309.Otdr)*1000.0)); N N MTPRead_fun_1( EEPROM_UTD, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x17, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utd = Rev_309_buf_A[0]; N EEPROM_309data.Utd = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utd+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utd)*1000.0)); X EEPROM_309data.Utd = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utd+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utd)*1000.0)); N N MTPRead_fun_1( EEPROM_UTDR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x18, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Utdr = Rev_309_buf_A[0]; N EEPROM_309data.Utdr = ClacNTC((u32)(((data_309_A.EEPROMWriRev_309.Utdr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utdr)*1000.0)); X EEPROM_309data.Utdr = ClacNTC((unsigned int)(((data_309_A.EEPROMWriRev_309.Utdr+256.0) * Rref)/(256.0-data_309_A.EEPROMWriRev_309.Utdr)*1000.0)); N N if(Conf_309num==1) N { N MTPRead_fun_1( EEPROM_SCONF1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N EEPROM_309data.Cell_Num = data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0; N if(EEPROM_309data.Cell_Num<5) N EEPROM_309data.Cell_Num = 16; N } N else if(Conf_309num==2) N { N MTPRead_fun_1( EEPROM_SCONF1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N MTPRead_fun_2( EEPROM_SCONF1, 1, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x00, 1, &Rev_309_buf_B[0]); N data_309_B.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_B[0]; N EEPROM_309data.Cell_Num = data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 + data_309_B.EEPROMWriRev_309.Sconf1.bits.cn3_cn0; N } N N N Type = 0x01; //应答 N memset(sendbuffer,0,sizeof(sendbuffer)); //数据清零 N N sendbuffer[0] = DATA_EEPROM_SCONF1; X sendbuffer[0] = 0x00; N sendbuffer[1] = EEPROM_309data.Sconf1.datas>>8; N sendbuffer[2] = EEPROM_309data.Sconf1.datas; N N sendbuffer[3] = DATA_EEPROM_SCONF2; X sendbuffer[3] = 0x01; N sendbuffer[4] = EEPROM_309data.Sconf2.datas; N N sendbuffer[5] = DATA_EEPROM_SCONF3; X sendbuffer[5] = 0x02; N sendbuffer[6] = EEPROM_309data.Sconf3.datas; N N sendbuffer[7] = DATA_EEPROM_OV; X sendbuffer[7] = 0x03; N sendbuffer[8] = EEPROM_309data.ycGVol >> 8; N sendbuffer[9] = EEPROM_309data.ycGVol; N N sendbuffer[10] = DATA_EEPROM_OVTIME; X sendbuffer[10] = 0x04; N sendbuffer[11] = EEPROM_309data.ycGVolTime.datas; N N sendbuffer[12] = DATA_EEPROM_GOV; X sendbuffer[12] = 0x05; N sendbuffer[13] = EEPROM_309data.GVol >> 8; N sendbuffer[14] = EEPROM_309data.GVol; N N sendbuffer[15] = DATA_EEPROM_GOVTIME; X sendbuffer[15] = 0x06; N sendbuffer[16] = EEPROM_309data.GVolTime.datas; N N sendbuffer[17] = DATA_EEPROM_GOVSF; X sendbuffer[17] = 0x07; N sendbuffer[18] = EEPROM_309data.GVolSf >> 8; N sendbuffer[19] = EEPROM_309data.GVolSf; N N sendbuffer[20] = DATA_EEPROM_BALV; X sendbuffer[20] = 0x08; N sendbuffer[21] = EEPROM_309data.Balv >> 8; N sendbuffer[22] = EEPROM_309data.Balv; N N sendbuffer[23] = DATA_EEPROM_QOVSF; X sendbuffer[23] = 0x09; N sendbuffer[24] = EEPROM_309data.QVolSf >> 8; N sendbuffer[25] = EEPROM_309data.QVolSf; N N sendbuffer[26] = DATA_EEPROM_QOV; X sendbuffer[26] = 0x0A; N sendbuffer[27] = EEPROM_309data.QVol >> 8; N sendbuffer[28] = EEPROM_309data.QVol; N N sendbuffer[29] = DATA_EEPROM_QOVTIME; X sendbuffer[29] = 0x0B; N sendbuffer[30] = EEPROM_309data.QVolTime.datas; N N sendbuffer[31] = DATA_EEPROM_YCVOL; X sendbuffer[31] = 0x0C; N sendbuffer[32] = EEPROM_309data.Prev >> 8; N sendbuffer[33] = EEPROM_309data.Prev; N N sendbuffer[34] = DATA_EEPROM_DVOL; X sendbuffer[34] = 0x0D; N sendbuffer[35] = EEPROM_309data.Lovstop >> 8; N sendbuffer[36] = EEPROM_309data.Lovstop; N N sendbuffer[37] = DATA_EEPROM_COJCVOL; X sendbuffer[37] = 0x0E; N sendbuffer[38] = EEPROM_309data.ChgOut_Vol.datas; N N sendbuffer[39] = DATA_EEPROM_OCD1_VOL; X sendbuffer[39] = 0x0F; N sendbuffer[40] = EEPROM_309data.Ocd1V_ocd1t.datas; N sendbuffer[41] = DATA_EEPROM_OCD1_TIME; X sendbuffer[41] = 0x10; N sendbuffer[42] = EEPROM_309data.Ocd1V_ocd1t_Time.datas; N N sendbuffer[43] = DATA_EEPROM_OCD2_VOL; X sendbuffer[43] = 0x11; N sendbuffer[44] = EEPROM_309data.Ocd2V_ocd2t.datas; N N sendbuffer[45] = DATA_EEPROM_OCD2_TIME; X sendbuffer[45] = 0x12; N sendbuffer[46] = EEPROM_309data.Ocd2V_ocd2t_Time.datas; N N sendbuffer[47] = DATA_EEPROM_DLUVOL; X sendbuffer[47] = 0x13; N sendbuffer[48] = EEPROM_309data.Scv_sct.datas; N N sendbuffer[49] = DATA_EEPROM_DLUVOL_TIME; X sendbuffer[49] = 0x14; N sendbuffer[50] = EEPROM_309data.Scv_sct_Time.datas; N N sendbuffer[51] = DATA_EEPROM_CHG_CURR; X sendbuffer[51] = 0x15; N sendbuffer[52] = EEPROM_309data.Occv_occt.datas; N N sendbuffer[53] = DATA_EEPROM_CHG_TIME; X sendbuffer[53] = 0x16; N sendbuffer[54] = EEPROM_309data.Occv_occt_Time.datas; N N sendbuffer[55] = DATA_EEPROM_CHG_MOS; X sendbuffer[55] = 0x17; N sendbuffer[56] = EEPROM_309data.ChgMos_Time.datas; N N sendbuffer[57] = DATA_EEProM_GCURRZ; X sendbuffer[57] = 0x18; N sendbuffer[58] = EEPROM_309data.GCurr_Time.datas; N N sendbuffer[59] = DATA_EEPROM_OTC; X sendbuffer[59] = 0x19; N sendbuffer[60] = EEPROM_309data.Otc; N N sendbuffer[61] = DATA_EEPROM_OTCR; X sendbuffer[61] = 0x1A; N sendbuffer[62] = EEPROM_309data.Otcr; N N sendbuffer[63] = DATA_EEPROM_UTC; X sendbuffer[63] = 0x1B; N sendbuffer[64] = EEPROM_309data.Utc; N N sendbuffer[65] = DATA_EEPROM_UTCR; X sendbuffer[65] = 0x1C; N sendbuffer[66] = EEPROM_309data.Utcr; N N sendbuffer[67] = DATA_EEPROM_OTD; X sendbuffer[67] = 0x1D; N sendbuffer[68] = EEPROM_309data.Otd; N N sendbuffer[69] = DATA_EEPROM_OTDR; X sendbuffer[69] = 0x1E; N sendbuffer[70] = EEPROM_309data.Otdr; N N sendbuffer[71] = DATA_EEPROM_UTD; X sendbuffer[71] = 0x1F; N sendbuffer[72] = EEPROM_309data.Utd; N N sendbuffer[73] = DATA_EEPROM_UTDR; X sendbuffer[73] = 0x20; N sendbuffer[74] = EEPROM_309data.Utdr; N N sendbuffer[75] = DATA_EEPROM_NTCX; X sendbuffer[75] = 0x21; N sendbuffer[76] = EEPROM_309data.NTC_x; N N sendbuffer[77] = DATA_EEPROM_JPGN; X sendbuffer[77] = 0x22; N sendbuffer[78] = EEPROM_309data.cpdata; N N sendbuffer[79] = DATA_EEPROM_CELLTYPE; X sendbuffer[79] = 0x23; N if(EEPROM_309data.GVol >= 4000) N EEPROM_309data.cell_type = 1; N else if(EEPROM_309data.GVol >= 3450) N EEPROM_309data.cell_type = 0; N else N EEPROM_309data.cell_type = 2; N N sendbuffer[80] = EEPROM_309data.cell_type; N N sendbuffer[81] = DATA_EEPROM_CELLNUM; X sendbuffer[81] = 0x24; N sendbuffer[82] = EEPROM_309data.Cell_Num; N N send_len = 83; N N Send_TString_BMS(start_orde,22); //发送给MCU开始对309读写 N /*发送数据*/ N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N Beep_Flag = 1; N } N break; N N case WRI_309EEPROM: //写309全部数据 X case 0x09: N if(Activate == 1) N { N u16 temp = 0; X unsigned short temp = 0; N u8 Write_309buf[30]={0}; X unsigned char Write_309buf[30]={0}; N Type = 0x01; //应答 N memset(sendbuffer,0,sizeof(sendbuffer)); //数据清零 N W "..\user\src\swj.c" 2475 7 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(stop_orde,22); //发送给MCU停止对309读写 N Delay_ms(100); N N /*309EEPROM写数据*/ N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_SCONF1) X if(swj_buf.gps_Rev_buf[11+temp] == 0x00) N { N EEPROM_309data.Sconf1.datas = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Sconf1.bits.ENPCH = EEPROM_309data.Sconf1.bits.bit0; N data_309_A.EEPROMWriRev_309.Sconf1.bits.ENMOS = EEPROM_309data.Sconf1.bits.bit1; N data_309_A.EEPROMWriRev_309.Sconf1.bits.OCPM = EEPROM_309data.Sconf1.bits.bit2; N data_309_A.EEPROMWriRev_309.Sconf1.bits.BAL = EEPROM_309data.Sconf1.bits.bit3; N data_309_A.EEPROMWriRev_309.Sconf2.bits.DIS_PF = EEPROM_309data.Sconf1.bits.bit4; N data_309_B.EEPROMWriRev_309.Sconf1.bits.ENPCH = EEPROM_309data.Sconf1.bits.bit0; N data_309_B.EEPROMWriRev_309.Sconf1.bits.ENMOS = EEPROM_309data.Sconf1.bits.bit1; N data_309_B.EEPROMWriRev_309.Sconf1.bits.OCPM = EEPROM_309data.Sconf1.bits.bit2; N data_309_B.EEPROMWriRev_309.Sconf1.bits.BAL = EEPROM_309data.Sconf1.bits.bit3; N data_309_A.EEPROMWriRev_309.Sconf2.bits.DIS_PF = EEPROM_309data.Sconf1.bits.bit4; N data_309_A.EEPROMWriRev_309.Sconf2.bits.E0VB = EEPROM_309data.Sconf1.bits.bit5; N data_309_A.EEPROMWriRev_309.Sconf2.bits.OCRA = EEPROM_309data.Sconf1.bits.bit6; N data_309_A.EEPROMWriRev_309.Sconf2.bits.EUVR = EEPROM_309data.Sconf1.bits.bit7; N data_309_A.EEPROMWriRev_309.Sconf2.bits.UV_OP = EEPROM_309data.Sconf1.bits.bit8; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_SCONF2) X if(swj_buf.gps_Rev_buf[11+temp] == 0x01) N { N EEPROM_309data.Sconf2.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.LDRT1_0 = EEPROM_309data.Sconf2.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_SCONF3) X if(swj_buf.gps_Rev_buf[11+temp] == 0x02) N { N EEPROM_309data.Sconf3.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Sconf2.bits.CTLC1_0 = EEPROM_309data.Sconf3.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OV) X if(swj_buf.gps_Rev_buf[11+temp] == 0x03) N { N EEPROM_309data.ycGVol = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Pfv = EEPROM_309data.ycGVol / 20; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OVTIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x04) N { N EEPROM_309data.ycGVolTime.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.PFT1_0 = EEPROM_309data.ycGVolTime.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_GOV) X if(swj_buf.gps_Rev_buf[11+temp] == 0x05) N { N EEPROM_309data.GVol = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OV9_0 = EEPROM_309data.GVol / 5; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_GOVTIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x06) N { N EEPROM_309data.GVolTime.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ovh_ovl.bits.OVT3_0 = EEPROM_309data.GVolTime.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_GOVSF) X if(swj_buf.gps_Rev_buf[11+temp] == 0x07) N { N EEPROM_309data.GVolSf = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.OVR9_0 = EEPROM_309data.GVolSf / 5; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_BALV) X if(swj_buf.gps_Rev_buf[11+temp] == 0x08) N { N EEPROM_309data.Balv = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Balv = EEPROM_309data.Balv / 20; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_QOVSF) X if(swj_buf.gps_Rev_buf[11+temp] == 0x09) N { N EEPROM_309data.QVolSf = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Uvr = EEPROM_309data.QVolSf / 20; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_QOV) X if(swj_buf.gps_Rev_buf[11+temp] == 0x0A) N { N EEPROM_309data.QVol = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Uv = EEPROM_309data.QVol / 20; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_QOVTIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x0B) N { N EEPROM_309data.QVolTime.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ovrh_ovrl.bits.UVT3_0 = EEPROM_309data.QVolTime.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_YCVOL) X if(swj_buf.gps_Rev_buf[11+temp] == 0x0C) N { N EEPROM_309data.Prev = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Prev = EEPROM_309data.Prev / 20; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_DVOL) X if(swj_buf.gps_Rev_buf[11+temp] == 0x0D) N { N EEPROM_309data.Lovstop = (swj_buf.gps_Rev_buf[12+temp] << 8) | swj_buf.gps_Rev_buf[13+temp]; N data_309_A.EEPROMWriRev_309.Lov = EEPROM_309data.Lovstop / 20; N temp+=3; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_COJCVOL) X if(swj_buf.gps_Rev_buf[11+temp] == 0x0E) N { N EEPROM_309data.ChgOut_Vol.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.CHS1_0 = EEPROM_309data.ChgOut_Vol.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OCD1_VOL) X if(swj_buf.gps_Rev_buf[11+temp] == 0x0F) N { N EEPROM_309data.Ocd1V_ocd1t.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.OCD1V3_0 = EEPROM_309data.Ocd1V_ocd1t.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OCD1_TIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x10) N { N EEPROM_309data.Ocd1V_ocd1t_Time.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.bits.CD1T3_0 = EEPROM_309data.Ocd1V_ocd1t_Time.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OCD2_VOL) X if(swj_buf.gps_Rev_buf[11+temp] == 0x11) N { N EEPROM_309data.Ocd2V_ocd2t.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2V3_0 = EEPROM_309data.Ocd2V_ocd2t.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OCD2_TIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x12) N { N EEPROM_309data.Ocd2V_ocd2t_Time.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.bits.OCD2T3_0 = EEPROM_309data.Ocd2V_ocd2t_Time.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_DLUVOL) X if(swj_buf.gps_Rev_buf[11+temp] == 0x13) N { N EEPROM_309data.Scv_sct.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCV_3_0 = EEPROM_309data.Scv_sct.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_DLUVOL_TIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x14) N { N EEPROM_309data.Scv_sct_Time.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Scv_sct.bits.SCT3_0 = EEPROM_309data.Scv_sct_Time.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_CHG_CURR) X if(swj_buf.gps_Rev_buf[11+temp] == 0x15) N { N EEPROM_309data.Occv_occt.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCV3_0 = EEPROM_309data.Occv_occt.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_CHG_TIME) X if(swj_buf.gps_Rev_buf[11+temp] == 0x16) N { N EEPROM_309data.Occv_occt_Time.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Occv_occt.bits.OCCT3_0 = EEPROM_309data.Occv_occt_Time.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_CHG_MOS) X if(swj_buf.gps_Rev_buf[11+temp] == 0x17) N { N EEPROM_309data.ChgMos_Time.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.MOST1_0 = EEPROM_309data.ChgMos_Time.datas; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEProM_GCURRZ) X if(swj_buf.gps_Rev_buf[11+temp] == 0x18) N { N EEPROM_309data.GCurr_Time.datas = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Most_ocrt_pft.bits.OCRT1_0 = EEPROM_309data.GCurr_Time.datas; N temp+=2; N } N N //////////////////////////////////////////////////////////////////////////////////////////////// N /////////////////////////////////////////////////////////////////////////////////////// N /*温度转换*/ N MTPRead_fun_1( EEPROM_TR, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x19, 1, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Tr = Rev_309_buf_A[0]; N Rref = (6.8 + 0.05 * (float)(data_309_A.EEPROMWriRev_309.Tr&0x7f)); N ///////////////////////////////////////////////////////////////////////////////////////// N /////////////////////////////////////////////////////////////////////////////////////////////// N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OTC) X if(swj_buf.gps_Rev_buf[11+temp] == 0x19) N { N EEPROM_309data.Otc = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Otc = Ntc_ad(EEPROM_309data.Otc) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otc)); N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OTCR) X if(swj_buf.gps_Rev_buf[11+temp] == 0x1A) N { N EEPROM_309data.Otcr = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Otcr = Ntc_ad(EEPROM_309data.Otcr) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otcr)); N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_UTC) X if(swj_buf.gps_Rev_buf[11+temp] == 0x1B) N { N EEPROM_309data.Utc = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Utc = (Ntc_ad(EEPROM_309data.Utc) / (Rref + Ntc_ad(EEPROM_309data.Utc)) - 0.5) * 512.0; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_UTCR) X if(swj_buf.gps_Rev_buf[11+temp] == 0x1C) N { N EEPROM_309data.Utcr = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Utcr = (Ntc_ad(EEPROM_309data.Utcr) / (Rref + Ntc_ad(EEPROM_309data.Utcr)) - 0.5) * 512.0; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OTD) X if(swj_buf.gps_Rev_buf[11+temp] == 0x1D) N { N EEPROM_309data.Otd = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Otd = Ntc_ad(EEPROM_309data.Otd) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otd)); N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_OTDR) X if(swj_buf.gps_Rev_buf[11+temp] == 0x1E) N { N EEPROM_309data.Otdr = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Otdr = Ntc_ad(EEPROM_309data.Otdr) * 512.0 / (Rref + Ntc_ad(EEPROM_309data.Otdr)); N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_UTD) X if(swj_buf.gps_Rev_buf[11+temp] == 0x1F) N { N EEPROM_309data.Utd = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Utd = (Ntc_ad(EEPROM_309data.Utd) / (Rref + Ntc_ad(EEPROM_309data.Utd)) - 0.5) * 512.0; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_UTDR) X if(swj_buf.gps_Rev_buf[11+temp] == 0x20) N { N EEPROM_309data.Utdr = swj_buf.gps_Rev_buf[12+temp]; N data_309_A.EEPROMWriRev_309.Utdr = (Ntc_ad(EEPROM_309data.Utdr) / (Rref + Ntc_ad(EEPROM_309data.Utdr)) - 0.5) * 512.0; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_NTCX) X if(swj_buf.gps_Rev_buf[11+temp] == 0x21) N { N EEPROM_309data.NTC_x = swj_buf.gps_Rev_buf[12+temp]; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_JPGN) X if(swj_buf.gps_Rev_buf[11+temp] == 0x22) N { N EEPROM_309data.cpdata = swj_buf.gps_Rev_buf[12+temp]; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_CELLTYPE) X if(swj_buf.gps_Rev_buf[11+temp] == 0x23) N { N EEPROM_309data.cell_type = swj_buf.gps_Rev_buf[12+temp]; N temp+=2; N } N N if(swj_buf.gps_Rev_buf[11+temp] == DATA_EEPROM_CELLNUM) X if(swj_buf.gps_Rev_buf[11+temp] == 0x24) N { N EEPROM_309data.Cell_Num = swj_buf.gps_Rev_buf[12+temp]; N if(Conf_309num==1) N { N if(EEPROM_309data.Cell_Num >= 16) N EEPROM_309data.Cell_Num = 0; N data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 = EEPROM_309data.Cell_Num; N } N else if(Conf_309num==2) N { N data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 = 9; N data_309_B.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 = EEPROM_309data.Cell_Num - 9; N } N temp+=2; N } N N /*数据拷贝*/ N Write_309buf[0] = data_309_A.EEPROMWriRev_309.Sconf1.datas; N Write_309buf[1] = data_309_A.EEPROMWriRev_309.Sconf2.datas; N Write_309buf[2] = data_309_A.EEPROMWriRev_309.Ovh_ovl.datas>>8; N Write_309buf[3] = data_309_A.EEPROMWriRev_309.Ovh_ovl.datas; N Write_309buf[4] = data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas>>8; N Write_309buf[5] = data_309_A.EEPROMWriRev_309.Ovrh_ovrl.datas; N Write_309buf[6] = data_309_A.EEPROMWriRev_309.Uv; N Write_309buf[7] = data_309_A.EEPROMWriRev_309.Uvr; N Write_309buf[8] = data_309_A.EEPROMWriRev_309.Balv; N Write_309buf[9] = data_309_A.EEPROMWriRev_309.Prev; N Write_309buf[10] = data_309_A.EEPROMWriRev_309.Lov; N Write_309buf[11] = data_309_A.EEPROMWriRev_309.Pfv; N Write_309buf[12] = data_309_A.EEPROMWriRev_309.Ocd1V_ocd1t.datas; N Write_309buf[13] = data_309_A.EEPROMWriRev_309.Ocd2V_ocd2t.datats; N Write_309buf[14] = data_309_A.EEPROMWriRev_309.Scv_sct.datas; N Write_309buf[15] = data_309_A.EEPROMWriRev_309.Occv_occt.datas; N Write_309buf[16] = data_309_A.EEPROMWriRev_309.Most_ocrt_pft.datas; N Write_309buf[17] = data_309_A.EEPROMWriRev_309.Otc; N Write_309buf[18] = data_309_A.EEPROMWriRev_309.Otcr; N Write_309buf[19] = data_309_A.EEPROMWriRev_309.Utc; N Write_309buf[20] = data_309_A.EEPROMWriRev_309.Utcr; N Write_309buf[21] = data_309_A.EEPROMWriRev_309.Otd; N Write_309buf[22] = data_309_A.EEPROMWriRev_309.Otdr; N Write_309buf[23] = data_309_A.EEPROMWriRev_309.Utd; N Write_309buf[24] = data_309_A.EEPROMWriRev_309.Utdr; N N /*写多个309EEPRO数据*/ N if(Conf_309num==1) N { E "..\user\src\swj.c" 2796 8 identifier "VPOR_A" is undefined N SETIO(VPOR_A); N Delay_ms(100); N MTPWrite_fun_1(EEPROM_SCONF1, 25, &Write_309buf[0]); X MTPWrite_fun_1(0x00, 25, &Write_309buf[0]); N ResetAFE_1(); N RESETIO(VPOR_A); X ((*VPOR_A . outputIO) &= (~VPOR_A . validBit)); N } N else if(Conf_309num==2) N { E "..\user\src\swj.c" 2804 8 identifier "VPOR_A" is undefined N SETIO(VPOR_A); E "..\user\src\swj.c" 2805 8 identifier "VPOR_B" is undefined N SETIO(VPOR_B); N Delay_ms(100); N Write_309buf[0] = data_309_A.EEPROMWriRev_309.Sconf1.datas; N MTPWrite_fun_1(EEPROM_SCONF1, 25, &Write_309buf[0]); X MTPWrite_fun_1(0x00, 25, &Write_309buf[0]); N ResetAFE_1(); N Write_309buf[0] = data_309_B.EEPROMWriRev_309.Sconf1.datas; N MTPWrite_fun_2(EEPROM_SCONF1, 25, &Write_309buf[0]); X MTPWrite_fun_2(0x00, 25, &Write_309buf[0]); N ResetAFE_2(); N RESETIO(VPOR_A); X ((*VPOR_A . outputIO) &= (~VPOR_A . validBit)); N RESETIO(VPOR_B); X ((*VPOR_B . outputIO) &= (~VPOR_B . validBit)); N } N N N /*数据返回*/ N sendbuffer[0] = 0xFF; N send_len = 1; N Send_TString_BMS(start_orde,22); //发送给MCU开始对309读写 N /*发送数据*/ N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N Beep_Flag = 1; N } N break; N N case REV_309RAM: //读309RAM全部数据 X case 0x0A: N if(Activate == 1) N { N u32 sumVol = 0; X unsigned int sumVol = 0; N u16 cell_Vol_1[24]={0}; //电芯电压缓存 X unsigned short cell_Vol_1[24]={0}; N u16 cell_Vol_2[24]={0}; //电芯电压缓存 X unsigned short cell_Vol_2[24]={0}; N u16 cell_vol_max = 0; //最高电芯电压 X unsigned short cell_vol_max = 0; N u16 cell_vol_min = 0; //最低电芯电压 X unsigned short cell_vol_min = 0; N N u8 i = 0; X unsigned char i = 0; N u8 j = 0; X unsigned char j = 0; N Type = 0x01; //应答 N memset(sendbuffer,0,sizeof(sendbuffer)); //数据清零 W "..\user\src\swj.c" 2841 7 function "Send_TString_BMS" declared implicitly N Send_TString_BMS(stop_orde,22); //发送给MCU停止对309读写 N Delay_ms(100); N N if(Conf_309num==1) N { N MTPRead_fun_1( EEPROM_SCONF1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N A_Cellnum = (data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 & 0x0f); N if(A_Cellnum<5) N A_Cellnum = 16; N B_Cellnum = 0; N } N N else if(Conf_309num==2) N { N MTPRead_fun_1( EEPROM_SCONF1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x00, 2, &Rev_309_buf_A[0]); N data_309_A.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_A[0]; N A_Cellnum = (data_309_A.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 & 0x0f); N if(A_Cellnum<5) N A_Cellnum = 16; N N MTPRead_fun_2( EEPROM_SCONF1, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x00, 2, &Rev_309_buf_B[0]); N data_309_B.EEPROMWriRev_309.Sconf1.datas = Rev_309_buf_B[0]; N B_Cellnum = (data_309_B.EEPROMWriRev_309.Sconf1.bits.cn3_cn0 & 0x0f); N if(B_Cellnum<5) N B_Cellnum = 0; N } N N N MTPRead_fun_1( MTP_CONF, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x40, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Conf.datas = Rev_309_buf_A[0]; N N RAM_309data.Conf.datas = data_309_A.RAM_WrieRev_309.Conf.datas; N N if(Conf_309num==1) N { N MTPRead_fun_1( MTP_BALANCEH, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x41, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Balanceh_l.datas = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N RAM_309data.Balanceh_l.datas = 0; N RAM_309data.Balanceh_l.datas = data_309_A.RAM_WrieRev_309.Balanceh_l.datas; N } N else if(Conf_309num==2) N { N MTPRead_fun_1( MTP_BALANCEH, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x41, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Balanceh_l.datas = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N MTPRead_fun_2( MTP_BALANCEH, 2, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x41, 2, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Balanceh_l.datas = (Rev_309_buf_B[0] << 8) | Rev_309_buf_B[1]; N RAM_309data.Balanceh_l.datas = 0; N RAM_309data.Balanceh_l.datas = (data_309_B.RAM_WrieRev_309.Balanceh_l.datas << A_Cellnum) | data_309_A.RAM_WrieRev_309.Balanceh_l.datas; N } N N if(Conf_309num==1) N { N MTPRead_fun_1( MTP_BSTATUS1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x43, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus1.datas = Rev_309_buf_A[0]; N RAM_309data.Bstrtus1.datas = data_309_A.RAM_WrieRev_309.Bstrtus1.datas; N N MTPRead_fun_1( MTP_BSTATUS2, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x44, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus2.datas = Rev_309_buf_A[0]; N RAM_309data.Bstrtus2.datas = data_309_A.RAM_WrieRev_309.Bstrtus2.datas; N N MTPRead_fun_1( MTP_BSTATUS3, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x45, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus3.datas = Rev_309_buf_A[0]; N RAM_309data.Bstrtus3.datas = data_309_A.RAM_WrieRev_309.Bstrtus3.datas; N } N N else if(Conf_309num==2) N { N MTPRead_fun_1( MTP_BSTATUS1, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x43, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus1.datas = Rev_309_buf_A[0]; N MTPRead_fun_2( MTP_BSTATUS1, 1, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x43, 1, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Bstrtus1.datas = Rev_309_buf_B[0]; N RAM_309data.Bstrtus1.datas = data_309_A.RAM_WrieRev_309.Bstrtus1.datas | data_309_B.RAM_WrieRev_309.Bstrtus1.datas; N N MTPRead_fun_1( MTP_BSTATUS2, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x44, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus2.datas = Rev_309_buf_A[0]; N MTPRead_fun_2( MTP_BSTATUS2, 1, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x44, 1, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Bstrtus2.datas = Rev_309_buf_B[0]; N RAM_309data.Bstrtus2.datas = data_309_A.RAM_WrieRev_309.Bstrtus2.datas | data_309_B.RAM_WrieRev_309.Bstrtus2.datas; N N MTPRead_fun_1( MTP_BSTATUS3, 1, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x45, 1, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Bstrtus3.datas = Rev_309_buf_A[0]; N MTPRead_fun_2( MTP_BSTATUS3, 1, &Rev_309_buf_B[0]); X MTPRead_fun_2( 0x45, 1, &Rev_309_buf_B[0]); N data_309_B.RAM_WrieRev_309.Bstrtus3.datas = Rev_309_buf_B[0]; N RAM_309data.Bstrtus3.datas = data_309_A.RAM_WrieRev_309.Bstrtus3.datas & data_309_B.RAM_WrieRev_309.Bstrtus3.datas; N } N N ////////////////////////////////////////// N N MTPRead_fun_1( MTP_TEMP1, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x46, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP1h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N RAM_309data.TEMP1h_l = data_309_A.RAM_WrieRev_309.TEMP1h_l; N N MTPRead_fun_1( MTP_TEMP2, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x48, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP2h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N RAM_309data.TEMP2h_l = data_309_A.RAM_WrieRev_309.TEMP2h_l; N N MTPRead_fun_1( MTP_TEMP3, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4A, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.TEMP3h_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N RAM_309data.TEMP3h_l = data_309_A.RAM_WrieRev_309.TEMP3h_l; N N MTPRead_fun_1( MTP_CUR, 2, &Rev_309_buf_A[0]); X MTPRead_fun_1( 0x4C, 2, &Rev_309_buf_A[0]); N data_309_A.RAM_WrieRev_309.Curh_l = (Rev_309_buf_A[0] << 8) | Rev_309_buf_A[1]; N RAM_309data.Curh_l = data_309_A.RAM_WrieRev_309.Curh_l; N N for(i=0;i> 24; N sendbuffer[4] = RAM_309data.Balanceh_l.datas >> 16; N sendbuffer[5] = RAM_309data.Balanceh_l.datas >> 8; N sendbuffer[6] = RAM_309data.Balanceh_l.datas; N N sendbuffer[7] = DATA_MTP_BSTATUS1; X sendbuffer[7] = 0x32; N sendbuffer[8] = RAM_309data.Bstrtus1.datas; N N sendbuffer[9] = DATA_MTP_BSTATUS2; X sendbuffer[9] = 0x33; N sendbuffer[10] = RAM_309data.Bstrtus2.datas; N N sendbuffer[11] = DATA_MTP_BSTATUS3; X sendbuffer[11] = 0x34; N sendbuffer[12] = RAM_309data.Bstrtus3.datas; N N sendbuffer[13] = DATA_MTP_TEMP1; X sendbuffer[13] = 0x35; N sendbuffer[14] = RAM_309data.TEMP1h_l >> 8; N sendbuffer[15] = RAM_309data.TEMP1h_l; N N sendbuffer[16] = DATA_MTP_TEMP2; X sendbuffer[16] = 0x36; N sendbuffer[17] = RAM_309data.TEMP2h_l >> 8; N sendbuffer[18] = RAM_309data.TEMP2h_l; N N sendbuffer[19] = DATA_MTP_TEMP3; X sendbuffer[19] = 0x37; N sendbuffer[20] = RAM_309data.TEMP3h_l >> 8; N sendbuffer[21] = RAM_309data.TEMP3h_l; N N sendbuffer[22] = DATA_MTP_CUR; X sendbuffer[22] = 0x38; N sendbuffer[23] = RAM_309data.Curh_l >> 8; N sendbuffer[24] = RAM_309data.Curh_l; N N sendbuffer[25] = DATA_MTP_CELL1; X sendbuffer[25] = 0x39; N sendbuffer[26] = RAM_309data.Cell.cellvol[0] >> 8; N sendbuffer[27] = RAM_309data.Cell.cellvol[0]; N N sendbuffer[28] = DATA_MTP_CELL2; X sendbuffer[28] = 0x3A; N sendbuffer[29] = RAM_309data.Cell.cellvol[1] >> 8; N sendbuffer[30] = RAM_309data.Cell.cellvol[1]; N N sendbuffer[31] = DATA_MTP_CELL3; X sendbuffer[31] = 0x3B; N sendbuffer[32] = RAM_309data.Cell.cellvol[2] >> 8; N sendbuffer[33] = RAM_309data.Cell.cellvol[2]; N N sendbuffer[34] = DATA_MTP_CELL4; X sendbuffer[34] = 0x3C; N sendbuffer[35] = RAM_309data.Cell.cellvol[3] >> 8; N sendbuffer[36] = RAM_309data.Cell.cellvol[3]; N N sendbuffer[37] = DATA_MTP_CELL5; X sendbuffer[37] = 0x3D; N sendbuffer[38] = RAM_309data.Cell.cellvol[4] >> 8; N sendbuffer[39] = RAM_309data.Cell.cellvol[4]; N N sendbuffer[40] = DATA_MTP_CELL6; X sendbuffer[40] = 0x3E; N sendbuffer[41] = RAM_309data.Cell.cellvol[5] >> 8; N sendbuffer[42] = RAM_309data.Cell.cellvol[5]; N N sendbuffer[43] = DATA_MTP_CELL7; X sendbuffer[43] = 0x3F; N sendbuffer[44] = RAM_309data.Cell.cellvol[6] >> 8; N sendbuffer[45] = RAM_309data.Cell.cellvol[6]; N N sendbuffer[46] = DATA_MTP_CELL8; X sendbuffer[46] = 0x40; N sendbuffer[47] = RAM_309data.Cell.cellvol[7] >> 8; N sendbuffer[48] = RAM_309data.Cell.cellvol[7]; N N sendbuffer[49] = DATA_MTP_CELL9; X sendbuffer[49] = 0x41; N sendbuffer[50] = RAM_309data.Cell.cellvol[8] >> 8; N sendbuffer[51] = RAM_309data.Cell.cellvol[8]; N N sendbuffer[52] = DATA_MTP_CELL10; X sendbuffer[52] = 0x42; N sendbuffer[53] = RAM_309data.Cell.cellvol[9] >> 8; N sendbuffer[54] = RAM_309data.Cell.cellvol[9]; N N sendbuffer[55] = DATA_MTP_CELL11; X sendbuffer[55] = 0x43; N sendbuffer[56] = RAM_309data.Cell.cellvol[10] >> 8; N sendbuffer[57] = RAM_309data.Cell.cellvol[10]; N N sendbuffer[58] = DATA_MTP_CELL12; X sendbuffer[58] = 0x44; N sendbuffer[59] = RAM_309data.Cell.cellvol[11] >> 8; N sendbuffer[60] = RAM_309data.Cell.cellvol[11]; N N sendbuffer[61] = DATA_MTP_CELL13; X sendbuffer[61] = 0x45; N sendbuffer[62] = RAM_309data.Cell.cellvol[12] >> 8; N sendbuffer[63] = RAM_309data.Cell.cellvol[12]; N N sendbuffer[64] = DATA_MTP_CELL14; X sendbuffer[64] = 0x46; N sendbuffer[65] = RAM_309data.Cell.cellvol[13] >> 8; N sendbuffer[66] = RAM_309data.Cell.cellvol[13]; N N sendbuffer[67] = DATA_MTP_CELL15; X sendbuffer[67] = 0x47; N sendbuffer[68] = RAM_309data.Cell.cellvol[14] >> 8; N sendbuffer[69] = RAM_309data.Cell.cellvol[14]; N N sendbuffer[70] = DATA_MTP_CELL16; X sendbuffer[70] = 0x48; N sendbuffer[71] = RAM_309data.Cell.cellvol[15] >> 8; N sendbuffer[72] = RAM_309data.Cell.cellvol[15]; N N sendbuffer[73] = DATA_MTP_CELL17; X sendbuffer[73] = 0x49; N sendbuffer[74] = RAM_309data.Cell.cellvol[16] >> 8; N sendbuffer[75] = RAM_309data.Cell.cellvol[16]; N N sendbuffer[76] = DATA_MTP_CELL18; X sendbuffer[76] = 0x4A; N sendbuffer[77] = RAM_309data.Cell.cellvol[17] >> 8; N sendbuffer[78] = RAM_309data.Cell.cellvol[17]; N N sendbuffer[79] = DATA_MTP_CELL19; X sendbuffer[79] = 0x4B; N sendbuffer[80] = RAM_309data.Cell.cellvol[18] >> 8; N sendbuffer[81] = RAM_309data.Cell.cellvol[18]; N N sendbuffer[82] = DATA_MTP_CELL20; X sendbuffer[82] = 0x4C; N sendbuffer[83] = RAM_309data.Cell.cellvol[19] >> 8; N sendbuffer[84] = RAM_309data.Cell.cellvol[19]; N N sendbuffer[85] = DATA_MTP_CELL21; X sendbuffer[85] = 0x4D; N sendbuffer[86] = RAM_309data.Cell.cellvol[20] >> 8; N sendbuffer[87] = RAM_309data.Cell.cellvol[20]; N N sendbuffer[88] = DATA_MTP_CELL22; X sendbuffer[88] = 0x4E; N sendbuffer[89] = RAM_309data.Cell.cellvol[21] >> 8; N sendbuffer[90] = RAM_309data.Cell.cellvol[21]; N N sendbuffer[91] = DATA_MTP_CELL23; X sendbuffer[91] = 0x4F; N sendbuffer[92] = RAM_309data.Cell.cellvol[22] >> 8; N sendbuffer[93] = RAM_309data.Cell.cellvol[22]; N N sendbuffer[94] = DATA_MTP_CELL24; X sendbuffer[94] = 0x50; N sendbuffer[95] = RAM_309data.Cell.cellvol[23] >> 8; N sendbuffer[96] = RAM_309data.Cell.cellvol[23]; N N sendbuffer[97] = DATA_MTP_ADC2; X sendbuffer[97] = 0x51; N sendbuffer[98] = RAM_309data.CADcdh_l >> 8; N sendbuffer[99] = RAM_309data.CADcdh_l; N N sendbuffer[100] = DATA_MTP_BFLAG1; X sendbuffer[100] = 0x52; N sendbuffer[101] = RAM_309data.Bflag1.datas; N N sendbuffer[102] = DATA_MTP_BFLAG2; X sendbuffer[102] = 0x53; N sendbuffer[103] = RAM_309data.Bflag2.datas; N N sendbuffer[104] = DATA_MTP_RSTSTAT; X sendbuffer[104] = 0x54; N sendbuffer[105] = RAM_309data.Rststat.datas; N N sendbuffer[106] = DATA_MTP_TEMP1_NUM; X sendbuffer[106] = 0x55; N sendbuffer[107] = RAM_309data.T1_tmp >> 8; N sendbuffer[108] = RAM_309data.T1_tmp; N N sendbuffer[109] = DATA_MTP_TEMP2_NUM; X sendbuffer[109] = 0x56; N sendbuffer[110] = RAM_309data.T2_tmp >> 8; N sendbuffer[111] = RAM_309data.T2_tmp; N N sendbuffer[112] = DATA_MTP_TEMP3_NUM; X sendbuffer[112] = 0x57; N sendbuffer[113] = RAM_309data.T3_tmp >> 8; N sendbuffer[114] = RAM_309data.T3_tmp; N N sendbuffer[115] = DATA_MTP_CELL1_NUM; X sendbuffer[115] = 0x58; N sendbuffer[116] = RAM_309data.Cell_Num.cellvol[0] >> 8; N sendbuffer[117] = RAM_309data.Cell_Num.cellvol[0]; N N sendbuffer[118] = DATA_MTP_CELL2_NUM; X sendbuffer[118] = 0x59; N sendbuffer[119] = RAM_309data.Cell_Num.cellvol[1] >> 8; N sendbuffer[120] = RAM_309data.Cell_Num.cellvol[1]; N N sendbuffer[121] = DATA_MTP_CELL3_NUM; X sendbuffer[121] = 0x5A; N sendbuffer[122] = RAM_309data.Cell_Num.cellvol[2] >> 8; N sendbuffer[123] = RAM_309data.Cell_Num.cellvol[2]; N N sendbuffer[124] = DATA_MTP_CELL4_NUM; X sendbuffer[124] = 0x5B; N sendbuffer[125] = RAM_309data.Cell_Num.cellvol[3] >> 8; N sendbuffer[126] = RAM_309data.Cell_Num.cellvol[3]; N N sendbuffer[127] = DATA_MTP_CELL5_NUM; X sendbuffer[127] = 0x5C; N sendbuffer[128] = RAM_309data.Cell_Num.cellvol[4] >> 8; N sendbuffer[129] = RAM_309data.Cell_Num.cellvol[4]; N N sendbuffer[130] = DATA_MTP_CELL6_NUM; X sendbuffer[130] = 0x5D; N sendbuffer[131] = RAM_309data.Cell_Num.cellvol[5] >> 8; N sendbuffer[132] = RAM_309data.Cell_Num.cellvol[5]; N N sendbuffer[133] = DATA_MTP_CELL7_NUM; X sendbuffer[133] = 0x5E; N sendbuffer[134] = RAM_309data.Cell_Num.cellvol[6] >> 8; N sendbuffer[135] = RAM_309data.Cell_Num.cellvol[6]; N N sendbuffer[136] = DATA_MTP_CELL8_NUM; X sendbuffer[136] = 0x5F; N sendbuffer[137] = RAM_309data.Cell_Num.cellvol[7] >> 8; N sendbuffer[138] = RAM_309data.Cell_Num.cellvol[7]; N N sendbuffer[139] = DATA_MTP_CELL9_NUM; X sendbuffer[139] = 0x60; N sendbuffer[140] = RAM_309data.Cell_Num.cellvol[8] >> 8; N sendbuffer[141] = RAM_309data.Cell_Num.cellvol[8]; N N sendbuffer[142] = DATA_MTP_CELL10_NUM; X sendbuffer[142] = 0x61; N sendbuffer[143] = RAM_309data.Cell_Num.cellvol[9] >> 8; N sendbuffer[144] = RAM_309data.Cell_Num.cellvol[9]; N N sendbuffer[145] = DATA_MTP_CELL11_NUM; X sendbuffer[145] = 0x62; N sendbuffer[146] = RAM_309data.Cell_Num.cellvol[10] >> 8; N sendbuffer[147] = RAM_309data.Cell_Num.cellvol[10]; N N sendbuffer[148] = DATA_MTP_CELL12_NUM; X sendbuffer[148] = 0x63; N sendbuffer[149] = RAM_309data.Cell_Num.cellvol[11] >> 8; N sendbuffer[150] = RAM_309data.Cell_Num.cellvol[11]; N N sendbuffer[151] = DATA_MTP_CELL13_NUM; X sendbuffer[151] = 0x64; N sendbuffer[152] = RAM_309data.Cell_Num.cellvol[12] >> 8; N sendbuffer[153] = RAM_309data.Cell_Num.cellvol[12]; N N sendbuffer[154] = DATA_MTP_CELL14_NUM; X sendbuffer[154] = 0x65; N sendbuffer[155] = RAM_309data.Cell_Num.cellvol[13] >> 8; N sendbuffer[156] = RAM_309data.Cell_Num.cellvol[13]; N N sendbuffer[157] = DATA_MTP_CELL15_NUM; X sendbuffer[157] = 0x66; N sendbuffer[158] = RAM_309data.Cell_Num.cellvol[14] >> 8; N sendbuffer[159] = RAM_309data.Cell_Num.cellvol[14]; N N sendbuffer[160] = DATA_MTP_CELL16_NUM; X sendbuffer[160] = 0x67; N sendbuffer[161] = RAM_309data.Cell_Num.cellvol[15] >> 8; N sendbuffer[162] = RAM_309data.Cell_Num.cellvol[15]; N N sendbuffer[163] = DATA_MTP_CELL17_NUM; X sendbuffer[163] = 0x68; N sendbuffer[164] = RAM_309data.Cell_Num.cellvol[16] >> 8; N sendbuffer[165] = RAM_309data.Cell_Num.cellvol[16]; N N sendbuffer[166] = DATA_MTP_CELL18_NUM; X sendbuffer[166] = 0x69; N sendbuffer[167] = RAM_309data.Cell_Num.cellvol[17] >> 8; N sendbuffer[168] = RAM_309data.Cell_Num.cellvol[17]; N N sendbuffer[169] = DATA_MTP_CELL19_NUM; X sendbuffer[169] = 0x6A; N sendbuffer[170] = RAM_309data.Cell_Num.cellvol[18] >> 8; N sendbuffer[171] = RAM_309data.Cell_Num.cellvol[18]; N N sendbuffer[172] = DATA_MTP_CELL20_NUM; X sendbuffer[172] = 0x6B; N sendbuffer[173] = RAM_309data.Cell_Num.cellvol[19] >> 8; N sendbuffer[174] = RAM_309data.Cell_Num.cellvol[19]; N N sendbuffer[175] = DATA_MTP_CELL21_NUM; X sendbuffer[175] = 0x6C; N sendbuffer[176] = RAM_309data.Cell_Num.cellvol[20] >> 8; N sendbuffer[177] = RAM_309data.Cell_Num.cellvol[20]; N N sendbuffer[178] = DATA_MTP_CELL22_NUM; X sendbuffer[178] = 0x6D; N sendbuffer[179] = RAM_309data.Cell_Num.cellvol[21] >> 8; N sendbuffer[180] = RAM_309data.Cell_Num.cellvol[21]; N N sendbuffer[181] = DATA_MTP_CELL23_NUM; X sendbuffer[181] = 0x6E; N sendbuffer[182] = RAM_309data.Cell_Num.cellvol[22] >> 8; N sendbuffer[183] = RAM_309data.Cell_Num.cellvol[22]; N N sendbuffer[184] = DATA_MTP_CELL24_NUM; X sendbuffer[184] = 0x6F; N sendbuffer[185] = RAM_309data.Cell_Num.cellvol[23] >> 8; N sendbuffer[186] = RAM_309data.Cell_Num.cellvol[23]; N N sumVol = 0; N for(i = 0; i < A_Cellnum + B_Cellnum; i++) N { N sumVol += RAM_309data.Cell_Num.cellvol[i]; N } N RAM_309data.zvols = sumVol; N N sendbuffer[187] = DATA_MTP_ZVOL; //总电压 X sendbuffer[187] = 0x70; N sendbuffer[188] = RAM_309data.zvols >> 8; N sendbuffer[189] = RAM_309data.zvols; N N memcpy(cell_Vol_1,&RAM_309data.Cell_Num.cellvol[0],(A_Cellnum + B_Cellnum)*2); N memcpy(cell_Vol_2,&RAM_309data.Cell_Num.cellvol[0],(A_Cellnum + B_Cellnum)*2); N N for(i=0; i<(A_Cellnum + B_Cellnum)-1; i++) N { N for(j=0; j cell_Vol_1[j+1]) N { N u16 temp = cell_Vol_1[j+1]; X unsigned short temp = cell_Vol_1[j+1]; N cell_Vol_1[j+1] = cell_Vol_1[j]; N cell_Vol_1[j] = temp; N } N } N } N cell_vol_max = cell_Vol_1[(A_Cellnum + B_Cellnum)-1]; N N for(i=0; i<(A_Cellnum + B_Cellnum)-1; i++) N { N for(j=0; j> 8; N sendbuffer[192] = RAM_309data.volyc; N N send_len = 187; //上位机处理 （依情况定） N Send_TString_BMS(start_orde,22); //发送给MCU开始对309读写 N /*发送数据*/ N Send_GpsFun(Bms_num,orde,Type,sendbuffer,send_len,recnum); N Beep_Flag = 1; N } N break; N N default: N break; N } N } N } N} N N N