boot 添加GD32F105RC
This commit is contained in:
parent
bbc86dfc57
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU Configuration
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// <o0.0> DBG_SLEEP
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// <i> Debug Sleep Mode
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// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
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// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
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// <o0.1> DBG_STOP
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// <i> Debug Stop Mode
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// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
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// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.2> DBG_STANDBY
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// <i> Debug Standby Mode
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// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
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// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.8> DBG_IWDG_STOP
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// <i> Debug independent watchdog stopped when core is halted
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// <i> 0: The watchdog counter clock continues even if the core is halted
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// <i> 1: The watchdog counter clock is stopped when the core is halted
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// <o0.9> DBG_WWDG_STOP
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// <i> Debug window watchdog stopped when core is halted
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// <i> 0: The window watchdog counter clock continues even if the core is halted
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// <i> 1: The window watchdog counter clock is stopped when the core is halted
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// <o0.10> DBG_TIM1_STOP
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// <i> Timer 1 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.11> DBG_TIM2_STOP
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// <i> Timer 2 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.12> DBG_TIM3_STOP
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// <i> Timer 3 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.13> DBG_TIM4_STOP
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// <i> Timer 4 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.14> DBG_CAN1_STOP
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// <i> Debug CAN1 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN1 receive registers are frozen
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// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
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// <i> I2C1 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
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// <i> I2C2 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.17> DBG_TIM8_STOP
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// <i> Timer 8 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.18> DBG_TIM5_STOP
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// <i> Timer 5 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.19> DBG_TIM6_STOP
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// <i> Timer 6 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.20> DBG_TIM7_STOP
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// <i> Timer 7 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.21> DBG_CAN2_STOP
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// <i> Debug CAN2 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN2 receive registers are frozen
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// <o0.25> DBG_TIM12_STOP
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// <i> Timer 12 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.26> DBG_TIM13_STOP
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// <i> Timer 13 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.27> DBG_TIM14_STOP
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// <i> Timer 14 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.28> DBG_TIM9_STOP
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// <i> Timer 9 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.29> DBG_TIM10_STOP
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// <i> Timer 10 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.30> DBG_TIM11_STOP
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// <i> Timer 11 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>
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97
boot_project/DebugConfig/hongri_boot_STM_STM32F105RC.dbgconf
Normal file
97
boot_project/DebugConfig/hongri_boot_STM_STM32F105RC.dbgconf
Normal file
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU Configuration
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// <o0.0> DBG_SLEEP
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// <i> Debug Sleep Mode
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// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
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// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
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// <o0.1> DBG_STOP
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// <i> Debug Stop Mode
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// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
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// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.2> DBG_STANDBY
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// <i> Debug Standby Mode
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// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
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// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.8> DBG_IWDG_STOP
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// <i> Debug independent watchdog stopped when core is halted
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// <i> 0: The watchdog counter clock continues even if the core is halted
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// <i> 1: The watchdog counter clock is stopped when the core is halted
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// <o0.9> DBG_WWDG_STOP
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// <i> Debug window watchdog stopped when core is halted
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// <i> 0: The window watchdog counter clock continues even if the core is halted
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// <i> 1: The window watchdog counter clock is stopped when the core is halted
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// <o0.10> DBG_TIM1_STOP
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// <i> Timer 1 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.11> DBG_TIM2_STOP
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// <i> Timer 2 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.12> DBG_TIM3_STOP
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// <i> Timer 3 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.13> DBG_TIM4_STOP
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// <i> Timer 4 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.14> DBG_CAN1_STOP
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// <i> Debug CAN1 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN1 receive registers are frozen
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// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
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// <i> I2C1 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
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// <i> I2C2 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.17> DBG_TIM8_STOP
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// <i> Timer 8 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.18> DBG_TIM5_STOP
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// <i> Timer 5 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.19> DBG_TIM6_STOP
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// <i> Timer 6 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.20> DBG_TIM7_STOP
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// <i> Timer 7 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.21> DBG_CAN2_STOP
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// <i> Debug CAN2 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN2 receive registers are frozen
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// <o0.25> DBG_TIM12_STOP
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// <i> Timer 12 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.26> DBG_TIM13_STOP
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// <i> Timer 13 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.27> DBG_TIM14_STOP
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// <i> Timer 14 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.28> DBG_TIM9_STOP
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// <i> Timer 9 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.29> DBG_TIM10_STOP
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// <i> Timer 10 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.30> DBG_TIM11_STOP
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// <i> Timer 11 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>
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BIN
boot_project/LED.map
Normal file
BIN
boot_project/LED.map
Normal file
Binary file not shown.
Binary file not shown.
BIN
boot_project/Listings/boot_GD32F105RC.map
Normal file
BIN
boot_project/Listings/boot_GD32F105RC.map
Normal file
Binary file not shown.
BIN
boot_project/Listings/boot_STM32F105.map
Normal file
BIN
boot_project/Listings/boot_STM32F105.map
Normal file
Binary file not shown.
BIN
boot_project/Listings/boot_STM32F105RC.map
Normal file
BIN
boot_project/Listings/boot_STM32F105RC.map
Normal file
Binary file not shown.
BIN
boot_project/Listings/boot_gd32F105.map
Normal file
BIN
boot_project/Listings/boot_gd32F105.map
Normal file
Binary file not shown.
BIN
boot_project/Listings/startup_gd32f10x_cl.lst
Normal file
BIN
boot_project/Listings/startup_gd32f10x_cl.lst
Normal file
Binary file not shown.
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[EXTDLL]
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Count=0
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Binary file not shown.
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<html>
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<body>
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<pre>
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<h1>µVision Build Log</h1>
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<h2>Tool Versions:</h2>
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IDE-Version: ¦ÌVision V5.25.2.0
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Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
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License Information: Zachary Administrator, Zachary, LIC=TIVNB-2IHDY-01WP1-C2K2G-5HIE0-XG8NS
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Tool Versions:
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Toolchain: MDK-ARM Plus Version: 5.25.2.0
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Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
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C Compiler: Armcc.exe V5.06 update 6 (build 750)
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Assembler: Armasm.exe V5.06 update 6 (build 750)
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Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
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Library Manager: ArmAr.exe V5.06 update 6 (build 750)
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Hex Converter: FromElf.exe V5.06 update 6 (build 750)
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CPU DLL: SARMCM3.DLL V5.25.2.0
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Dialog DLL: DCM.DLL V1.17.1.0
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Target DLL: Segger\JL2CM3.dll V2.99.29.0
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Dialog DLL: TCM.DLL V1.35.1.0
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<h2>Project:</h2>
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E:\liudagui\project\HONGRI\code\boot_up\boot_project\hongri_boot.uvprojx
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Project File Date: 11/04/2024
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<h2>Output:</h2>
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*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
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Rebuild target 'hongri_boot'
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assembling startup_stm32f10x_cl.s...
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compiling misc.c...
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compiling stm32f10x_dma.c...
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compiling led.c...
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compiling stm32f10x_pwr.c...
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compiling stm32f10x_can.c...
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compiling stm32f10x_iwdg.c...
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compiling stm32f10x_flash.c...
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compiling 24cxx.c...
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compiling core_cm3.c...
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compiling stm32f10x_rcc.c...
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compiling stm32f10x_gpio.c...
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compiling bsp_i2c_gpio.c...
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compiling stm32f10x_it.c...
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compiling can2.c...
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compiling dev_flashApi.c...
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compiling dev_crc32.c...
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compiling dev_eerom.c...
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compiling system_stm32f10x.c...
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compiling dev_sys.c...
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compiling UDS.c...
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compiling iso15765-2_entry.c...
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compiling Can_Transceiver.c...
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compiling Diag_Eeprom_C301.c...
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compiling iso15765-2.c...
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compiling CanCtrl_C301.c...
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compiling CanConfig_C301.c...
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compiling UDS_SA_C301.c...
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..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c(48): warning: #177-D: function "BL_BE32_TO_MCU" was declared but never referenced
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static uint32_t BL_BE32_TO_MCU(uint8_t *pBuf)
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..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c: 1 warning, 0 errors
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compiling app_can.c...
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compiling main.c...
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..\boot_source\code_app\main\src\main.c(163): warning: #188-D: enumerated type mixed with another type
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RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP,ENABLE );//
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..\boot_source\code_app\main\src\main.c(164): warning: #188-D: enumerated type mixed with another type
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PWR_BackupAccessCmd(ENABLE);//
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..\boot_source\code_app\main\src\main.c(198): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_1MS = RESET;
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..\boot_source\code_app\main\src\main.c(207): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_5MS = RESET;
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..\boot_source\code_app\main\src\main.c(213): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_10MS = RESET;
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..\boot_source\code_app\main\src\main.c(222): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_20MS = RESET;
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..\boot_source\code_app\main\src\main.c(226): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_50MS = RESET;
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..\boot_source\code_app\main\src\main.c(230): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_100MS = RESET;
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..\boot_source\code_app\main\src\main.c(234): warning: #188-D: enumerated type mixed with another type
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TimeTaskData.F_Time_1000MS = RESET;
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..\boot_source\code_app\main\src\main.c(89): warning: #177-D: function "Task_RunToAppCheckValide" was declared but never referenced
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static uint8_t Task_RunToAppCheckValide(void)
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..\boot_source\code_app\main\src\main.c: 10 warnings, 0 errors
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compiling Diag_Appl_C301.c...
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..\boot_source\code_app\driver\inc\dev_eerom.h(32): warning: #1-D: last line of file ends without a newline
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/** EOF */
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(1329): warning: #177-D: variable "crc32" was declared but never referenced
|
||||
uint32_t crc32=0;
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2026): warning: #550-D: variable "CRC_16" was set but never used
|
||||
uint16_t CRC_16=0xFFFF;
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2121): warning: #223-D: function "GetCrc32Chk" declared implicitly
|
||||
if(GetCrc32Chk() == transSequenceValue)
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(289): warning: #177-D: function "Diag_ExtMemorySecFAAFlagSave" was declared but never referenced
|
||||
static void Diag_ExtMemorySecFAAFlagSave(uint8_t cnt)
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c: 5 warnings, 0 errors
|
||||
linking...
|
||||
Program Size: Code=22124 RO-data=980 RW-data=252 ZI-data=12716
|
||||
FromELF: creating hex file...
|
||||
".\Objects\boot.axf" - 0 Error(s), 16 Warning(s).
|
||||
|
||||
<h2>Software Packages used:</h2>
|
||||
|
||||
Package Vendor: Keil
|
||||
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.1.0.pack
|
||||
Keil.STM32F1xx_DFP.2.1.0
|
||||
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
|
||||
|
||||
<h2>Collection of Component include folders:</h2>
|
||||
.\RTE\_hongri_boot
|
||||
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
|
||||
|
||||
<h2>Collection of Component Files used:</h2>
|
||||
Build Time Elapsed: 00:00:06
|
||||
</pre>
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,36 +0,0 @@
|
||||
--cpu Cortex-M3
|
||||
".\objects\startup_stm32f10x_cl.o"
|
||||
".\objects\core_cm3.o"
|
||||
".\objects\misc.o"
|
||||
".\objects\stm32f10x_gpio.o"
|
||||
".\objects\stm32f10x_rcc.o"
|
||||
".\objects\stm32f10x_can.o"
|
||||
".\objects\stm32f10x_dma.o"
|
||||
".\objects\stm32f10x_flash.o"
|
||||
".\objects\stm32f10x_iwdg.o"
|
||||
".\objects\stm32f10x_pwr.o"
|
||||
".\objects\led.o"
|
||||
".\objects\24cxx.o"
|
||||
".\objects\bsp_i2c_gpio.o"
|
||||
".\objects\can2.o"
|
||||
".\objects\stm32f10x_it.o"
|
||||
".\objects\system_stm32f10x.o"
|
||||
".\objects\dev_flashapi.o"
|
||||
".\objects\dev_crc32.o"
|
||||
".\objects\dev_sys.o"
|
||||
".\objects\dev_eerom.o"
|
||||
".\objects\uds.o"
|
||||
".\objects\iso15765-2.o"
|
||||
".\objects\iso15765-2_entry.o"
|
||||
".\objects\can_transceiver.o"
|
||||
".\objects\diag_eeprom_c301.o"
|
||||
".\objects\canconfig_c301.o"
|
||||
".\objects\canctrl_c301.o"
|
||||
".\objects\diag_appl_c301.o"
|
||||
".\objects\uds_sa_c301.o"
|
||||
".\objects\main.o"
|
||||
".\objects\app_can.o"
|
||||
--library_type=microlib --strict --scatter ".\link_sct\STM32F105Boot.sct"
|
||||
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
|
||||
--info sizes --info totals --info unused --info veneers
|
||||
--list ".\Listings\boot.map" -o .\Objects\boot.axf
|
||||
@ -1,6 +0,0 @@
|
||||
--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com\inc -I ..\boot_source\code_app\service\CanStack\canBus_hongri\inc -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
|
||||
-I.\RTE\_hongri_boot
|
||||
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
|
||||
-IC:\Keil_v5\ARM\CMSIS\Include
|
||||
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
|
||||
-o .\objects\diag_appl_hr.o --omf_browse .\objects\diag_appl_hr.crf --depend .\objects\diag_appl_hr.d "..\boot_source\code_app\service\CanStack\canBus_hongri\src\Diag_Appl_hr.c"
|
||||
Binary file not shown.
@ -1,116 +0,0 @@
|
||||
<html>
|
||||
<body>
|
||||
<pre>
|
||||
<h1>µVision Build Log</h1>
|
||||
<h2>Tool Versions:</h2>
|
||||
IDE-Version: ¦ÌVision V5.25.2.0
|
||||
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
|
||||
License Information: Zachary Administrator, Zachary, LIC=TIVNB-2IHDY-01WP1-C2K2G-5HIE0-XG8NS
|
||||
|
||||
Tool Versions:
|
||||
Toolchain: MDK-ARM Plus Version: 5.25.2.0
|
||||
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
|
||||
C Compiler: Armcc.exe V5.06 update 6 (build 750)
|
||||
Assembler: Armasm.exe V5.06 update 6 (build 750)
|
||||
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
|
||||
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
|
||||
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
|
||||
CPU DLL: SARMCM3.DLL V5.25.2.0
|
||||
Dialog DLL: DCM.DLL V1.17.1.0
|
||||
Target DLL: Segger\JL2CM3.dll V2.99.29.0
|
||||
Dialog DLL: TCM.DLL V1.35.1.0
|
||||
|
||||
<h2>Project:</h2>
|
||||
E:\liudagui\project\HONGRI\code\boot_up\boot_project\hongri_boot.uvprojx
|
||||
Project File Date: 11/04/2024
|
||||
|
||||
<h2>Output:</h2>
|
||||
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
|
||||
Rebuild target 'hongri_boot'
|
||||
assembling startup_stm32f10x_cl.s...
|
||||
compiling stm32f10x_gpio.c...
|
||||
compiling misc.c...
|
||||
compiling stm32f10x_dma.c...
|
||||
compiling stm32f10x_iwdg.c...
|
||||
compiling stm32f10x_pwr.c...
|
||||
compiling stm32f10x_can.c...
|
||||
compiling stm32f10x_rcc.c...
|
||||
compiling led.c...
|
||||
compiling stm32f10x_flash.c...
|
||||
compiling 24cxx.c...
|
||||
compiling core_cm3.c...
|
||||
compiling bsp_i2c_gpio.c...
|
||||
compiling dev_eerom.c...
|
||||
compiling dev_crc32.c...
|
||||
compiling dev_flashApi.c...
|
||||
compiling stm32f10x_it.c...
|
||||
compiling system_stm32f10x.c...
|
||||
compiling dev_sys.c...
|
||||
compiling can2.c...
|
||||
compiling iso15765-2_entry.c...
|
||||
compiling Can_Transceiver.c...
|
||||
compiling iso15765-2.c...
|
||||
compiling Diag_Eeprom_C301.c...
|
||||
compiling UDS.c...
|
||||
compiling CanConfig_C301.c...
|
||||
compiling CanCtrl_C301.c...
|
||||
compiling UDS_SA_C301.c...
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c(48): warning: #177-D: function "BL_BE32_TO_MCU" was declared but never referenced
|
||||
static uint32_t BL_BE32_TO_MCU(uint8_t *pBuf)
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c: 1 warning, 0 errors
|
||||
compiling Diag_Appl_C301.c...
|
||||
..\boot_source\code_app\driver\inc\dev_eerom.h(32): warning: #1-D: last line of file ends without a newline
|
||||
/** EOF */
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(1329): warning: #177-D: variable "crc32" was declared but never referenced
|
||||
uint32_t crc32=0;
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2026): warning: #550-D: variable "CRC_16" was set but never used
|
||||
uint16_t CRC_16=0xFFFF;
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2121): warning: #223-D: function "GetCrc32Chk" declared implicitly
|
||||
if(GetCrc32Chk() == transSequenceValue)
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(289): warning: #177-D: function "Diag_ExtMemorySecFAAFlagSave" was declared but never referenced
|
||||
static void Diag_ExtMemorySecFAAFlagSave(uint8_t cnt)
|
||||
..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c: 5 warnings, 0 errors
|
||||
compiling main.c...
|
||||
..\boot_source\code_app\main\src\main.c(163): warning: #188-D: enumerated type mixed with another type
|
||||
RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP,ENABLE );//
|
||||
..\boot_source\code_app\main\src\main.c(164): warning: #188-D: enumerated type mixed with another type
|
||||
PWR_BackupAccessCmd(ENABLE);//
|
||||
..\boot_source\code_app\main\src\main.c(198): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_1MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(207): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_5MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(213): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_10MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(222): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_20MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(226): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_50MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(230): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_100MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(234): warning: #188-D: enumerated type mixed with another type
|
||||
TimeTaskData.F_Time_1000MS = RESET;
|
||||
..\boot_source\code_app\main\src\main.c(89): warning: #177-D: function "Task_RunToAppCheckValide" was declared but never referenced
|
||||
static uint8_t Task_RunToAppCheckValide(void)
|
||||
..\boot_source\code_app\main\src\main.c: 10 warnings, 0 errors
|
||||
compiling app_can.c...
|
||||
linking...
|
||||
Program Size: Code=22124 RO-data=980 RW-data=252 ZI-data=12716
|
||||
FromELF: creating hex file...
|
||||
".\Objects\hongri_boot.axf" - 0 Error(s), 16 Warning(s).
|
||||
|
||||
<h2>Software Packages used:</h2>
|
||||
|
||||
Package Vendor: Keil
|
||||
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.1.0.pack
|
||||
Keil.STM32F1xx_DFP.2.1.0
|
||||
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
|
||||
|
||||
<h2>Collection of Component include folders:</h2>
|
||||
.\RTE\_hongri_boot
|
||||
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
|
||||
|
||||
<h2>Collection of Component Files used:</h2>
|
||||
Build Time Elapsed: 00:00:06
|
||||
</pre>
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,36 +0,0 @@
|
||||
--cpu Cortex-M3
|
||||
".\objects\startup_stm32f10x_cl.o"
|
||||
".\objects\core_cm3.o"
|
||||
".\objects\misc.o"
|
||||
".\objects\stm32f10x_gpio.o"
|
||||
".\objects\stm32f10x_rcc.o"
|
||||
".\objects\stm32f10x_can.o"
|
||||
".\objects\stm32f10x_dma.o"
|
||||
".\objects\stm32f10x_flash.o"
|
||||
".\objects\stm32f10x_iwdg.o"
|
||||
".\objects\stm32f10x_pwr.o"
|
||||
".\objects\led.o"
|
||||
".\objects\24cxx.o"
|
||||
".\objects\bsp_i2c_gpio.o"
|
||||
".\objects\can2.o"
|
||||
".\objects\stm32f10x_it.o"
|
||||
".\objects\system_stm32f10x.o"
|
||||
".\objects\dev_flashapi.o"
|
||||
".\objects\dev_crc32.o"
|
||||
".\objects\dev_sys.o"
|
||||
".\objects\dev_eerom.o"
|
||||
".\objects\uds.o"
|
||||
".\objects\iso15765-2.o"
|
||||
".\objects\iso15765-2_entry.o"
|
||||
".\objects\can_transceiver.o"
|
||||
".\objects\diag_eeprom_c301.o"
|
||||
".\objects\canconfig_c301.o"
|
||||
".\objects\canctrl_c301.o"
|
||||
".\objects\diag_appl_c301.o"
|
||||
".\objects\uds_sa_c301.o"
|
||||
".\objects\main.o"
|
||||
".\objects\app_can.o"
|
||||
--library_type=microlib --strict --scatter ".\link_sct\STM32F105Boot.sct"
|
||||
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
|
||||
--info sizes --info totals --info unused --info veneers
|
||||
--list ".\Listings\hongri_boot.map" -o .\Objects\hongri_boot.axf
|
||||
Binary file not shown.
@ -1,482 +0,0 @@
|
||||
Dependencies for Project 'hongri_boot', Target 'hongri_boot': (DO NOT MODIFY !)
|
||||
F (..\boot_source\platform\CMSIS\ST\STM32F10x\Source\arm\startup_stm32f10x_cl.s)(0x67188B3E)(--cpu Cortex-M3 -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
--pd "__UVISION_VERSION SETA 525" --pd "STM32F10X_CL SETA 1"
--list .\listings\startup_stm32f10x_cl.lst --xref -o .\objects\startup_stm32f10x_cl.o --depend .\objects\startup_stm32f10x_cl.d)
|
||||
F (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.c)(0x61605444)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\core_cm3.o --omf_browse .\objects\core_cm3.crf --depend .\objects\core_cm3.d)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\misc.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\misc.o --omf_browse .\objects\misc.crf --depend .\objects\misc.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_gpio.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_gpio.o --omf_browse .\objects\stm32f10x_gpio.crf --depend .\objects\stm32f10x_gpio.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_rcc.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_rcc.o --omf_browse .\objects\stm32f10x_rcc.crf --depend .\objects\stm32f10x_rcc.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_can.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_can.o --omf_browse .\objects\stm32f10x_can.crf --depend .\objects\stm32f10x_can.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_dma.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_dma.o --omf_browse .\objects\stm32f10x_dma.crf --depend .\objects\stm32f10x_dma.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_dma.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_flash.c)(0x6118F57E)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_flash.o --omf_browse .\objects\stm32f10x_flash.crf --depend .\objects\stm32f10x_flash.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_flash.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_iwdg.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_iwdg.o --omf_browse .\objects\stm32f10x_iwdg.crf --depend .\objects\stm32f10x_iwdg.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_pwr.c)(0x65F32F30)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_pwr.o --omf_browse .\objects\stm32f10x_pwr.crf --depend .\objects\stm32f10x_pwr.d)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\drivers\src\LED\led.c)(0x671A1AEB)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\led.o --omf_browse .\objects\led.crf --depend .\objects\led.d)
|
||||
I (..\boot_source\platform\drivers\inc\led.h)(0x67175BF6)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\platform\drivers\src\EEROM\24cxx.c)(0x67284208)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\24cxx.o --omf_browse .\objects\24cxx.crf --depend .\objects\24cxx.d)
|
||||
I (..\boot_source\platform\drivers\inc\24cxx.h)(0x67285B2C)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\drivers\inc\bsp_i2c_gpio.h)(0x5EDA6162)
|
||||
I (..\boot_source\code_app\driver\inc\dev_config_all.h)(0x671755F9)
|
||||
I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
|
||||
F (..\boot_source\platform\drivers\src\EEROM\bsp_i2c_gpio.c)(0x67283D3C)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\bsp_i2c_gpio.o --omf_browse .\objects\bsp_i2c_gpio.crf --depend .\objects\bsp_i2c_gpio.d)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\drivers\inc\bsp_i2c_gpio.h)(0x5EDA6162)
|
||||
F (..\boot_source\platform\drivers\src\CAN2\can2.c)(0x67231E54)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\can2.o --omf_browse .\objects\can2.crf --depend .\objects\can2.d)
|
||||
I (..\boot_source\platform\drivers\inc\can2.h)(0x67205017)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
F (..\boot_source\platform\drivers\src\flash\ecual_flash.c)(0x67232464)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\ecual_flash.o --omf_browse .\objects\ecual_flash.crf --depend .\objects\ecual_flash.d)
|
||||
I (..\boot_source\code_app\main\inc\config.h)(0x671A0813)
|
||||
I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x6720A9AA)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
F (..\boot_source\code_app\startup\src\stm32f10x_it.c)(0x6718B1A0)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_it.o --omf_browse .\objects\stm32f10x_it.crf --depend .\objects\stm32f10x_it.d)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_it.h)(0x61605442)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\code_app\startup\src\system_stm32f10x.c)(0x6718B1B1)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\code_app\driver\src\dev_flashApi.c)(0x67171677)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_flashapi.o --omf_browse .\objects\dev_flashapi.crf --depend .\objects\dev_flashapi.d)
|
||||
I (..\boot_source\code_app\driver\inc\dev_flashApi.h)(0x67282DED)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
F (..\boot_source\code_app\driver\src\dev_crc32.c)(0x67173C51)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_crc32.o --omf_browse .\objects\dev_crc32.crf --depend .\objects\dev_crc32.d)
|
||||
I (..\boot_source\code_app\driver\inc\dev_crc32.h)(0x67184946)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
F (..\boot_source\code_app\driver\src\dev_sys.c)(0x67208F33)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_sys.o --omf_browse .\objects\dev_sys.crf --depend .\objects\dev_sys.d)
|
||||
I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
F (..\boot_source\code_app\driver\src\dev_eerom.c)(0x67286104)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_eerom.o --omf_browse .\objects\dev_eerom.crf --depend .\objects\dev_eerom.d)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_Com\UDS.c)(0x6729762E)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\uds.o --omf_browse .\objects\uds.crf --depend .\objects\uds.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
|
||||
I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.h)(0x672977E5)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2.c)(0x67242B88)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\iso15765-2.o --omf_browse .\objects\iso15765-2.crf --depend .\objects\iso15765-2.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_entry.c)(0x6721ABCB)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\iso15765-2_entry.o --omf_browse .\objects\iso15765-2_entry.crf --depend .\objects\iso15765-2_entry.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_Com\Can_Transceiver.c)(0x67297613)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\can_transceiver.o --omf_browse .\objects\can_transceiver.crf --depend .\objects\can_transceiver.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\Can_Transceiver.h)(0x67297611)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.c)(0x672974A7)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\diag_eeprom_c301.o --omf_browse .\objects\diag_eeprom_c301.crf --depend .\objects\diag_eeprom_c301.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\driver\inc\dev_flashApi.h)(0x67282DED)
|
||||
I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x67288F56)
|
||||
I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.c)(0x6724308B)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\canconfig_c301.o --omf_browse .\objects\canconfig_c301.crf --depend .\objects\canconfig_c301.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.c)(0x672974D8)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\canctrl_c301.o --omf_browse .\objects\canctrl_c301.crf --depend .\objects\canctrl_c301.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c)(0x672975E0)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\diag_appl_c301.o --omf_browse .\objects\diag_appl_c301.crf --depend .\objects\diag_appl_c301.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.h)(0x672977E5)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
|
||||
I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
|
||||
I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x67288F56)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.h)(0x672444AF)
|
||||
I (..\boot_source\code_app\driver\inc\dev_flashApi.h)(0x67282DED)
|
||||
I (..\boot_source\code_app\driver\inc\dev_eerom.h)(0x672860FC)
|
||||
I (..\boot_source\platform\drivers\inc\24cxx.h)(0x67285B2C)
|
||||
F (..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c)(0x6725BFB7)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\uds_sa_c301.o --omf_browse .\objects\uds_sa_c301.crf --depend .\objects\uds_sa_c301.d)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.h)(0x672444AF)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
F (..\boot_source\code_app\main\src\main.c)(0x6728AF31)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d)
|
||||
I (..\boot_source\code_app\main\inc\main.h)(0x6718CD0E)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\driver\inc\dev_config_all.h)(0x671755F9)
|
||||
I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
|
||||
I (..\boot_source\platform\drivers\inc\platform_driver_inc_all.h)(0x67177546)
|
||||
I (..\boot_source\platform\drivers\inc\led.h)(0x67175BF6)
|
||||
I (..\boot_source\platform\drivers\inc\24cxx.h)(0x67285B2C)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\platform\drivers\inc\can2.h)(0x67205017)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Service_Canstack_CanBus_hongri_All.h)(0x671F598C)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
|
||||
I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
|
||||
I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x67288F56)
|
||||
F (..\boot_source\code_app\app_boot\src\app_can.c)(0x672975E0)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\app_can.o --omf_browse .\objects\app_can.crf --depend .\objects\app_can.d)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
|
||||
I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
|
||||
I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
|
||||
I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
|
||||
I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
|
||||
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
|
||||
I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
|
||||
I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
|
||||
I (..\boot_source\code_app\service\CanStack\canBus_Com\Can_Transceiver.h)(0x67297611)
|
||||
I (..\boot_source\platform\drivers\inc\can2.h)(0x67205017)
|
||||
@ -1,6 +0,0 @@
|
||||
--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
|
||||
-I.\RTE\_hongri_boot
|
||||
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
|
||||
-IC:\Keil_v5\ARM\CMSIS\Include
|
||||
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
|
||||
-o .\objects\if_can.o --omf_browse .\objects\if_can.crf --depend .\objects\if_can.d "..\boot_source\code_app\interface\src\if_can.c"
|
||||
@ -1,6 +0,0 @@
|
||||
--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
|
||||
-I.\RTE\_hongri_boot
|
||||
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
|
||||
-IC:\Keil_v5\ARM\CMSIS\Include
|
||||
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
|
||||
-o .\objects\if_gpio.o --omf_browse .\objects\if_gpio.crf --depend .\objects\if_gpio.d "..\boot_source\code_app\interface\src\if_gpio.c"
|
||||
BIN
boot_project/hongri_boot-GD32F105.uvguix.Administrator
Normal file
BIN
boot_project/hongri_boot-GD32F105.uvguix.Administrator
Normal file
Binary file not shown.
BIN
boot_project/hongri_boot-GD32F105.uvprojx
Normal file
BIN
boot_project/hongri_boot-GD32F105.uvprojx
Normal file
Binary file not shown.
BIN
boot_project/hongri_boot-STM32F105.uvguix.Administrator
Normal file
BIN
boot_project/hongri_boot-STM32F105.uvguix.Administrator
Normal file
Binary file not shown.
BIN
boot_project/hongri_boot-STM32F105.uvprojx
Normal file
BIN
boot_project/hongri_boot-STM32F105.uvprojx
Normal file
Binary file not shown.
Binary file not shown.
BIN
boot_project/hongri_boot.uvmpw
Normal file
BIN
boot_project/hongri_boot.uvmpw
Normal file
Binary file not shown.
BIN
boot_project/hongri_boot.uvmpw.uvgui.Administrator
Normal file
BIN
boot_project/hongri_boot.uvmpw.uvgui.Administrator
Normal file
Binary file not shown.
Binary file not shown.
BIN
boot_project/link_sct/GD32F105Flashdriver.sct
Normal file
BIN
boot_project/link_sct/GD32F105Flashdriver.sct
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
boot_source/code_app/startup/GD32F105/inc/gd32f10x.h
Normal file
BIN
boot_source/code_app/startup/GD32F105/inc/gd32f10x.h
Normal file
Binary file not shown.
60
boot_source/code_app/startup/GD32F105/inc/gd32f10x_it.h
Normal file
60
boot_source/code_app/startup/GD32F105/inc/gd32f10x_it.h
Normal file
@ -0,0 +1,60 @@
|
||||
/*!
|
||||
\file gd32f10x_it.h
|
||||
\brief the header file of the ISR
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_IT_H
|
||||
#define GD32F10X_IT_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* function declarations */
|
||||
/* this function handles NMI exception */
|
||||
void NMI_Handler(void);
|
||||
/* this function handles HardFault exception */
|
||||
void HardFault_Handler(void);
|
||||
/* this function handles MemManage exception */
|
||||
void MemManage_Handler(void);
|
||||
/* this function handles BusFault exception */
|
||||
void BusFault_Handler(void);
|
||||
/* this function handles UsageFault exception */
|
||||
void UsageFault_Handler(void);
|
||||
/* this function handles SVC exception */
|
||||
void SVC_Handler(void);
|
||||
/* this function handles DebugMon exception */
|
||||
void DebugMon_Handler(void);
|
||||
/* this function handles PendSV exception */
|
||||
void PendSV_Handler(void);
|
||||
/* this function handles SysTick exception */
|
||||
void SysTick_Handler(void);
|
||||
|
||||
#endif /* GD32F10X_IT_H */
|
||||
BIN
boot_source/code_app/startup/GD32F105/inc/gd32f10x_libopt.h
Normal file
BIN
boot_source/code_app/startup/GD32F105/inc/gd32f10x_libopt.h
Normal file
Binary file not shown.
BIN
boot_source/code_app/startup/GD32F105/inc/system_gd32f10x.h
Normal file
BIN
boot_source/code_app/startup/GD32F105/inc/system_gd32f10x.h
Normal file
Binary file not shown.
BIN
boot_source/code_app/startup/GD32F105/src/gd32f10x_it.c
Normal file
BIN
boot_source/code_app/startup/GD32F105/src/gd32f10x_it.c
Normal file
Binary file not shown.
BIN
boot_source/code_app/startup/GD32F105/src/system_gd32f10x.c
Normal file
BIN
boot_source/code_app/startup/GD32F105/src/system_gd32f10x.c
Normal file
Binary file not shown.
1638
boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cm3.h
Normal file
1638
boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
637
boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmFunc.h
Normal file
637
boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmFunc.h
Normal file
@ -0,0 +1,637 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V3.30
|
||||
* @date 17. February 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
__ASM volatile ("");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||
__ASM volatile ("");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
@ -0,0 +1,687 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V3.30
|
||||
* @date 17. February 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x.h
Normal file
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x.h
Normal file
Binary file not shown.
60
boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_it.h
Normal file
60
boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_it.h
Normal file
@ -0,0 +1,60 @@
|
||||
/*!
|
||||
\file gd32f10x_it.h
|
||||
\brief the header file of the ISR
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_IT_H
|
||||
#define GD32F10X_IT_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* function declarations */
|
||||
/* this function handles NMI exception */
|
||||
void NMI_Handler(void);
|
||||
/* this function handles HardFault exception */
|
||||
void HardFault_Handler(void);
|
||||
/* this function handles MemManage exception */
|
||||
void MemManage_Handler(void);
|
||||
/* this function handles BusFault exception */
|
||||
void BusFault_Handler(void);
|
||||
/* this function handles UsageFault exception */
|
||||
void UsageFault_Handler(void);
|
||||
/* this function handles SVC exception */
|
||||
void SVC_Handler(void);
|
||||
/* this function handles DebugMon exception */
|
||||
void DebugMon_Handler(void);
|
||||
/* this function handles PendSV exception */
|
||||
void PendSV_Handler(void);
|
||||
/* this function handles SysTick exception */
|
||||
void SysTick_Handler(void);
|
||||
|
||||
#endif /* GD32F10X_IT_H */
|
||||
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_libopt.h
Normal file
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_libopt.h
Normal file
Binary file not shown.
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h
Normal file
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h
Normal file
Binary file not shown.
Binary file not shown.
@ -0,0 +1,369 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_hd.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN = 3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN = 3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_IRQHandler ; 21:RCU
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
|
||||
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
|
||||
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
|
||||
DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
|
||||
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt
|
||||
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt
|
||||
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD ADC2_IRQHandler ; 63:ADC2
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_IRQHandler ; 70:TIMER5
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
HardFault_Handler PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
MemManage_Handler PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
BusFault_Handler PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
UsageFault_Handler PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
DebugMon_Handler PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBD_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
|
||||
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_IRQHandler
|
||||
TIMER0_UP_IRQHandler
|
||||
TIMER0_TRG_CMT_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBD_WKUP_IRQHandler
|
||||
TIMER7_BRK_IRQHandler
|
||||
TIMER7_UP_IRQHandler
|
||||
TIMER7_TRG_CMT_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_4_IRQHandler
|
||||
|
||||
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,326 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_md.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN = 3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN = 3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_IRQHandler ; 21:RCU
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
|
||||
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
|
||||
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
|
||||
DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
HardFault_Handler PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
MemManage_Handler PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
BusFault_Handler PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
UsageFault_Handler PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
DebugMon_Handler PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBD_WKUP_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_IRQHandler
|
||||
TIMER0_UP_IRQHandler
|
||||
TIMER0_TRG_CMT_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBD_WKUP_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
|
||||
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,369 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_xd.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN = 3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN = 3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_IRQHandler ; 21:RCU
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 global
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 global
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
|
||||
DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break Interrupt and TIMER11 global
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update Interrupt and TIMER12 global
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13 global
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD ADC2_IRQHandler ; 63:ADC2
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_IRQHandler ; 70:TIMER5
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
HardFault_Handler PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
MemManage_Handler PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
BusFault_Handler PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
UsageFault_Handler PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
DebugMon_Handler PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC0_1_IRQHandler [WEAK]
|
||||
EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBD_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
|
||||
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC0_1_IRQHandler
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBD_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_4_IRQHandler
|
||||
|
||||
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
Binary file not shown.
@ -0,0 +1,527 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_cl.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; Vector Number 20,FMC
|
||||
DCD RCU_IRQHandler ; Vector Number 21,RCU
|
||||
DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
|
||||
DCD CAN0_TX_IRQHandler ; Vector Number 35,CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; Vector Number 36,CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break
|
||||
DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update
|
||||
DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
|
||||
DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
|
||||
DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
|
||||
DCD SPI0_IRQHandler ; Vector Number 51,SPI0
|
||||
DCD SPI1_IRQHandler ; Vector Number 52,SPI1
|
||||
DCD USART0_IRQHandler ; Vector Number 53,USART0
|
||||
DCD USART1_IRQHandler ; Vector Number 54,USART1
|
||||
DCD USART2_IRQHandler ; Vector Number 55,USART2
|
||||
DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
|
||||
DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line
|
||||
DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt
|
||||
DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt
|
||||
DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt
|
||||
DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; Vector Number 64,EXMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4
|
||||
DCD SPI2_IRQHandler ; Vector Number 67,SPI2
|
||||
DCD UART3_IRQHandler ; Vector Number 68,UART3
|
||||
DCD UART4_IRQHandler ; Vector Number 69,UART4
|
||||
DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5
|
||||
DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; Vector Number 75,DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; Vector Number 76,DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; Vector Number 77,Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; Vector Number 78,Ethernet Wakeup through EXTI line
|
||||
DCD CAN1_TX_IRQHandler ; Vector Number 79,CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; Vector Number 80,CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; Vector Number 81,CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; Vector Number 82,CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; Vector Number 83,USBFS
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, = SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_IRQHandler
|
||||
B RCU_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC0_1_IRQHandler
|
||||
B ADC0_1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_TX_IRQHandler
|
||||
B CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX0_IRQHandler
|
||||
B CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_IRQHandler
|
||||
B TIMER0_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_IRQHandler
|
||||
B TIMER0_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_IRQHandler
|
||||
B TIMER0_TRG_CMT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_IRQHandler
|
||||
B TIMER7_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_IRQHandler
|
||||
B TIMER7_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_IRQHandler
|
||||
B TIMER7_TRG_CMT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK ENET_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_WKUP_IRQHandler
|
||||
B ENET_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_EWMC_IRQHandler
|
||||
B CAN1_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
|
||||
|
||||
END
|
||||
@ -0,0 +1,489 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_hd.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; Vector Number 20,FMC
|
||||
DCD RCU_IRQHandler ; Vector Number 21,RCU
|
||||
DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break
|
||||
DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update
|
||||
DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
|
||||
DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
|
||||
DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
|
||||
DCD SPI0_IRQHandler ; Vector Number 51,SPI0
|
||||
DCD SPI1_IRQHandler ; Vector Number 52,SPI1
|
||||
DCD USART0_IRQHandler ; Vector Number 53,USART0
|
||||
DCD USART1_IRQHandler ; Vector Number 54,USART1
|
||||
DCD USART2_IRQHandler ; Vector Number 55,USART2
|
||||
DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
|
||||
DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line
|
||||
DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt
|
||||
DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt
|
||||
DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt
|
||||
DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare
|
||||
DCD ADC2_IRQHandler ; Vector Number 63,ADC2
|
||||
DCD EXMC_IRQHandler ; Vector Number 64,EXMC
|
||||
DCD SDIO_IRQHandler ; Vector Number 65,SDIO
|
||||
DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4
|
||||
DCD SPI2_IRQHandler ; Vector Number 67,SPI2
|
||||
DCD UART3_IRQHandler ; Vector Number 68,UART3
|
||||
DCD UART4_IRQHandler ; Vector Number 69,UART4
|
||||
DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5
|
||||
DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2
|
||||
DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, = SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_IRQHandler
|
||||
B RCU_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC0_1_IRQHandler
|
||||
B ADC0_1_IRQHandler
|
||||
|
||||
PUBWEAK USBD_HP_CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
B USBD_HP_CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK USBD_LP_CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
B USBD_LP_CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_IRQHandler
|
||||
B TIMER0_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_IRQHandler
|
||||
B TIMER0_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_IRQHandler
|
||||
B TIMER0_TRG_CMT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBD_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_WKUP_IRQHandler
|
||||
B USBD_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_IRQHandler
|
||||
B TIMER7_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_IRQHandler
|
||||
B TIMER7_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_IRQHandler
|
||||
B TIMER7_TRG_CMT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK ADC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC2_IRQHandler
|
||||
B ADC2_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_4_IRQHandler
|
||||
B DMA1_Channel3_4_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,398 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_md.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; Vector Number 20,FMC
|
||||
DCD RCU_IRQHandler ; Vector Number 21,RCU
|
||||
DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break
|
||||
DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update
|
||||
DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
|
||||
DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
|
||||
DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
|
||||
DCD SPI0_IRQHandler ; Vector Number 51,SPI0
|
||||
DCD SPI1_IRQHandler ; Vector Number 52,SPI1
|
||||
DCD USART0_IRQHandler ; Vector Number 53,USART0
|
||||
DCD USART1_IRQHandler ; Vector Number 54,USART1
|
||||
DCD USART2_IRQHandler ; Vector Number 55,USART2
|
||||
DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
|
||||
DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXMC_IRQHandler ; Vector Number 64,EXMC
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, = SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_IRQHandler
|
||||
B RCU_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC0_1_IRQHandler
|
||||
B ADC0_1_IRQHandler
|
||||
|
||||
PUBWEAK USBD_HP_CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
B USBD_HP_CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK USBD_LP_CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
B USBD_LP_CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_IRQHandler
|
||||
B TIMER0_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_IRQHandler
|
||||
B TIMER0_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_IRQHandler
|
||||
B TIMER0_TRG_CMT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBD_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_WKUP_IRQHandler
|
||||
B USBD_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,489 @@
|
||||
;/*!
|
||||
; \file startup_gd32f10x_xd.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
; Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
|
||||
DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; Vector Number 20,FMC
|
||||
DCD RCU_IRQHandler ; Vector Number 21,RCU
|
||||
DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
|
||||
DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
|
||||
DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
|
||||
DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
|
||||
DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
|
||||
DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
|
||||
DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
|
||||
DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
|
||||
DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX
|
||||
DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; Vector Number 40,TIMER0 Break and TIMER8 global
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; Vector Number 41,TIMER0 Update and TIMER9 global
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global
|
||||
DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
|
||||
DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
|
||||
DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
|
||||
DCD SPI0_IRQHandler ; Vector Number 51,SPI0
|
||||
DCD SPI1_IRQHandler ; Vector Number 52,SPI1
|
||||
DCD USART0_IRQHandler ; Vector Number 53,USART0
|
||||
DCD USART1_IRQHandler ; Vector Number 54,USART1
|
||||
DCD USART2_IRQHandler ; Vector Number 55,USART2
|
||||
DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
|
||||
DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
|
||||
DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 global
|
||||
DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare
|
||||
DCD ADC2_IRQHandler ; Vector Number 63,ADC2
|
||||
DCD EXMC_IRQHandler ; Vector Number 64,EXMC
|
||||
DCD SDIO_IRQHandler ; Vector Number 65,SDIO
|
||||
DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4
|
||||
DCD SPI2_IRQHandler ; Vector Number 67,SPI2
|
||||
DCD UART3_IRQHandler ; Vector Number 68,UART3
|
||||
DCD UART4_IRQHandler ; Vector Number 69,UART4
|
||||
DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5
|
||||
DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2
|
||||
DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, = SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_IRQHandler
|
||||
B RCU_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC0_1_IRQHandler
|
||||
B ADC0_1_IRQHandler
|
||||
|
||||
PUBWEAK USBD_HP_CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_HP_CAN0_TX_IRQHandler
|
||||
B USBD_HP_CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK USBD_LP_CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_LP_CAN0_RX0_IRQHandler
|
||||
B USBD_LP_CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
B TIMER0_BRK_TIMER8_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
B TIMER0_UP_TIMER9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBD_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBD_WKUP_IRQHandler
|
||||
B USBD_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
B TIMER7_BRK_TIMER11_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
B TIMER7_UP_TIMER12_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK ADC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC2_IRQHandler
|
||||
B ADC2_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_4_IRQHandler
|
||||
B DMA1_Channel3_4_IRQHandler
|
||||
|
||||
END
|
||||
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Source/gd32f10x_it.c
Normal file
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Source/gd32f10x_it.c
Normal file
Binary file not shown.
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c
Normal file
BIN
boot_source/platform/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c
Normal file
Binary file not shown.
Binary file not shown.
@ -0,0 +1,364 @@
|
||||
/*!
|
||||
\file gd32f10x_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10x_ADC_H
|
||||
#define GD32F10x_ADC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC0 ADC_BASE
|
||||
#define ADC1 (ADC_BASE + 0x400U)
|
||||
#define ADC2 (ADC_BASE + 0x1800U)
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
|
||||
|
||||
/* ADC_SAMPTx x=0..1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx x=0..2 */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
|
||||
#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */
|
||||
|
||||
/* constants definitions */
|
||||
/* adc_stat register value */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||
|
||||
/* scan mode */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
|
||||
/* inserted channel group convert automatically */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
|
||||
/* ADC sync mode */
|
||||
#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
|
||||
#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
|
||||
#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
|
||||
#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
|
||||
|
||||
/* adc_ctl1 register value */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||
|
||||
/* continuous mode */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
|
||||
/* for ADC0 and ADC1 regular channel */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
/* for ADC2 regular channel */
|
||||
#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */
|
||||
|
||||
/* external trigger mode for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
|
||||
/* for ADC0 and ADC1 inserted channel */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */
|
||||
#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
/* for ADC2 inserted channel */
|
||||
#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */
|
||||
|
||||
/* adc_samptx register value */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* adc_ioffx register value */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
||||
|
||||
/* adc_wdht register value */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
||||
|
||||
/* adc_wdlt register value */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
||||
|
||||
/* adc_rsqx register value */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
||||
|
||||
/* adc_isq register value */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
|
||||
/* ADC interrupt */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization config */
|
||||
/* reset ADC */
|
||||
void adc_deinit(uint32_t adc_periph);
|
||||
/* configure the ADC sync mode */
|
||||
void adc_mode_config(uint32_t mode);
|
||||
/* enable or disable ADC special function */
|
||||
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(uint32_t adc_periph);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(uint32_t adc_periph);
|
||||
/* ADC calibration and reset calibration(GD32F10x_MD series without this function) */
|
||||
void adc_calibration_enable(uint32_t adc_periph);
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
|
||||
/* DMA config */
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||
|
||||
/* regular group and inserted group config */
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
|
||||
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
|
||||
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
|
||||
/* configure ADC external trigger */
|
||||
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
||||
|
||||
/* get channel data */
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(uint32_t adc_periph);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
|
||||
/* read the last ADC0 and ADC1 conversion result data in sync mode */
|
||||
uint32_t adc_sync_mode_convert_value_read(void);
|
||||
|
||||
/* watchdog config */
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(uint32_t adc_periph);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
|
||||
/* get the bit state of ADCx software start conversion */
|
||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the bit state of ADCx software inserted channel start conversion */
|
||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
|
||||
|
||||
#endif /* GD32F10x_ADC_H */
|
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,77 @@
|
||||
/*!
|
||||
\file gd32f10x_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_CRC_H
|
||||
#define GD32F10X_CRC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register to the value of initializaiton data register */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32F10X_CRC_H */
|
||||
@ -0,0 +1,249 @@
|
||||
/*!
|
||||
\file gd32f10x_dac.h
|
||||
\brief definitions for the DAC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_DAC_H
|
||||
#define GD32F10X_DAC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* DACx(x=0) definitions */
|
||||
#define DAC0 (DAC_BASE)
|
||||
|
||||
/* registers definitions */
|
||||
#define DAC_CTL0(dacx) REG32((dacx) + 0x00000000U) /*!< DACx control register 0 */
|
||||
#define DAC_SWT(dacx) REG32((dacx) + 0x00000004U) /*!< DACx software trigger register */
|
||||
|
||||
#define DAC_OUT0_R12DH(dacx) REG32((dacx) + 0x00000008U) /*!< DACx_OUT0 12-bit right-aligned data holding register */
|
||||
#define DAC_OUT0_L12DH(dacx) REG32((dacx) + 0x0000000CU) /*!< DACx_OUT0 12-bit left-aligned data holding register */
|
||||
#define DAC_OUT0_R8DH(dacx) REG32((dacx) + 0x00000010U) /*!< DACx_OUT0 8-bit right-aligned data holding register */
|
||||
#define DAC_OUT1_R12DH(dacx) REG32((dacx) + 0x00000014U) /*!< DACx_OUT1 12-bit right-aligned data holding register */
|
||||
#define DAC_OUT1_L12DH(dacx) REG32((dacx) + 0x00000018U) /*!< DACx_OUT1 12-bit left-aligned data holding register */
|
||||
#define DAC_OUT1_R8DH(dacx) REG32((dacx) + 0x0000001CU) /*!< DACx_OUT1 8-bit right-aligned data holding register */
|
||||
#define DACC_R12DH(dacx) REG32((dacx) + 0x00000020U) /*!< DACx concurrent mode 12-bit right-aligned data holding register */
|
||||
#define DACC_L12DH(dacx) REG32((dacx) + 0x00000024U) /*!< DACx concurrent mode 12-bit left-aligned data holding register */
|
||||
#define DACC_R8DH(dacx) REG32((dacx) + 0x00000028U) /*!< DACx concurrent mode 8-bit right-aligned data holding register */
|
||||
#define DAC_OUT0_DO(dacx) REG32((dacx) + 0x0000002CU) /*!< DACx_OUT0 data output register */
|
||||
#define DAC_OUT1_DO(dacx) REG32((dacx) + 0x00000030U) /*!< DACx_OUT1 data output register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DAC_CTL0 */
|
||||
#define DAC_CTL0_DEN0 BIT(0) /*!< DACx_OUT0 enable */
|
||||
#define DAC_CTL0_DBOFF0 BIT(1) /*!< DACx_OUT0 output buffer turn off */
|
||||
#define DAC_CTL0_DTEN0 BIT(2) /*!< DACx_OUT0 trigger enable */
|
||||
#define DAC_CTL0_DTSEL0 BITS(3,5) /*!< DACx_OUT0 trigger selection */
|
||||
#define DAC_CTL0_DWM0 BITS(6,7) /*!< DACx_OUT0 noise wave mode */
|
||||
#define DAC_CTL0_DWBW0 BITS(8,11) /*!< DACx_OUT0 noise wave bit width */
|
||||
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
|
||||
|
||||
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable */
|
||||
#define DAC_CTL0_DBOFF1 BIT(17) /*!< DACx_OUT1 output buffer turn off */
|
||||
#define DAC_CTL0_DTEN1 BIT(18) /*!< DACx_OUT1 trigger enable */
|
||||
#define DAC_CTL0_DTSEL1 BITS(19,21) /*!< DACx_OUT1 trigger selection */
|
||||
#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */
|
||||
#define DAC_CTL0_DWBW1 BITS(24,27) /*!< DACx_OUT1 noise wave bit width */
|
||||
#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DACx_OUT1 DMA enable */
|
||||
|
||||
/* DAC_SWT */
|
||||
#define DAC_SWT_SWTR0 BIT(0) /*!< DACx_OUT0 software trigger */
|
||||
#define DAC_SWT_SWTR1 BIT(1) /*!< DACx_OUT1 software trigger */
|
||||
|
||||
/* DAC_OUT0_R12DH */
|
||||
#define DAC_OUT0_DH_R12 BITS(0,11) /*!< DACx_OUT0 12-bit right-aligned data */
|
||||
|
||||
/* DAC_OUT0_L12DH */
|
||||
#define DAC_OUT0_DH_L12 BITS(4,15) /*!< DACx_OUT0 12-bit left-aligned data */
|
||||
|
||||
/* DAC_OUT0_R8DH */
|
||||
#define DAC_OUT0_DH_R8 BITS(0,7) /*!< DACx_OUT0 8-bit right-aligned data */
|
||||
|
||||
/* DAC_OUT1_R12DH */
|
||||
#define DAC_OUT1_DH_R12 BITS(0,11) /*!< DACx_OUT1 12-bit right-aligned data */
|
||||
|
||||
/* DAC_OUT1_L12DH */
|
||||
#define DAC_OUT1_DH_L12 BITS(4,15) /*!< DACx_OUT1 12-bit left-aligned data */
|
||||
|
||||
/* DAC_OUT1_R8DH */
|
||||
#define DAC_OUT1_DH_R8 BITS(0,7) /*!< DACx_OUT1 8-bit right-aligned data */
|
||||
|
||||
/* DACC_R12DH */
|
||||
#define DACC_OUT0_DH_R12 BITS(0,11) /*!< DAC concurrent mode DACx_OUT0 12-bit right-aligned data */
|
||||
#define DACC_OUT1_DH_R12 BITS(16,27) /*!< DAC concurrent mode DACx_OUT1 12-bit right-aligned data */
|
||||
|
||||
/* DACC_L12DH */
|
||||
#define DACC_OUT0_DH_L12 BITS(4,15) /*!< DAC concurrent mode DACx_OUT0 12-bit left-aligned data */
|
||||
#define DACC_OUT1_DH_L12 BITS(20,31) /*!< DAC concurrent mode DACx_OUT1 12-bit left-aligned data */
|
||||
|
||||
/* DACC_R8DH */
|
||||
#define DACC_OUT0_DH_R8 BITS(0,7) /*!< DAC concurrent mode DACx_OUT0 8-bit right-aligned data */
|
||||
#define DACC_OUT1_DH_R8 BITS(8,15) /*!< DAC concurrent mode DACx_OUT1 8-bit right-aligned data */
|
||||
|
||||
/* DAC_OUT0_DO */
|
||||
#define DAC_OUT0_DO_BITS BITS(0,11) /*!< DACx_OUT0 12-bit output data */
|
||||
|
||||
/* DAC_OUT1_DO */
|
||||
#define DAC_OUT1_DO_BITS BITS(0,11) /*!< DACx_OUT1 12-bit output data */
|
||||
|
||||
/* constants definitions */
|
||||
/* DAC trigger source */
|
||||
#define CTL0_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define DAC_TRIGGER_T5_TRGO CTL0_DTSEL(0) /*!< TIMER5 TRGO */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define DAC_TRIGGER_T7_TRGO CTL0_DTSEL(1) /*!< TIMER7 TRGO */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define DAC_TRIGGER_T2_TRGO CTL0_DTSEL(1) /*!< TIMER2 TRGO */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
#define DAC_TRIGGER_T6_TRGO CTL0_DTSEL(2) /*!< TIMER6 TRGO */
|
||||
#define DAC_TRIGGER_T4_TRGO CTL0_DTSEL(3) /*!< TIMER4 TRGO */
|
||||
#define DAC_TRIGGER_T1_TRGO CTL0_DTSEL(4) /*!< TIMER1 TRGO */
|
||||
#define DAC_TRIGGER_T3_TRGO CTL0_DTSEL(5) /*!< TIMER3 TRGO */
|
||||
#define DAC_TRIGGER_EXTI_9 CTL0_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||
#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(7) /*!< software trigger */
|
||||
|
||||
/* DAC noise wave mode */
|
||||
#define CTL0_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DAC_WAVE_DISABLE CTL0_DWM(0) /*!< wave disabled */
|
||||
#define DAC_WAVE_MODE_LFSR CTL0_DWM(1) /*!< LFSR noise mode */
|
||||
#define DAC_WAVE_MODE_TRIANGLE CTL0_DWM(2) /*!< triangle noise mode */
|
||||
|
||||
/* DAC noise wave bit width */
|
||||
#define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8))
|
||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||
|
||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||
|
||||
/* triangle amplitude in DAC triangle noise mode */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||
|
||||
/* DAC data alignment */
|
||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */
|
||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */
|
||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */
|
||||
|
||||
/* DAC output channel definitions */
|
||||
#define DAC_OUT0 ((uint8_t)0x00U) /*!< DACx_OUT0 channel */
|
||||
#define DAC_OUT1 ((uint8_t)0x01U) /*!< DACx_OUT1 channel */
|
||||
|
||||
/* function declarations */
|
||||
/* DAC initialization functions */
|
||||
/* deinitialize DAC */
|
||||
void dac_deinit(uint32_t dac_periph);
|
||||
/* enable DAC */
|
||||
void dac_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* disable DAC */
|
||||
void dac_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* enable DAC DMA function */
|
||||
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* disable DAC DMA function */
|
||||
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||
|
||||
/* DAC buffer functions */
|
||||
/* enable DAC output buffer */
|
||||
void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* disable DAC output buffer */
|
||||
void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||
|
||||
/* read and write operation functions */
|
||||
/* get DAC output value */
|
||||
uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* set DAC data holding register value */
|
||||
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data);
|
||||
|
||||
/* DAC trigger configuration */
|
||||
/* enable DAC trigger */
|
||||
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* disable DAC trigger */
|
||||
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||
/* configure DAC trigger source */
|
||||
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource);
|
||||
/* enable DAC software trigger */
|
||||
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||
|
||||
/* DAC wave mode configuration */
|
||||
/* configure DAC wave mode */
|
||||
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode);
|
||||
/* configure DAC LFSR noise mode */
|
||||
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits);
|
||||
/* configure DAC triangle noise mode */
|
||||
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude);
|
||||
|
||||
/* DAC concurrent mode configuration */
|
||||
/* enable DAC concurrent mode */
|
||||
void dac_concurrent_enable(uint32_t dac_periph);
|
||||
/* disable DAC concurrent mode */
|
||||
void dac_concurrent_disable(uint32_t dac_periph);
|
||||
/* enable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_enable(uint32_t dac_periph);
|
||||
/* enable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_enable(uint32_t dac_periph);
|
||||
/* disable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_disable(uint32_t dac_periph);
|
||||
/* set DAC concurrent mode data holding register value */
|
||||
void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1);
|
||||
|
||||
#endif /* GD32F10X_DAC_H */
|
||||
@ -0,0 +1,148 @@
|
||||
/*!
|
||||
\file gd32f10x_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_DBG_H
|
||||
#define GD32F10X_DBG_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL */
|
||||
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||
#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
|
||||
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */
|
||||
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
|
||||
#ifdef GD32F10X_CL
|
||||
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
|
||||
#endif /* GD32F10X_CL */
|
||||
#ifdef GD32F10X_XD
|
||||
#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */
|
||||
#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */
|
||||
#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */
|
||||
#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */
|
||||
#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */
|
||||
#endif /* GD32F10X_XD */
|
||||
|
||||
/* constants definitions */
|
||||
/* debug hold when core is halted */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_TIMER7_HOLD = BIT(17), /*!< hold TIMER7 counter when core is halted */
|
||||
DBG_TIMER4_HOLD = BIT(18), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = BIT(19), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = BIT(20), /*!< hold TIMER6 counter when core is halted */
|
||||
#ifdef GD32F10X_CL
|
||||
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
|
||||
#endif /* GD32F10X_CL */
|
||||
#if (defined(GD32F10X_XD) || defined(GD32F10X_CL))
|
||||
DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */
|
||||
DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */
|
||||
DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */
|
||||
DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */
|
||||
DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */
|
||||
DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
|
||||
#endif /* GD32F10X_XD || GD32F10X_CL*/
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* DBG low power mode configurations */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* DBG_CTL0_TRACE_MODE configurations */
|
||||
#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
|
||||
#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
|
||||
#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
|
||||
|
||||
/* function declarations */
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* low power behavior configuration */
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* peripheral behavior configuration */
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
/* trace pin assignment configuration */
|
||||
/* enable trace pin assignment */
|
||||
void dbg_trace_pin_enable(void);
|
||||
/* disable trace pin assignment */
|
||||
void dbg_trace_pin_disable(void);
|
||||
/* set trace pin mode */
|
||||
void dbg_trace_pin_mode_set(uint32_t trace_mode);
|
||||
|
||||
#endif /* GD32F10X_DBG_H */
|
||||
@ -0,0 +1,285 @@
|
||||
/*!
|
||||
\file gd32f10x_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_DMA_H
|
||||
#define GD32F10X_DMA_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
|
||||
|
||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
|
||||
|
||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
|
||||
|
||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
|
||||
|
||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
|
||||
|
||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
|
||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
|
||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
|
||||
#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
|
||||
|
||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
|
||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
|
||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
|
||||
#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL, x=0..6 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT, x=0..6 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR, x=0..6 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR, x=0..6 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA channel 0 */
|
||||
DMA_CH1, /*!< DMA channel 1 */
|
||||
DMA_CH2, /*!< DMA channel 2 */
|
||||
DMA_CH3, /*!< DMA channel 3 */
|
||||
DMA_CH4, /*!< DMA channel 4 */
|
||||
DMA_CH5, /*!< DMA channel 5 */
|
||||
DMA_CH6 /*!< DMA channel 6 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
|
||||
} dma_parameter_struct;
|
||||
|
||||
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_register address */
|
||||
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
|
||||
/* circular mode */
|
||||
#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */
|
||||
#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
|
||||
|
||||
/* memory to memory mode */
|
||||
#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */
|
||||
#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
|
||||
|
||||
/* function declarations */
|
||||
/* DMA deinitialization and initialization functions */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* DMA configuration functions */
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear the flag of a DMA channel */
|
||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear the interrupt flag of a DMA channel */
|
||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32F10X_DMA_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,428 @@
|
||||
/*!
|
||||
\file gd32f10x_exmc.h
|
||||
\brief definitions for the EXMC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_EXMC_H
|
||||
#define GD32F10X_EXMC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* EXMC definitions */
|
||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||
|
||||
/* registers definitions */
|
||||
/* NOR/PSRAM */
|
||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
|
||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
|
||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
|
||||
|
||||
#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */
|
||||
#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */
|
||||
#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */
|
||||
|
||||
#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */
|
||||
#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */
|
||||
#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */
|
||||
|
||||
#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */
|
||||
#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */
|
||||
#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */
|
||||
|
||||
/* NAND/PC card */
|
||||
#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */
|
||||
#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */
|
||||
#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */
|
||||
#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */
|
||||
#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */
|
||||
|
||||
#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */
|
||||
#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */
|
||||
#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */
|
||||
#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */
|
||||
#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */
|
||||
|
||||
#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */
|
||||
#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */
|
||||
#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */
|
||||
#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */
|
||||
#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */
|
||||
|
||||
/* bits definitions */
|
||||
/* NOR/PSRAM */
|
||||
/* EXMC_SNCTLx,x=0..3 */
|
||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
|
||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
|
||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
||||
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
|
||||
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */
|
||||
|
||||
/* EXMC_SNTCFGx,x=0..3 */
|
||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
|
||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
|
||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
|
||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
|
||||
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */
|
||||
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_SNWTCFGx,x=0..3 */
|
||||
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */
|
||||
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */
|
||||
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */
|
||||
#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
|
||||
#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */
|
||||
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* NAND/PC card */
|
||||
/* EXMC_NPCTLx,x=1..3 */
|
||||
#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
|
||||
#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
|
||||
#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
|
||||
#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
|
||||
#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
|
||||
#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
|
||||
#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
|
||||
#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
|
||||
|
||||
/* EXMC_NPINTENx,x=1..3 */
|
||||
#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
|
||||
#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
|
||||
#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
|
||||
#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
|
||||
#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
|
||||
#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
|
||||
#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
|
||||
|
||||
/* EXMC_NPCTCFGx,x=1..3 */
|
||||
#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
|
||||
#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
|
||||
#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
|
||||
#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
|
||||
|
||||
/* EXMC_NPATCFGx,x=1..3 */
|
||||
#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
|
||||
#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
|
||||
#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
|
||||
#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
|
||||
|
||||
/* EXMC_PIOTCFG3 */
|
||||
#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
|
||||
#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
|
||||
#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
|
||||
#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
|
||||
|
||||
/* EXMC_NECCx,x=1,2 */
|
||||
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXMC NOR/SRAM timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t asyn_access_mode; /*!< asynchronous access mode */
|
||||
uint32_t syn_data_latency; /*!< configure the data latency */
|
||||
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
|
||||
uint32_t bus_latency; /*!< configure the bus latency */
|
||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
}exmc_norsram_timing_parameter_struct;
|
||||
|
||||
/* EXMC NOR/SRAM initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
|
||||
uint32_t extended_mode; /*!< enable or disable the extended mode */
|
||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
|
||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||
uint32_t nwait_config; /*!< NWAIT signal configuration */
|
||||
uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
|
||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||
uint32_t burst_mode; /*!< enable or disable the burst mode */
|
||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing
|
||||
parameters for read if the extended mode is used */
|
||||
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */
|
||||
}exmc_norsram_parameter_struct;
|
||||
|
||||
/* EXMC NAND/PC card timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
||||
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
|
||||
uint32_t waittime; /*!< configure the minimum wait time */
|
||||
uint32_t setuptime; /*!< configure the address setup time */
|
||||
}exmc_nand_pccard_timing_parameter_struct;
|
||||
|
||||
/* EXMC NAND initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nand_bank; /*!< select the bank of NAND */
|
||||
uint32_t ecc_size; /*!< the page size for the ECC calculation */
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
|
||||
uint32_t databus_width; /*!< the NAND flash databus width */
|
||||
uint32_t wait_feature; /*!< enables or disables the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||
}exmc_nand_parameter_struct;
|
||||
|
||||
/* EXMC PC card initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t wait_feature; /*!< enables or disables the Wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */
|
||||
}exmc_pccard_parameter_struct;;
|
||||
|
||||
/* EXMC register address */
|
||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
|
||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
|
||||
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */
|
||||
|
||||
#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */
|
||||
#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */
|
||||
#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */
|
||||
#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */
|
||||
#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */
|
||||
|
||||
/* NOR bank memory data bus width */
|
||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
|
||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
|
||||
|
||||
/* NOR bank memory type */
|
||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||
|
||||
/* asynchronous access mode */
|
||||
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
|
||||
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
|
||||
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
|
||||
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
|
||||
|
||||
/* data latency for NOR flash */
|
||||
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */
|
||||
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */
|
||||
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */
|
||||
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */
|
||||
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */
|
||||
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */
|
||||
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */
|
||||
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */
|
||||
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */
|
||||
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */
|
||||
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */
|
||||
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */
|
||||
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */
|
||||
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */
|
||||
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */
|
||||
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */
|
||||
|
||||
/* synchronous clock divide ratio */
|
||||
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
|
||||
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< frequency EXMC_CLK = HCLK/2 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< frequency EXMC_CLK = HCLK/3 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< frequency EXMC_CLK = HCLK/4 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< frequency EXMC_CLK = HCLK/5 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< frequency EXMC_CLK = HCLK/6 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< frequency EXMC_CLK = HCLK/7 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< frequency EXMC_CLK = HCLK/8 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< frequency EXMC_CLK = HCLK/9 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< frequency EXMC_CLK = HCLK/10 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< frequency EXMC_CLK = HCLK/11 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< frequency EXMC_CLK = HCLK/12 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< frequency EXMC_CLK = HCLK/13 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< frequency EXMC_CLK = HCLK/14 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< frequency EXMC_CLK = HCLK/15 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< frequency EXMC_CLK = HCLK/16 */
|
||||
|
||||
/* ECC size */
|
||||
#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */
|
||||
#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */
|
||||
#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */
|
||||
#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */
|
||||
#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */
|
||||
#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */
|
||||
|
||||
/* ALE to RE delay */
|
||||
#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
|
||||
#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
|
||||
|
||||
/* CLE to RE delay */
|
||||
#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
|
||||
#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
|
||||
|
||||
/* NAND bank memory data bus width */
|
||||
#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */
|
||||
#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */
|
||||
|
||||
/* EXMC NOR/SRAM bank region definition */
|
||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
|
||||
|
||||
/* EXMC NOR/SRAM write mode */
|
||||
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
|
||||
#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */
|
||||
|
||||
/* EXMC NWAIT signal configuration */
|
||||
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
|
||||
#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */
|
||||
|
||||
/* EXMC NWAIT signal polarity configuration */
|
||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||
#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
|
||||
|
||||
/* EXMC NAND/PC card bank definition */
|
||||
#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */
|
||||
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */
|
||||
#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */
|
||||
|
||||
/* EXMC flag bits */
|
||||
#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
|
||||
|
||||
/* EXMC interrupt flag bits */
|
||||
#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */
|
||||
#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */
|
||||
#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_deinit(uint32_t norsram_region);
|
||||
/* exmc_norsram_parameter_struct parameter initialize */
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* initialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* EXMC NOR/SRAM bank enable */
|
||||
void exmc_norsram_enable(uint32_t norsram_region);
|
||||
/* EXMC NOR/SRAM bank disable */
|
||||
void exmc_norsram_disable(uint32_t norsram_region);
|
||||
|
||||
/* deinitialize EXMC NAND bank */
|
||||
void exmc_nand_deinit(uint32_t nand_bank);
|
||||
/* initialize EXMC NAND bank */
|
||||
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* exmc_nand_init_struct parameter initialize */
|
||||
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* EXMC NAND bank enable */
|
||||
void exmc_nand_enable(uint32_t nand_bank);
|
||||
/* EXMC NAND bank disable */
|
||||
void exmc_nand_disable(uint32_t nand_bank);
|
||||
/* enable or disable the EXMC NAND ECC function */
|
||||
void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue);
|
||||
/* get the EXMC ECC value */
|
||||
uint32_t exmc_ecc_get(uint32_t nand_bank);
|
||||
|
||||
/* deinitialize EXMC PC card bank */
|
||||
void exmc_pccard_deinit(void);
|
||||
/* initialize EXMC PC card bank */
|
||||
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* exmc_pccard_parameter_struct parameter initialize */
|
||||
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* EXMC PC card bank enable */
|
||||
void exmc_pccard_enable(void);
|
||||
/* EXMC PC card bank disable */
|
||||
void exmc_pccard_disable(void);
|
||||
|
||||
/* enable EXMC interrupt */
|
||||
void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source);
|
||||
/* disable EXMC interrupt */
|
||||
void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source);
|
||||
/* check EXMC flag is set or not */
|
||||
FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag);
|
||||
/* clear EXMC flag */
|
||||
void exmc_flag_clear(uint32_t bank, uint32_t flag);
|
||||
/* check EXMC flag is set or not */
|
||||
FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source);
|
||||
/* clear EXMC flag */
|
||||
void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source);
|
||||
|
||||
#endif /* GD32F10X_EXMC_H */
|
||||
@ -0,0 +1,252 @@
|
||||
/*!
|
||||
\file gd32f10x_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_EXTI_H
|
||||
#define GD32F10X_EXTI_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
|
||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum {
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19) /*!< EXTI line 19 */
|
||||
} exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum {
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
} exti_mode_enum;
|
||||
|
||||
/* interrupt and event trigger mode */
|
||||
typedef enum {
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
||||
} exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization, EXTI lines configuration functions */
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* initialize the EXTI line x */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
/* enable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32F10X_EXTI_H */
|
||||
@ -0,0 +1,366 @@
|
||||
/*!
|
||||
\file gd32f10x_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_FMC_H
|
||||
#define GD32F10X_FMC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option bytes base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
||||
#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
|
||||
#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
|
||||
#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
|
||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
|
||||
#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */
|
||||
#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */
|
||||
#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */
|
||||
#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */
|
||||
#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
|
||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
|
||||
#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
|
||||
#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
|
||||
#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
|
||||
#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */
|
||||
#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
|
||||
/* FMC_KEY0 */
|
||||
#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT0 */
|
||||
#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
|
||||
#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL0 */
|
||||
#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
|
||||
#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
|
||||
#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
|
||||
#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
|
||||
#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
|
||||
/* FMC_ADDR0 */
|
||||
#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
|
||||
#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
|
||||
#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
|
||||
#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */
|
||||
|
||||
/* FMC_WP */
|
||||
#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
|
||||
|
||||
/* FMC_KEY1 */
|
||||
#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */
|
||||
|
||||
/* FMC_STAT1 */
|
||||
#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */
|
||||
#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL1 */
|
||||
#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */
|
||||
#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */
|
||||
#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */
|
||||
#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */
|
||||
#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
|
||||
/* FMC_ADDR1 */
|
||||
#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */
|
||||
|
||||
/* FMC_WSEN */
|
||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the FMC bit position and its register index offset */
|
||||
#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
|
||||
#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||
#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
|
||||
#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||
#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
|
||||
|
||||
/* configuration register */
|
||||
#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
|
||||
#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
|
||||
#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */
|
||||
#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */
|
||||
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
|
||||
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* FMC interrupt enable */
|
||||
typedef enum
|
||||
{
|
||||
FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
|
||||
FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
|
||||
FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */
|
||||
FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */
|
||||
}fmc_int_enum;
|
||||
|
||||
/* FMC flags */
|
||||
typedef enum
|
||||
{
|
||||
FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */
|
||||
FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */
|
||||
FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */
|
||||
FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */
|
||||
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
|
||||
FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */
|
||||
FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */
|
||||
FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */
|
||||
FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */
|
||||
}fmc_flag_enum;
|
||||
|
||||
/* FMC interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */
|
||||
}fmc_interrupt_flag_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* FMC wait state counter */
|
||||
#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
|
||||
#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
|
||||
#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
|
||||
#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */
|
||||
|
||||
/* option bytes software/hardware free watch dog timer */
|
||||
#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
|
||||
#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
|
||||
|
||||
/* option bytes reset or not entering deep sleep mode */
|
||||
#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
|
||||
|
||||
/* option bytes reset or not entering standby mode */
|
||||
#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
|
||||
|
||||
/* option bytes boot bank value */
|
||||
#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */
|
||||
#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */
|
||||
|
||||
#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
|
||||
#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */
|
||||
|
||||
/* OB_SPC */
|
||||
#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */
|
||||
#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */
|
||||
|
||||
/* OB_USER */
|
||||
#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */
|
||||
#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */
|
||||
|
||||
/* OB_WP0 */
|
||||
#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */
|
||||
|
||||
/* OB_WP1 */
|
||||
#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */
|
||||
|
||||
/* OB_WP2 */
|
||||
#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */
|
||||
|
||||
/* OB_WP3 */
|
||||
#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */
|
||||
|
||||
/* option bytes write protection */
|
||||
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
|
||||
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
|
||||
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
|
||||
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
|
||||
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
|
||||
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
|
||||
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
|
||||
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
|
||||
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
|
||||
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
|
||||
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
|
||||
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
|
||||
#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
|
||||
#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
|
||||
#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
|
||||
#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
|
||||
#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
|
||||
#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
|
||||
#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
|
||||
#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
|
||||
#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
|
||||
#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
|
||||
#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
|
||||
#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
|
||||
#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
|
||||
#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
|
||||
#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
|
||||
#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
|
||||
#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
|
||||
#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
|
||||
#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
|
||||
#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */
|
||||
#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
|
||||
|
||||
/* FMC timeout */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */
|
||||
|
||||
/* FMC BANK address */
|
||||
#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */
|
||||
#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */
|
||||
#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* set the FMC wait state counter */
|
||||
void fmc_wscnt_set(uint32_t wscnt);
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* unlock the FMC bank0 operation */
|
||||
void fmc_bank0_unlock(void);
|
||||
/* unlock the FMC bank1 operation */
|
||||
void fmc_bank1_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* lock the bank0 FMC operation */
|
||||
void fmc_bank0_lock(void);
|
||||
/* lock the bank1 FMC operation */
|
||||
void fmc_bank1_lock(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC erase whole bank0 */
|
||||
fmc_state_enum fmc_bank0_erase(void);
|
||||
/* FMC erase whole bank1 */
|
||||
fmc_state_enum fmc_bank1_erase(void);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
/* FMC program a half word at the corresponding address */
|
||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* erase the option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable write protect */
|
||||
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
|
||||
/* configure the option byte security protection */
|
||||
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
|
||||
/* write the FMC option byte */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
|
||||
/* program option bytes data */
|
||||
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
|
||||
/* get the FMC option byte user */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get OB_DATA in register FMC_OBSTAT */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint32_t ob_write_protection_get(void);
|
||||
/* get option byte security protection code value */
|
||||
FlagStatus ob_spc_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* check flag is set or not */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get FMC interrupt flag state */
|
||||
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
|
||||
/* clear FMC interrupt flag state */
|
||||
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
|
||||
/* return the FMC bank0 state */
|
||||
fmc_state_enum fmc_bank0_state_get(void);
|
||||
/* return the FMC bank1 state */
|
||||
fmc_state_enum fmc_bank1_state_get(void);
|
||||
/* check FMC bank0 ready or not */
|
||||
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
|
||||
/* check FMC bank1 ready or not */
|
||||
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
|
||||
|
||||
#endif /* GD32F10X_FMC_H */
|
||||
@ -0,0 +1,111 @@
|
||||
/*!
|
||||
\file gd32f10x_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_FWDGT_H
|
||||
#define GD32F10X_FWDGT_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
|
||||
/* constants definitions */
|
||||
/* psc register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the free watchdog timer counter prescaler value */
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||
/* configure the free watchdog timer counter reload value */
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32F10X_FWDGT_H */
|
||||
Binary file not shown.
@ -0,0 +1,345 @@
|
||||
/*!
|
||||
\file gd32f10x_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_I2C_H
|
||||
#define GD32F10X_I2C_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* I2Cx(x=0,1) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
|
||||
|
||||
/* I2C flags */
|
||||
typedef enum
|
||||
{
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
}i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
|
||||
}i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
|
||||
}i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
|
||||
/* I2C dual-address mode switch */
|
||||
#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
|
||||
#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||
|
||||
/* application function declarations */
|
||||
/* select SMBus type */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C POAP position */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* configure I2C DMA mode */
|
||||
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* configure software reset of I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
/* configure I2C PEC calculation */
|
||||
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* configure whether to transfer PEC value */
|
||||
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* get packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* configure I2C alert through SMBA pin */
|
||||
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* configure I2C ARP protocol in SMBus */
|
||||
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get I2C flag status */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag status */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* get I2C interrupt flag status */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag status */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
|
||||
#endif /* GD32E10X_I2C_H */
|
||||
@ -0,0 +1,91 @@
|
||||
/*!
|
||||
\file gd32f10x_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_MISC_H
|
||||
#define GD32F10X_MISC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U)
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U)
|
||||
|
||||
/* priority group - define the pre-emption priority and the subpriority */
|
||||
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700U) /*!< 0 bits for pre-emption priority, 4 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600U) /*!< 1 bits for pre-emption priority, 3 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500U) /*!< 2 bits for pre-emption priority, 2 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400U) /*!< 3 bits for pre-emption priority, 1 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300U) /*!< 4 bits for pre-emption priority, 0 bits for subpriority */
|
||||
|
||||
/* choose the method to enter or exit the low power mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the low power mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
/* set the priority group */
|
||||
void nvic_priority_group_set(uint32_t nvic_prigroup);
|
||||
|
||||
/* enable NVIC interrupt request */
|
||||
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
|
||||
/* disable NVIC interrupt request */
|
||||
void nvic_irq_disable(uint8_t nvic_irq);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32F10X_MISC_H */
|
||||
@ -0,0 +1,126 @@
|
||||
/*!
|
||||
\file gd32f10x_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_PMU_H
|
||||
#define GD32F10X_PMU_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* LVD functions */
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work in sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work in deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work in standby mode */
|
||||
void pmu_to_standbymode(void);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(void);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(void);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable write access to the registers in backup domain */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable write access to the registers in backup domain */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32F10X_PMU_H */
|
||||
@ -0,0 +1,919 @@
|
||||
/*!
|
||||
\file gd32f10x_rcu.h
|
||||
\brief definitions for the RCU
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_RCU_H
|
||||
#define GD32F10X_RCU_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* RCU definitions */
|
||||
#define RCU RCU_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
|
||||
#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */
|
||||
#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
|
||||
#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
|
||||
#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
|
||||
#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */
|
||||
#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
|
||||
#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
|
||||
#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
|
||||
#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */
|
||||
#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
|
||||
#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */
|
||||
#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
|
||||
#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
|
||||
#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
|
||||
#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */
|
||||
#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
|
||||
#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
|
||||
#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
|
||||
#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */
|
||||
#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */
|
||||
#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */
|
||||
#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* bits definitions */
|
||||
/* RCU_CTL */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
|
||||
#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
|
||||
#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
|
||||
#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
|
||||
#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */
|
||||
#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
|
||||
#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
|
||||
#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
|
||||
#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
|
||||
#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
|
||||
#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
|
||||
#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
|
||||
#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
|
||||
#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */
|
||||
#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
|
||||
#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
|
||||
#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
|
||||
#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
|
||||
#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
|
||||
#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */
|
||||
#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */
|
||||
#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */
|
||||
#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* RCU_CFG0 */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
|
||||
#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
|
||||
#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
|
||||
#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
|
||||
#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
|
||||
#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */
|
||||
#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
|
||||
#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */
|
||||
#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */
|
||||
#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */
|
||||
#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */
|
||||
#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */
|
||||
#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
|
||||
#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
|
||||
#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
|
||||
#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
|
||||
#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
|
||||
#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */
|
||||
#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
|
||||
#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */
|
||||
#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */
|
||||
#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */
|
||||
#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */
|
||||
#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */
|
||||
#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* RCU_INT */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
|
||||
#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
|
||||
#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
|
||||
#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
|
||||
#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
|
||||
#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
|
||||
#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
|
||||
#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
|
||||
#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
|
||||
#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
|
||||
#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
|
||||
#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */
|
||||
#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */
|
||||
#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */
|
||||
#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */
|
||||
#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
|
||||
#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
|
||||
#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
|
||||
#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
|
||||
#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
|
||||
#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
|
||||
#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */
|
||||
#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */
|
||||
#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
|
||||
#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
|
||||
#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
|
||||
#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
|
||||
#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
|
||||
#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
|
||||
#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */
|
||||
#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */
|
||||
#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */
|
||||
#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */
|
||||
#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */
|
||||
#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */
|
||||
#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
|
||||
#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */
|
||||
#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */
|
||||
#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* RCU_APB2RST */
|
||||
#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */
|
||||
#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */
|
||||
#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */
|
||||
#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */
|
||||
#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */
|
||||
#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */
|
||||
#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */
|
||||
#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */
|
||||
#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */
|
||||
#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */
|
||||
#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */
|
||||
#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */
|
||||
#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */
|
||||
#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */
|
||||
#ifndef GD32F10X_CL
|
||||
#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */
|
||||
#endif /* GD32F10X_CL */
|
||||
#ifdef GD32F10X_XD
|
||||
#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */
|
||||
#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */
|
||||
#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */
|
||||
#endif /* GD32F10X_XD */
|
||||
|
||||
/* RCU_APB1RST */
|
||||
#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */
|
||||
#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */
|
||||
#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */
|
||||
#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */
|
||||
#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */
|
||||
#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */
|
||||
#ifdef GD32F10X_XD
|
||||
#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */
|
||||
#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */
|
||||
#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */
|
||||
#endif /* GD32F10X_XD */
|
||||
#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */
|
||||
#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */
|
||||
#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */
|
||||
#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */
|
||||
#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */
|
||||
#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */
|
||||
#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */
|
||||
#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */
|
||||
#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */
|
||||
#ifdef GD32F10X_CL
|
||||
#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */
|
||||
#endif /* GD32F10X_CL */
|
||||
#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */
|
||||
#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */
|
||||
#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */
|
||||
|
||||
/* RCU_AHBEN */
|
||||
#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */
|
||||
#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */
|
||||
#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */
|
||||
#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */
|
||||
#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */
|
||||
#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */
|
||||
#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */
|
||||
#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */
|
||||
#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* RCU_APB2EN */
|
||||
#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */
|
||||
#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */
|
||||
#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */
|
||||
#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */
|
||||
#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */
|
||||
#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */
|
||||
#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */
|
||||
#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */
|
||||
#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */
|
||||
#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */
|
||||
#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */
|
||||
#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */
|
||||
#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */
|
||||
#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */
|
||||
#ifndef GD32F10X_CL
|
||||
#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */
|
||||
#endif /* GD32F10X_CL */
|
||||
#ifdef GD32F10X_XD
|
||||
#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */
|
||||
#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */
|
||||
#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */
|
||||
#endif /* GD32F10X_XD */
|
||||
|
||||
/* RCU_APB1EN */
|
||||
#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */
|
||||
#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */
|
||||
#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */
|
||||
#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */
|
||||
#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */
|
||||
#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */
|
||||
#ifdef GD32F10X_XD
|
||||
#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */
|
||||
#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */
|
||||
#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */
|
||||
#endif /* GD32F10X_XD */
|
||||
#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */
|
||||
#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */
|
||||
#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */
|
||||
#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */
|
||||
#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */
|
||||
#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */
|
||||
#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */
|
||||
#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */
|
||||
#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */
|
||||
#ifdef GD32F10X_CL
|
||||
#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */
|
||||
#endif /* GD32F10X_CL */
|
||||
#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */
|
||||
#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */
|
||||
#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */
|
||||
|
||||
/* RCU_BDCTL */
|
||||
#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */
|
||||
#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */
|
||||
#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */
|
||||
#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */
|
||||
#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */
|
||||
#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */
|
||||
|
||||
/* RCU_RSTSCK */
|
||||
#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */
|
||||
#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */
|
||||
#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */
|
||||
#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */
|
||||
#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */
|
||||
#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */
|
||||
#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */
|
||||
#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */
|
||||
#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */
|
||||
|
||||
#ifdef GD32F10X_CL
|
||||
/* RCU_AHBRST */
|
||||
#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */
|
||||
#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */
|
||||
#endif /* GD32F10X_CL */
|
||||
|
||||
#if defined(GD32F10X_CL)
|
||||
/* RCU_CFG1 */
|
||||
#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */
|
||||
#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */
|
||||
#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */
|
||||
#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */
|
||||
#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */
|
||||
#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */
|
||||
#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */
|
||||
#endif /* GD32F10X_CL */
|
||||
|
||||
/* RCU_DSV */
|
||||
#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the peripheral clock enable bit position and its register index offset */
|
||||
#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
|
||||
#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register offset */
|
||||
/* peripherals enable */
|
||||
#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */
|
||||
#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */
|
||||
#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */
|
||||
|
||||
/* peripherals reset */
|
||||
#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */
|
||||
#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */
|
||||
#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */
|
||||
#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */
|
||||
|
||||
/* clock control */
|
||||
#define CTL_REG_OFFSET 0x00U /*!< control register offset */
|
||||
#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */
|
||||
|
||||
/* clock stabilization and stuck interrupt */
|
||||
#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */
|
||||
|
||||
/* configuration register */
|
||||
#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */
|
||||
#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */
|
||||
|
||||
/* peripheral clock enable */
|
||||
typedef enum
|
||||
{
|
||||
/* AHB peripherals */
|
||||
RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
|
||||
RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
|
||||
RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */
|
||||
RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */
|
||||
#elif defined(GD32F10X_CL)
|
||||
RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */
|
||||
RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */
|
||||
RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */
|
||||
RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* APB1 peripherals */
|
||||
RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */
|
||||
RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */
|
||||
RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */
|
||||
RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */
|
||||
RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */
|
||||
RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */
|
||||
#if defined(GD32F10X_XD)
|
||||
RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */
|
||||
RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */
|
||||
RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */
|
||||
#endif /* GD32F10X_XD */
|
||||
RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */
|
||||
RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */
|
||||
RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */
|
||||
RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */
|
||||
RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */
|
||||
RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */
|
||||
RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */
|
||||
RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */
|
||||
RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */
|
||||
#endif /* GD32F10X_CL */
|
||||
RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */
|
||||
RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */
|
||||
RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */
|
||||
RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */
|
||||
|
||||
/* APB2 peripherals */
|
||||
RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */
|
||||
RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */
|
||||
RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */
|
||||
RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */
|
||||
RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */
|
||||
RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */
|
||||
RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */
|
||||
RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */
|
||||
RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */
|
||||
RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */
|
||||
RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */
|
||||
RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */
|
||||
RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */
|
||||
RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */
|
||||
#ifndef GD32F10X_CL
|
||||
RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */
|
||||
#endif /* GD32F10X_CL */
|
||||
#ifdef GD32F10X_XD
|
||||
RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */
|
||||
RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */
|
||||
RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */
|
||||
#endif /* GD32F10X_XD */
|
||||
}rcu_periph_enum;
|
||||
|
||||
/* peripheral clock enable when sleep mode*/
|
||||
typedef enum
|
||||
{
|
||||
/* AHB peripherals */
|
||||
RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
|
||||
RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
|
||||
}rcu_periph_sleep_enum;
|
||||
|
||||
/* peripherals reset */
|
||||
typedef enum
|
||||
{
|
||||
/* AHB peripherals */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
|
||||
RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */
|
||||
#endif /* GD32F10X_CL */
|
||||
|
||||
/* APB1 peripherals */
|
||||
RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */
|
||||
RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */
|
||||
RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */
|
||||
RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */
|
||||
RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */
|
||||
RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */
|
||||
#ifdef GD32F10X_XD
|
||||
RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */
|
||||
RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */
|
||||
RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */
|
||||
#endif /* GD32F10X_XD */
|
||||
RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */
|
||||
RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */
|
||||
RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */
|
||||
RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */
|
||||
RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */
|
||||
RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */
|
||||
RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */
|
||||
RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */
|
||||
RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */
|
||||
#endif /* GD32F10X_CL */
|
||||
RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */
|
||||
RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */
|
||||
RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */
|
||||
|
||||
/* APB2 peripherals */
|
||||
RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */
|
||||
RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */
|
||||
RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */
|
||||
RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */
|
||||
RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */
|
||||
RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */
|
||||
RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */
|
||||
RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */
|
||||
RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */
|
||||
RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */
|
||||
RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */
|
||||
RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */
|
||||
RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */
|
||||
RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */
|
||||
#ifndef GD32F10X_CL
|
||||
RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */
|
||||
#endif /* GD32F10X_CL */
|
||||
#ifdef GD32F10X_XD
|
||||
RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */
|
||||
RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */
|
||||
RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */
|
||||
#endif /* GD32F10X_XD */
|
||||
}rcu_periph_reset_enum;
|
||||
|
||||
/* clock stabilization and peripheral reset flags */
|
||||
typedef enum
|
||||
{
|
||||
/* clock stabilization flags */
|
||||
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
|
||||
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
|
||||
RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */
|
||||
RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */
|
||||
#endif /* GD32F10X_CL */
|
||||
RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */
|
||||
RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */
|
||||
/* reset source flags */
|
||||
RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */
|
||||
RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */
|
||||
RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */
|
||||
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */
|
||||
RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */
|
||||
RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */
|
||||
}rcu_flag_enum;
|
||||
|
||||
/* clock stabilization and ckm interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
|
||||
RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
|
||||
RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
|
||||
RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */
|
||||
RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */
|
||||
RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */
|
||||
#endif /* GD32F10X_CL */
|
||||
RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */
|
||||
}rcu_int_flag_enum;
|
||||
|
||||
/* clock stabilization and stuck interrupt flags clear */
|
||||
typedef enum
|
||||
{
|
||||
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */
|
||||
#endif /* GD32F10X_CL */
|
||||
RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */
|
||||
}rcu_int_flag_clear_enum;
|
||||
|
||||
/* clock stabilization interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
|
||||
RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
|
||||
RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
|
||||
RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */
|
||||
RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */
|
||||
RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
|
||||
#endif /* GD32F10X_CL */
|
||||
}rcu_int_enum;
|
||||
|
||||
/* oscillator types */
|
||||
typedef enum
|
||||
{
|
||||
RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */
|
||||
RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */
|
||||
RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */
|
||||
RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */
|
||||
RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */
|
||||
#ifdef GD32F10X_CL
|
||||
RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */
|
||||
RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */
|
||||
#endif /* GD32F10X_CL */
|
||||
}rcu_osci_type_enum;
|
||||
|
||||
/* rcu clock frequency */
|
||||
typedef enum
|
||||
{
|
||||
CK_SYS = 0, /*!< system clock */
|
||||
CK_AHB, /*!< AHB clock */
|
||||
CK_APB1, /*!< APB1 clock */
|
||||
CK_APB2, /*!< APB2 clock */
|
||||
}rcu_clock_freq_enum;
|
||||
|
||||
/* RCU_CFG0 register bit define */
|
||||
/* system clock source select */
|
||||
#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */
|
||||
#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */
|
||||
#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */
|
||||
|
||||
/* system clock source select status */
|
||||
#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */
|
||||
#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */
|
||||
#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */
|
||||
|
||||
/* AHB prescaler selection */
|
||||
#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */
|
||||
#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */
|
||||
#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */
|
||||
#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */
|
||||
#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */
|
||||
#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */
|
||||
#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */
|
||||
#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */
|
||||
#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */
|
||||
|
||||
/* APB1 prescaler selection */
|
||||
#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
|
||||
#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */
|
||||
#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */
|
||||
#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */
|
||||
#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */
|
||||
#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */
|
||||
|
||||
/* APB2 prescaler selection */
|
||||
#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
|
||||
#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */
|
||||
#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */
|
||||
#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */
|
||||
#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */
|
||||
#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */
|
||||
|
||||
/* ADC prescaler select */
|
||||
#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */
|
||||
#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */
|
||||
#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */
|
||||
#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */
|
||||
#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */
|
||||
#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */
|
||||
|
||||
/* PLL clock source selection */
|
||||
#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */
|
||||
#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */
|
||||
|
||||
/* PLL clock multiplication factor */
|
||||
#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */
|
||||
|
||||
#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
|
||||
#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */
|
||||
#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */
|
||||
#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */
|
||||
#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */
|
||||
#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */
|
||||
#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */
|
||||
#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */
|
||||
#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */
|
||||
#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */
|
||||
#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */
|
||||
#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */
|
||||
#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */
|
||||
#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */
|
||||
#elif defined(GD32F10X_CL)
|
||||
#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */
|
||||
#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */
|
||||
#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */
|
||||
#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */
|
||||
#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */
|
||||
#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */
|
||||
#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */
|
||||
#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */
|
||||
#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */
|
||||
#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */
|
||||
#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */
|
||||
#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */
|
||||
#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */
|
||||
#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */
|
||||
#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */
|
||||
#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */
|
||||
#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */
|
||||
|
||||
/* USBD/USBFS prescaler select */
|
||||
#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
|
||||
#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */
|
||||
#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */
|
||||
#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */
|
||||
#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */
|
||||
|
||||
/* CKOUT0 clock source selection */
|
||||
#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */
|
||||
#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */
|
||||
#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */
|
||||
#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */
|
||||
#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */
|
||||
#ifdef GD32F10X_CL
|
||||
#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */
|
||||
#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */
|
||||
#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */
|
||||
#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */
|
||||
#endif /* GD32F10X_CL */
|
||||
|
||||
/* RTC clock entry selection */
|
||||
#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */
|
||||
#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */
|
||||
#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */
|
||||
#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */
|
||||
|
||||
/* PREDV0 division factor */
|
||||
#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */
|
||||
#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */
|
||||
#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */
|
||||
#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */
|
||||
#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */
|
||||
#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */
|
||||
#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */
|
||||
#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */
|
||||
#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */
|
||||
#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */
|
||||
#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */
|
||||
#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */
|
||||
#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */
|
||||
#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */
|
||||
#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */
|
||||
#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */
|
||||
|
||||
/* PREDV1 division factor */
|
||||
#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */
|
||||
#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */
|
||||
#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */
|
||||
#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */
|
||||
#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */
|
||||
#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */
|
||||
#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */
|
||||
#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */
|
||||
#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */
|
||||
#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */
|
||||
#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */
|
||||
#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */
|
||||
#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */
|
||||
#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */
|
||||
#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */
|
||||
#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */
|
||||
|
||||
/* PLL1 clock multiplication factor */
|
||||
#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */
|
||||
#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */
|
||||
#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */
|
||||
#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */
|
||||
#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */
|
||||
#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */
|
||||
#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */
|
||||
#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */
|
||||
#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */
|
||||
#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */
|
||||
|
||||
/* PLL2 clock multiplication factor */
|
||||
#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12))
|
||||
#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */
|
||||
#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */
|
||||
#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */
|
||||
#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */
|
||||
#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */
|
||||
#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */
|
||||
#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */
|
||||
#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */
|
||||
#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */
|
||||
#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */
|
||||
|
||||
#ifdef GD32F10X_CL
|
||||
/* PREDV0 input clock source selection */
|
||||
#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */
|
||||
#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */
|
||||
|
||||
/* I2S1 clock source selection */
|
||||
#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */
|
||||
#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */
|
||||
|
||||
/* I2S2 clock source selection */
|
||||
#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */
|
||||
#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */
|
||||
#endif /* GD32F10X_CL */
|
||||
|
||||
/* deep-sleep mode voltage */
|
||||
#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */
|
||||
#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */
|
||||
#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */
|
||||
#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization, peripheral clock enable/disable functions */
|
||||
/* deinitialize the RCU */
|
||||
void rcu_deinit(void);
|
||||
/* enable the peripherals clock */
|
||||
void rcu_periph_clock_enable(rcu_periph_enum periph);
|
||||
/* disable the peripherals clock */
|
||||
void rcu_periph_clock_disable(rcu_periph_enum periph);
|
||||
/* enable the peripherals clock when sleep mode */
|
||||
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
|
||||
/* disable the peripherals clock when sleep mode */
|
||||
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
|
||||
/* reset the peripherals */
|
||||
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
|
||||
/* disable reset the peripheral */
|
||||
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
|
||||
/* reset the BKP domain */
|
||||
void rcu_bkp_reset_enable(void);
|
||||
/* disable the BKP domain reset */
|
||||
void rcu_bkp_reset_disable(void);
|
||||
|
||||
/* clock configuration functions */
|
||||
/* configure the system clock source */
|
||||
void rcu_system_clock_source_config(uint32_t ck_sys);
|
||||
/* get the system clock source */
|
||||
uint32_t rcu_system_clock_source_get(void);
|
||||
/* configure the AHB prescaler selection */
|
||||
void rcu_ahb_clock_config(uint32_t ck_ahb);
|
||||
/* configure the APB1 prescaler selection */
|
||||
void rcu_apb1_clock_config(uint32_t ck_apb1);
|
||||
/* configure the APB2 prescaler selection */
|
||||
void rcu_apb2_clock_config(uint32_t ck_apb2);
|
||||
/* configure the CK_OUT0 clock source and divider */
|
||||
void rcu_ckout0_config(uint32_t ckout0_src);
|
||||
/* configure the PLL clock source selection and PLL multiply factor */
|
||||
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
|
||||
#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
|
||||
/* configure the PREDV0 division factor and clock source */
|
||||
void rcu_predv0_config(uint32_t predv0_div);
|
||||
#elif defined(GD32F10X_CL)
|
||||
/* configure the PREDV0 division factor and clock source */
|
||||
void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div);
|
||||
/* configure the PREDV1 division factor */
|
||||
void rcu_predv1_config(uint32_t predv1_div);
|
||||
/* configure the PLL1 clock */
|
||||
void rcu_pll1_config(uint32_t pll_mul);
|
||||
/* configure the PLL2 clock */
|
||||
void rcu_pll2_config(uint32_t pll_mul);
|
||||
#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
|
||||
|
||||
/* peripheral clock configuration functions */
|
||||
/* configure the ADC division factor */
|
||||
void rcu_adc_clock_config(uint32_t adc_psc);
|
||||
/* configure the USBD/USBFS prescaler factor */
|
||||
void rcu_usb_clock_config(uint32_t usb_psc);
|
||||
/* configure the RTC clock source selection */
|
||||
void rcu_rtc_clock_config(uint32_t rtc_clock_source);
|
||||
#ifdef GD32F10X_CL
|
||||
/* configure the I2S1 clock source selection */
|
||||
void rcu_i2s1_clock_config(uint32_t i2s_clock_source);
|
||||
/* configure the I2S2 clock source selection */
|
||||
void rcu_i2s2_clock_config(uint32_t i2s_clock_source);
|
||||
#endif /* GD32F10X_CL */
|
||||
|
||||
/* oscillator configuration functions */
|
||||
/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
|
||||
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
|
||||
/* turn on the oscillator */
|
||||
void rcu_osci_on(rcu_osci_type_enum osci);
|
||||
/* turn off the oscillator */
|
||||
void rcu_osci_off(rcu_osci_type_enum osci);
|
||||
/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
|
||||
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
|
||||
/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
|
||||
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
|
||||
/* enable the HXTAL clock monitor */
|
||||
void rcu_hxtal_clock_monitor_enable(void);
|
||||
/* disable the HXTAL clock monitor */
|
||||
void rcu_hxtal_clock_monitor_disable(void);
|
||||
|
||||
/* set the IRC8M adjust value */
|
||||
void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
|
||||
/* set the deep sleep mode voltage */
|
||||
void rcu_deepsleep_voltage_set(uint32_t dsvol);
|
||||
/* get the system clock, bus and peripheral clock frequency */
|
||||
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get the clock stabilization and periphral reset flags */
|
||||
FlagStatus rcu_flag_get(rcu_flag_enum flag);
|
||||
/* clear the reset flag */
|
||||
void rcu_all_reset_flag_clear(void);
|
||||
/* get the clock stabilization interrupt and ckm flags */
|
||||
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
|
||||
/* clear the interrupt flags */
|
||||
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
|
||||
/* enable the stabilization interrupt */
|
||||
void rcu_interrupt_enable(rcu_int_enum stab_int);
|
||||
/* disable the stabilization interrupt */
|
||||
void rcu_interrupt_disable(rcu_int_enum stab_int);
|
||||
|
||||
#endif /* GD32F10X_RCU_H */
|
||||
@ -0,0 +1,148 @@
|
||||
/*!
|
||||
\file gd32f10x_rtc.h
|
||||
\brief definitions for the RTC
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_RTC_H
|
||||
#define GD32F10X_RTC_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* RTC definitions */
|
||||
#define RTC RTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
|
||||
#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
|
||||
#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
|
||||
#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
|
||||
#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
|
||||
#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
|
||||
#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
|
||||
#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
|
||||
#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
|
||||
#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTC_INTEN */
|
||||
#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
|
||||
#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
|
||||
#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC_CTL */
|
||||
#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
|
||||
#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
|
||||
#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
|
||||
#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
|
||||
#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
|
||||
#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
|
||||
|
||||
/* RTC_PSCH */
|
||||
#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
|
||||
|
||||
/* RTC_PSCL */
|
||||
#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
|
||||
|
||||
/* RTC_DIVH */
|
||||
#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
|
||||
|
||||
/* RTC_DIVL */
|
||||
#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
|
||||
|
||||
/* RTC_CNTH */
|
||||
#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
|
||||
|
||||
/* RTC_CNTL */
|
||||
#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
|
||||
|
||||
/* RTC_ALRMH */
|
||||
#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
|
||||
|
||||
/* RTC_ALRML */
|
||||
#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
|
||||
|
||||
/* constants definitions */
|
||||
/* RTC interrupt enable or disable definitions */
|
||||
#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
|
||||
#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
|
||||
#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
|
||||
|
||||
/* RTC interrupt flag definitions */
|
||||
#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
|
||||
/* RTC flag definitions */
|
||||
#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
|
||||
#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
|
||||
#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
|
||||
#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
|
||||
#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* enter RTC configuration mode */
|
||||
void rtc_configuration_mode_enter(void);
|
||||
/* exit RTC configuration mode */
|
||||
void rtc_configuration_mode_exit(void);
|
||||
/* set RTC counter value */
|
||||
void rtc_counter_set(uint32_t cnt);
|
||||
/* set RTC prescaler value */
|
||||
void rtc_prescaler_set(uint32_t psc);
|
||||
|
||||
/* operation functions */
|
||||
/* wait RTC last write operation finished flag set */
|
||||
void rtc_lwoff_wait(void);
|
||||
/* wait RTC registers synchronized flag set */
|
||||
void rtc_register_sync_wait(void);
|
||||
/* set RTC alarm value */
|
||||
void rtc_alarm_config(uint32_t alarm);
|
||||
/* get RTC counter value */
|
||||
uint32_t rtc_counter_get(void);
|
||||
/* get RTC divider value */
|
||||
uint32_t rtc_divider_get(void);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* get RTC flag status */
|
||||
FlagStatus rtc_flag_get(uint32_t flag);
|
||||
/* clear RTC flag status */
|
||||
void rtc_flag_clear(uint32_t flag);
|
||||
/* get RTC interrupt flag status */
|
||||
FlagStatus rtc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear RTC interrupt flag status */
|
||||
void rtc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable RTC interrupt */
|
||||
void rtc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable RTC interrupt */
|
||||
void rtc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F10X_RTC_H */
|
||||
@ -0,0 +1,430 @@
|
||||
/*!
|
||||
\file gd32f10x_sdio.h
|
||||
\brief definitions for the SDIO
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_SDIO_H
|
||||
#define GD32F10X_SDIO_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* SDIO definitions */
|
||||
#define SDIO SDIO_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */
|
||||
#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */
|
||||
#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */
|
||||
#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */
|
||||
#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */
|
||||
#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */
|
||||
#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */
|
||||
#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */
|
||||
#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */
|
||||
#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */
|
||||
#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */
|
||||
#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */
|
||||
#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */
|
||||
#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */
|
||||
#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */
|
||||
#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */
|
||||
#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */
|
||||
#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */
|
||||
|
||||
/* bits definitions */
|
||||
/* SDIO_PWRCTL */
|
||||
#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
|
||||
|
||||
/* SDIO_CLKCTL */
|
||||
#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */
|
||||
#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */
|
||||
#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
|
||||
#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */
|
||||
#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */
|
||||
#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */
|
||||
#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */
|
||||
|
||||
/* SDIO_CMDAGMT */
|
||||
#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
|
||||
|
||||
/* SDIO_CMDCTL */
|
||||
#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
|
||||
#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */
|
||||
#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */
|
||||
#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */
|
||||
#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */
|
||||
#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */
|
||||
#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */
|
||||
#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */
|
||||
#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */
|
||||
|
||||
/* SDIO_DATATO */
|
||||
#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
|
||||
|
||||
/* SDIO_DATALEN */
|
||||
#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
|
||||
|
||||
/* SDIO_DATACTL */
|
||||
#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
|
||||
#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
|
||||
#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */
|
||||
#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */
|
||||
#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
|
||||
#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */
|
||||
#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */
|
||||
#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */
|
||||
#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */
|
||||
|
||||
/* SDIO_STAT */
|
||||
#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
|
||||
#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
|
||||
#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
|
||||
#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
|
||||
#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
|
||||
#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
|
||||
#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
|
||||
#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
|
||||
#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */
|
||||
#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */
|
||||
#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
|
||||
#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */
|
||||
#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */
|
||||
#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */
|
||||
#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
|
||||
#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
|
||||
#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
|
||||
#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
|
||||
#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
|
||||
#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
|
||||
#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */
|
||||
#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */
|
||||
#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
|
||||
#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */
|
||||
|
||||
/* SDIO_INTC */
|
||||
#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
|
||||
#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
|
||||
#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
|
||||
#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
|
||||
#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
|
||||
#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
|
||||
#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
|
||||
#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
|
||||
#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
|
||||
#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */
|
||||
#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
|
||||
#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
|
||||
#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */
|
||||
|
||||
/* SDIO_INTEN */
|
||||
#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
|
||||
#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
|
||||
#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
|
||||
#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
|
||||
#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
|
||||
#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
|
||||
#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
|
||||
#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
|
||||
#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
|
||||
#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */
|
||||
#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
|
||||
#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */
|
||||
#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */
|
||||
#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */
|
||||
#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
|
||||
#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
|
||||
#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */
|
||||
#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
|
||||
#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
|
||||
#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */
|
||||
#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */
|
||||
#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */
|
||||
#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
|
||||
#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */
|
||||
|
||||
/* SDIO_FIFO */
|
||||
#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */
|
||||
|
||||
/* constants definitions */
|
||||
/* SDIO flags */
|
||||
#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
|
||||
#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
|
||||
#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
|
||||
#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
|
||||
#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
|
||||
#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
|
||||
#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
|
||||
#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
|
||||
#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
|
||||
#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */
|
||||
#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
|
||||
#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */
|
||||
#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */
|
||||
#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */
|
||||
#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
|
||||
#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
|
||||
#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
|
||||
#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
|
||||
#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
|
||||
#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
|
||||
#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */
|
||||
#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */
|
||||
#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
|
||||
#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */
|
||||
|
||||
/* SDIO interrupt enable or disable */
|
||||
#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
|
||||
#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
|
||||
#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
|
||||
#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
|
||||
#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
|
||||
#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
|
||||
#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
|
||||
#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
|
||||
#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
|
||||
#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */
|
||||
#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
|
||||
#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
|
||||
#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
|
||||
#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
|
||||
#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
|
||||
#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
|
||||
#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */
|
||||
#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
|
||||
#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
|
||||
#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */
|
||||
#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
|
||||
#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
|
||||
#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
|
||||
#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
|
||||
|
||||
/* SDIO interrupt flags */
|
||||
#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */
|
||||
#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */
|
||||
#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */
|
||||
#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */
|
||||
#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */
|
||||
#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */
|
||||
#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */
|
||||
#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */
|
||||
#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */
|
||||
#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */
|
||||
#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */
|
||||
#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */
|
||||
#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */
|
||||
#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */
|
||||
#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */
|
||||
#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */
|
||||
#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */
|
||||
#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */
|
||||
|
||||
/* SDIO power control */
|
||||
#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
|
||||
#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
|
||||
|
||||
/* SDIO card bus mode control */
|
||||
#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
|
||||
#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
|
||||
#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
|
||||
|
||||
/* SDIO_CLK clock edge selection */
|
||||
#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
|
||||
#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
|
||||
|
||||
/* clock bypass enable or disable */
|
||||
#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */
|
||||
#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */
|
||||
|
||||
/* SDIO_CLK clock dynamic switch on/off for power saving */
|
||||
#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */
|
||||
#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
|
||||
|
||||
/* SDIO command response type */
|
||||
#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
|
||||
#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
|
||||
#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
|
||||
|
||||
/* command state machine wait type */
|
||||
#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */
|
||||
#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
|
||||
#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
|
||||
|
||||
#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */
|
||||
#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */
|
||||
#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */
|
||||
#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */
|
||||
|
||||
/* SDIO data block size */
|
||||
#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
|
||||
#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
|
||||
#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
|
||||
|
||||
/* SDIO data transfer mode */
|
||||
#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */
|
||||
#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */
|
||||
|
||||
/* SDIO data transfer direction */
|
||||
#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */
|
||||
#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
|
||||
|
||||
/* SDIO read wait type */
|
||||
#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */
|
||||
#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
|
||||
|
||||
/* function declarations */
|
||||
/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */
|
||||
/* deinitialize the SDIO */
|
||||
void sdio_deinit(void);
|
||||
/* configure the SDIO clock */
|
||||
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
|
||||
/* enable hardware clock control */
|
||||
void sdio_hardware_clock_enable(void);
|
||||
/* disable hardware clock control */
|
||||
void sdio_hardware_clock_disable(void);
|
||||
/* set different SDIO card bus mode */
|
||||
void sdio_bus_mode_set(uint32_t bus_mode);
|
||||
/* set the SDIO power state */
|
||||
void sdio_power_state_set(uint32_t power_state);
|
||||
/* get the SDIO power state */
|
||||
uint32_t sdio_power_state_get(void);
|
||||
/* enable SDIO_CLK clock output */
|
||||
void sdio_clock_enable(void);
|
||||
/* disable SDIO_CLK clock output */
|
||||
void sdio_clock_disable(void);
|
||||
|
||||
/* configure the command index, argument, response type, wait type and CSM to send command functions */
|
||||
/* configure the command and response */
|
||||
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
|
||||
/* set the command state machine wait type */
|
||||
void sdio_wait_type_set(uint32_t wait_type);
|
||||
/* enable the CSM(command state machine) */
|
||||
void sdio_csm_enable(void);
|
||||
/* disable the CSM(command state machine) */
|
||||
void sdio_csm_disable(void);
|
||||
/* get the last response command index */
|
||||
uint8_t sdio_command_index_get(void);
|
||||
/* get the response for the last received command */
|
||||
uint32_t sdio_response_get(uint32_t responsex);
|
||||
|
||||
/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */
|
||||
/* configure the data timeout, data length and data block size */
|
||||
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
|
||||
/* configure the data transfer mode and direction */
|
||||
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
|
||||
/* enable the DSM(data state machine) for data transfer */
|
||||
void sdio_dsm_enable(void);
|
||||
/* disable the DSM(data state machine) */
|
||||
void sdio_dsm_disable(void);
|
||||
/* write data(one word) to the transmit FIFO */
|
||||
void sdio_data_write(uint32_t data);
|
||||
/* read data(one word) from the receive FIFO */
|
||||
uint32_t sdio_data_read(void);
|
||||
/* get the number of remaining data bytes to be transferred to card */
|
||||
uint32_t sdio_data_counter_get(void);
|
||||
/* get the number of words remaining to be written or read from FIFO */
|
||||
uint32_t sdio_fifo_counter_get(void);
|
||||
/* enable the DMA request for SDIO */
|
||||
void sdio_dma_enable(void);
|
||||
/* disable the DMA request for SDIO */
|
||||
void sdio_dma_disable(void);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get the flags state of SDIO */
|
||||
FlagStatus sdio_flag_get(uint32_t flag);
|
||||
/* clear the pending flags of SDIO */
|
||||
void sdio_flag_clear(uint32_t flag);
|
||||
/* enable the SDIO interrupt */
|
||||
void sdio_interrupt_enable(uint32_t int_flag);
|
||||
/* disable the SDIO interrupt */
|
||||
void sdio_interrupt_disable(uint32_t int_flag);
|
||||
/* get the interrupt flags state of SDIO */
|
||||
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear the interrupt pending flags of SDIO */
|
||||
void sdio_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
/* SD I/O card functions */
|
||||
/* enable the read wait mode(SD I/O only) */
|
||||
void sdio_readwait_enable(void);
|
||||
/* disable the read wait mode(SD I/O only) */
|
||||
void sdio_readwait_disable(void);
|
||||
/* enable the function that stop the read wait process(SD I/O only) */
|
||||
void sdio_stop_readwait_enable(void);
|
||||
/* disable the function that stop the read wait process(SD I/O only) */
|
||||
void sdio_stop_readwait_disable(void);
|
||||
/* set the read wait type(SD I/O only) */
|
||||
void sdio_readwait_type_set(uint32_t readwait_type);
|
||||
/* enable the SD I/O mode specific operation(SD I/O only) */
|
||||
void sdio_operation_enable(void);
|
||||
/* disable the SD I/O mode specific operation(SD I/O only) */
|
||||
void sdio_operation_disable(void);
|
||||
/* enable the SD I/O suspend operation(SD I/O only) */
|
||||
void sdio_suspend_enable(void);
|
||||
/* disable the SD I/O suspend operation(SD I/O only) */
|
||||
void sdio_suspend_disable(void);
|
||||
|
||||
/* CE-ATA functions */
|
||||
/* enable the CE-ATA command(CE-ATA only) */
|
||||
void sdio_ceata_command_enable(void);
|
||||
/* disable the CE-ATA command(CE-ATA only) */
|
||||
void sdio_ceata_command_disable(void);
|
||||
/* enable the CE-ATA interrupt(CE-ATA only) */
|
||||
void sdio_ceata_interrupt_enable(void);
|
||||
/* disable the CE-ATA interrupt(CE-ATA only) */
|
||||
void sdio_ceata_interrupt_disable(void);
|
||||
/* enable the CE-ATA command completion signal(CE-ATA only) */
|
||||
void sdio_ceata_command_completion_enable(void);
|
||||
/* disable the CE-ATA command completion signal(CE-ATA only) */
|
||||
void sdio_ceata_command_completion_disable(void);
|
||||
|
||||
#endif /* GD32F10X_SDIO_H */
|
||||
@ -0,0 +1,324 @@
|
||||
/*!
|
||||
\file gd32f10x_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_SPI_H
|
||||
#define GD32F10X_SPI_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* SPIx(x=0,1,2) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
#define SPI2 (SPI_BASE + 0x00000400U)
|
||||
|
||||
/* registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2SPSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct {
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transfer type */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI NSS control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescaler factor */
|
||||
} spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI frame size */
|
||||
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
|
||||
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescaler factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
|
||||
/* function declarations */
|
||||
/* SPI deinitialization and initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI structure with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
||||
/* initialize SPI parameters */
|
||||
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* I2S initialization functions */
|
||||
/* initialize I2S parameters */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* DMA functions */
|
||||
/* enable SPI DMA send or receive */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
|
||||
/* disable SPI DMA send or receive */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
|
||||
|
||||
/* communication functions */
|
||||
/* configure SPI data frame format */
|
||||
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
|
||||
#endif /* GD32F10X_SPI_H */
|
||||
@ -0,0 +1,725 @@
|
||||
/*!
|
||||
\file gd32f10x_timer.h
|
||||
\brief definitions for the TIMER
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_TIMER_H
|
||||
#define GD32F10X_TIMER_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* TIMERx(x=0..13) definitions */
|
||||
#define TIMER0 (TIMER_BASE + 0x00012C00U)
|
||||
#define TIMER1 (TIMER_BASE + 0x00000000U)
|
||||
#define TIMER2 (TIMER_BASE + 0x00000400U)
|
||||
#define TIMER3 (TIMER_BASE + 0x00000800U)
|
||||
#define TIMER4 (TIMER_BASE + 0x00000C00U)
|
||||
#define TIMER5 (TIMER_BASE + 0x00001000U)
|
||||
#define TIMER6 (TIMER_BASE + 0x00001400U)
|
||||
#define TIMER7 (TIMER_BASE + 0x00013400U)
|
||||
#define TIMER8 (TIMER_BASE + 0x00014C00U)
|
||||
#define TIMER9 (TIMER_BASE + 0x00015000U)
|
||||
#define TIMER10 (TIMER_BASE + 0x00015400U)
|
||||
#define TIMER11 (TIMER_BASE + 0x00001800U)
|
||||
#define TIMER12 (TIMER_BASE + 0x00001C00U)
|
||||
#define TIMER13 (TIMER_BASE + 0x00002000U)
|
||||
|
||||
/* registers definitions */
|
||||
#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */
|
||||
#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */
|
||||
#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */
|
||||
#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */
|
||||
#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
|
||||
#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */
|
||||
#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */
|
||||
#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */
|
||||
#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */
|
||||
#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */
|
||||
#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */
|
||||
#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */
|
||||
#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */
|
||||
#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */
|
||||
#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */
|
||||
#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */
|
||||
#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */
|
||||
#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */
|
||||
#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */
|
||||
#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */
|
||||
|
||||
/* bits definitions */
|
||||
/* TIMER_CTL0 */
|
||||
#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */
|
||||
#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */
|
||||
#define TIMER_CTL0_UPS BIT(2) /*!< update source */
|
||||
#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
|
||||
#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */
|
||||
#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
|
||||
#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
|
||||
#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */
|
||||
|
||||
/* TIMER_CTL1 */
|
||||
#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */
|
||||
#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */
|
||||
#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */
|
||||
#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
|
||||
#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
|
||||
#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */
|
||||
#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */
|
||||
#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */
|
||||
#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */
|
||||
#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */
|
||||
#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */
|
||||
#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */
|
||||
|
||||
/* TIMER_SMCFG */
|
||||
#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
|
||||
#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */
|
||||
#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
|
||||
#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */
|
||||
#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */
|
||||
#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */
|
||||
#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */
|
||||
|
||||
/* TIMER_DMAINTEN */
|
||||
#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */
|
||||
#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */
|
||||
#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */
|
||||
#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */
|
||||
#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */
|
||||
#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */
|
||||
|
||||
/* TIMER_INTF */
|
||||
#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */
|
||||
#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */
|
||||
#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */
|
||||
#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */
|
||||
#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */
|
||||
#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */
|
||||
#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */
|
||||
#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */
|
||||
|
||||
/* TIMER_SWEVG */
|
||||
#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */
|
||||
#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */
|
||||
#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */
|
||||
#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */
|
||||
|
||||
/* TIMER_CHCTL0 */
|
||||
/* output compare mode */
|
||||
#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */
|
||||
#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */
|
||||
#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */
|
||||
#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */
|
||||
#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */
|
||||
#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */
|
||||
#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */
|
||||
#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */
|
||||
#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */
|
||||
#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */
|
||||
/* input capture mode */
|
||||
#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */
|
||||
#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */
|
||||
#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */
|
||||
#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */
|
||||
|
||||
/* TIMER_CHCTL1 */
|
||||
/* output compare mode */
|
||||
#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */
|
||||
#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */
|
||||
#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */
|
||||
#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */
|
||||
#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */
|
||||
#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */
|
||||
#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */
|
||||
#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */
|
||||
#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */
|
||||
#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */
|
||||
/* input capture mode */
|
||||
#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */
|
||||
#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */
|
||||
#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */
|
||||
#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */
|
||||
|
||||
/* TIMER_CHCTL2 */
|
||||
#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */
|
||||
#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */
|
||||
#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */
|
||||
#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */
|
||||
#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */
|
||||
#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */
|
||||
#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */
|
||||
|
||||
/* TIMER_CNT */
|
||||
#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */
|
||||
|
||||
/* TIMER_PSC */
|
||||
#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */
|
||||
|
||||
/* TIMER_CAR */
|
||||
#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */
|
||||
|
||||
/* TIMER_CREP */
|
||||
#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */
|
||||
|
||||
/* TIMER_CH0CV */
|
||||
#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */
|
||||
|
||||
/* TIMER_CH1CV */
|
||||
#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */
|
||||
|
||||
/* TIMER_CH2CV */
|
||||
#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */
|
||||
|
||||
/* TIMER_CH3CV */
|
||||
#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */
|
||||
|
||||
/* TIMER_CCHP */
|
||||
#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */
|
||||
#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */
|
||||
#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */
|
||||
#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */
|
||||
#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */
|
||||
#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */
|
||||
#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */
|
||||
#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */
|
||||
|
||||
/* TIMER_DMACFG */
|
||||
#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */
|
||||
#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */
|
||||
|
||||
/* TIMER_DMATB */
|
||||
#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */
|
||||
|
||||
/* constants definitions */
|
||||
/* TIMER init parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t prescaler; /*!< prescaler value */
|
||||
uint16_t alignedmode; /*!< aligned mode */
|
||||
uint16_t counterdirection; /*!< counter direction */
|
||||
uint32_t period; /*!< period value */
|
||||
uint16_t clockdivision; /*!< clock division value */
|
||||
uint8_t repetitioncounter; /*!< the counter repetition value */
|
||||
}timer_parameter_struct;
|
||||
|
||||
/* break parameter struct definitions*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t runoffstate; /*!< run mode off-state */
|
||||
uint16_t ideloffstate; /*!< idle mode off-state */
|
||||
uint16_t deadtime; /*!< dead time */
|
||||
uint16_t breakpolarity; /*!< break polarity */
|
||||
uint16_t outputautostate; /*!< output automatic enable */
|
||||
uint16_t protectmode; /*!< complementary register protect control */
|
||||
uint16_t breakstate; /*!< break enable */
|
||||
}timer_break_parameter_struct;
|
||||
|
||||
/* channel output parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t outputstate; /*!< channel output state */
|
||||
uint16_t outputnstate; /*!< channel complementary output state */
|
||||
uint16_t ocpolarity; /*!< channel output polarity */
|
||||
uint16_t ocnpolarity; /*!< channel complementary output polarity */
|
||||
uint16_t ocidlestate; /*!< idle state of channel output */
|
||||
uint16_t ocnidlestate; /*!< idle state of channel complementary output */
|
||||
}timer_oc_parameter_struct;
|
||||
|
||||
/* channel input parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t icpolarity; /*!< channel input polarity */
|
||||
uint16_t icselection; /*!< channel input mode selection */
|
||||
uint16_t icprescaler; /*!< channel input capture prescaler */
|
||||
uint16_t icfilter; /*!< channel input capture filter control */
|
||||
}timer_ic_parameter_struct;
|
||||
|
||||
/* TIMER interrupt enable or disable */
|
||||
#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */
|
||||
#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */
|
||||
#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */
|
||||
#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */
|
||||
#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */
|
||||
#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */
|
||||
#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */
|
||||
#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */
|
||||
|
||||
/* TIMER interrupt flag */
|
||||
#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */
|
||||
#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */
|
||||
#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */
|
||||
#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */
|
||||
#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */
|
||||
#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */
|
||||
#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */
|
||||
#define TIMER_INT_FLAG_BRK TIMER_INT_BRK
|
||||
|
||||
/* TIMER flag */
|
||||
#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */
|
||||
#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */
|
||||
#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */
|
||||
#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */
|
||||
#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */
|
||||
#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */
|
||||
#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */
|
||||
#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */
|
||||
#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */
|
||||
#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */
|
||||
#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */
|
||||
#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */
|
||||
/* TIMER DMA source enable */
|
||||
#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
|
||||
#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
|
||||
#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */
|
||||
#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */
|
||||
#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */
|
||||
#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */
|
||||
#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */
|
||||
|
||||
/* channel DMA request source selection */
|
||||
#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */
|
||||
#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */
|
||||
|
||||
/* DMA access base address */
|
||||
#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
|
||||
#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */
|
||||
#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */
|
||||
#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */
|
||||
#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */
|
||||
#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */
|
||||
#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */
|
||||
#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */
|
||||
#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */
|
||||
#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */
|
||||
#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */
|
||||
#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */
|
||||
#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */
|
||||
#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */
|
||||
#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */
|
||||
#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */
|
||||
#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */
|
||||
#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */
|
||||
#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */
|
||||
#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */
|
||||
|
||||
/* DMA access burst length */
|
||||
#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
|
||||
#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */
|
||||
#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */
|
||||
#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */
|
||||
#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */
|
||||
#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */
|
||||
#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */
|
||||
#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */
|
||||
#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */
|
||||
#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */
|
||||
#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */
|
||||
#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */
|
||||
#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */
|
||||
#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */
|
||||
#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */
|
||||
#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */
|
||||
#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */
|
||||
#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */
|
||||
#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */
|
||||
|
||||
/* TIMER software event generation source */
|
||||
#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */
|
||||
#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */
|
||||
#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */
|
||||
#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */
|
||||
|
||||
/* center-aligned mode selection */
|
||||
#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
|
||||
#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */
|
||||
#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */
|
||||
#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */
|
||||
#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */
|
||||
|
||||
/* TIMER prescaler reload mode */
|
||||
#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */
|
||||
#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */
|
||||
|
||||
/* count direction */
|
||||
#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */
|
||||
#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */
|
||||
|
||||
/* specify division ratio between TIMER clock and dead-time and sampling clock */
|
||||
#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
|
||||
#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */
|
||||
#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */
|
||||
#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
|
||||
|
||||
/* single pulse mode */
|
||||
#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */
|
||||
#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */
|
||||
|
||||
/* update source */
|
||||
#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */
|
||||
#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
|
||||
|
||||
/* run mode off-state configure */
|
||||
#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
|
||||
#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */
|
||||
|
||||
/* idle mode off-state configure */
|
||||
#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
|
||||
#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */
|
||||
|
||||
/* break input polarity */
|
||||
#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */
|
||||
#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */
|
||||
|
||||
/* output automatic enable */
|
||||
#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */
|
||||
#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */
|
||||
|
||||
/* complementary register protect control */
|
||||
#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
|
||||
#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */
|
||||
#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */
|
||||
#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */
|
||||
#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */
|
||||
|
||||
/* break input enable */
|
||||
#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */
|
||||
#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */
|
||||
|
||||
/* TIMER channel n(n=0,1,2,3) */
|
||||
#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */
|
||||
#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */
|
||||
#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */
|
||||
#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */
|
||||
|
||||
/* channel enable state */
|
||||
#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */
|
||||
#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */
|
||||
|
||||
/* channel complementary output enable state */
|
||||
#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */
|
||||
#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */
|
||||
|
||||
/* channel output polarity */
|
||||
#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */
|
||||
#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */
|
||||
|
||||
/* channel complementary output polarity */
|
||||
#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */
|
||||
#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */
|
||||
|
||||
/* idle state of channel output */
|
||||
#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */
|
||||
#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */
|
||||
|
||||
/* idle state of channel complementary output */
|
||||
#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */
|
||||
#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */
|
||||
|
||||
/* channel output compare mode */
|
||||
#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */
|
||||
#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */
|
||||
#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */
|
||||
#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */
|
||||
#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */
|
||||
#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */
|
||||
#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */
|
||||
#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/
|
||||
|
||||
/* channel output compare shadow enable */
|
||||
#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */
|
||||
#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */
|
||||
|
||||
/* channel output compare fast enable */
|
||||
#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */
|
||||
#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */
|
||||
|
||||
/* channel output compare clear enable */
|
||||
#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */
|
||||
#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */
|
||||
|
||||
/* channel control shadow register update control */
|
||||
#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */
|
||||
#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
|
||||
|
||||
/* channel input capture polarity */
|
||||
#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */
|
||||
#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */
|
||||
|
||||
/* timer input capture selection */
|
||||
#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */
|
||||
#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */
|
||||
#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */
|
||||
|
||||
/* channel input capture prescaler */
|
||||
#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */
|
||||
#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */
|
||||
#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */
|
||||
#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */
|
||||
|
||||
/* trigger selection */
|
||||
#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
|
||||
#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */
|
||||
#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */
|
||||
#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */
|
||||
#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */
|
||||
#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */
|
||||
#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */
|
||||
#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */
|
||||
#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */
|
||||
|
||||
/* master mode control */
|
||||
#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
|
||||
#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */
|
||||
#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */
|
||||
|
||||
/* slave mode control */
|
||||
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
|
||||
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
|
||||
#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */
|
||||
#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */
|
||||
#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */
|
||||
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
|
||||
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
|
||||
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
|
||||
#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */
|
||||
|
||||
/* master slave mode selection */
|
||||
#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */
|
||||
#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */
|
||||
|
||||
/* external trigger prescaler */
|
||||
#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
|
||||
#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */
|
||||
#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */
|
||||
#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */
|
||||
#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */
|
||||
|
||||
/* external trigger polarity */
|
||||
#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */
|
||||
#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */
|
||||
|
||||
/* channel 0 trigger input selection */
|
||||
#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */
|
||||
#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */
|
||||
|
||||
/* TIMERx(x=0..4,7..13) write CHxVAL register selection */
|
||||
#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */
|
||||
#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */
|
||||
|
||||
/* function declarations */
|
||||
/* TIMER timebase */
|
||||
/* deinit a TIMER */
|
||||
void timer_deinit(uint32_t timer_periph);
|
||||
/* initialize TIMER init parameter struct */
|
||||
void timer_struct_para_init(timer_parameter_struct* initpara);
|
||||
/* initialize TIMER counter */
|
||||
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
|
||||
/* enable a TIMER */
|
||||
void timer_enable(uint32_t timer_periph);
|
||||
/* disable a TIMER */
|
||||
void timer_disable(uint32_t timer_periph);
|
||||
/* enable the auto reload shadow function */
|
||||
void timer_auto_reload_shadow_enable(uint32_t timer_periph);
|
||||
/* disable the auto reload shadow function */
|
||||
void timer_auto_reload_shadow_disable(uint32_t timer_periph);
|
||||
/* enable the update event */
|
||||
void timer_update_event_enable(uint32_t timer_periph);
|
||||
/* disable the update event */
|
||||
void timer_update_event_disable(uint32_t timer_periph);
|
||||
/* set TIMER counter alignment mode */
|
||||
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
|
||||
/* set TIMER counter up direction */
|
||||
void timer_counter_up_direction(uint32_t timer_periph);
|
||||
/* set TIMER counter down direction */
|
||||
void timer_counter_down_direction(uint32_t timer_periph);
|
||||
/* configure TIMER prescaler */
|
||||
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload);
|
||||
/* configure TIMER repetition register value */
|
||||
void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition);
|
||||
/* configure TIMER autoreload register value */
|
||||
void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload);
|
||||
/* configure TIMER counter register value */
|
||||
void timer_counter_value_config(uint32_t timer_periph, uint32_t counter);
|
||||
/* read TIMER counter value */
|
||||
uint32_t timer_counter_read(uint32_t timer_periph);
|
||||
/* read TIMER prescaler value */
|
||||
uint16_t timer_prescaler_read(uint32_t timer_periph);
|
||||
/* configure TIMER single pulse mode */
|
||||
void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
|
||||
/* configure TIMER update source */
|
||||
void timer_update_source_config(uint32_t timer_periph, uint32_t update);
|
||||
|
||||
/* timer DMA and event */
|
||||
/* enable the TIMER DMA */
|
||||
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
|
||||
/* disable the TIMER DMA */
|
||||
void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
|
||||
/* channel DMA request source selection */
|
||||
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request);
|
||||
/* configure the TIMER DMA transfer */
|
||||
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
|
||||
/* software generate events */
|
||||
void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
|
||||
|
||||
/* TIMER channel complementary protection */
|
||||
/* initialize TIMER break parameter struct */
|
||||
void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
|
||||
/* configure TIMER break function */
|
||||
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
|
||||
/* enable TIMER break function */
|
||||
void timer_break_enable(uint32_t timer_periph);
|
||||
/* disable TIMER break function */
|
||||
void timer_break_disable(uint32_t timer_periph);
|
||||
/* enable TIMER output automatic function */
|
||||
void timer_automatic_output_enable(uint32_t timer_periph);
|
||||
/* disable TIMER output automatic function */
|
||||
void timer_automatic_output_disable(uint32_t timer_periph);
|
||||
/* enable or disable TIMER primary output function */
|
||||
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
|
||||
/* enable or disable channel capture/compare control shadow register */
|
||||
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
|
||||
/* configure TIMER channel control shadow register update control */
|
||||
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl);
|
||||
|
||||
/* TIMER channel output */
|
||||
/* initialize TIMER channel output parameter struct */
|
||||
void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
|
||||
/* configure TIMER channel output function */
|
||||
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
|
||||
/* configure TIMER channel output compare mode */
|
||||
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
|
||||
/* configure TIMER channel output pulse value */
|
||||
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint16_t pulse);
|
||||
/* configure TIMER channel output shadow function */
|
||||
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
|
||||
/* configure TIMER channel output fast function */
|
||||
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
|
||||
/* configure TIMER channel output clear function */
|
||||
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
|
||||
/* configure TIMER channel output polarity */
|
||||
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
|
||||
/* configure TIMER channel complementary output polarity */
|
||||
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
|
||||
/* configure TIMER channel enable state */
|
||||
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
|
||||
/* configure TIMER channel complementary output enable state */
|
||||
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
|
||||
|
||||
/* TIMER channel input */
|
||||
/* initialize TIMER channel input parameter struct */
|
||||
void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
|
||||
/* configure TIMER input capture parameter */
|
||||
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
|
||||
/* configure TIMER channel input capture prescaler value */
|
||||
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
|
||||
/* read TIMER channel capture compare register value */
|
||||
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
|
||||
/* configure TIMER input pwm capture function */
|
||||
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
|
||||
/* configure TIMER hall sensor mode */
|
||||
void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
|
||||
|
||||
/* TIMER master and slave */
|
||||
/* select TIMER input trigger source */
|
||||
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
|
||||
/* select TIMER master mode output trigger source */
|
||||
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
|
||||
/* select TIMER slave mode */
|
||||
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
|
||||
/* configure TIMER master slave mode */
|
||||
void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
|
||||
/* configure TIMER external trigger input */
|
||||
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
|
||||
/* configure TIMER quadrature decoder mode */
|
||||
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
|
||||
/* configure TIMER internal clock mode */
|
||||
void timer_internal_clock_config(uint32_t timer_periph);
|
||||
/* configure TIMER the internal trigger as external clock input */
|
||||
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
|
||||
/* configure TIMER the external trigger as external clock input */
|
||||
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint8_t extfilter);
|
||||
/* configure TIMER the external clock mode 0 */
|
||||
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
|
||||
/* configure TIMER the external clock mode 1 */
|
||||
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
|
||||
/* disable TIMER the external clock mode 1 */
|
||||
void timer_external_clock_mode1_disable(uint32_t timer_periph);
|
||||
|
||||
/* TIMER interrupt and flag */
|
||||
/* enable the TIMER interrupt */
|
||||
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* disable the TIMER interrupt */
|
||||
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* get TIMER interrupt flag */
|
||||
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* clear TIMER interrupt flag */
|
||||
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* get TIMER flag */
|
||||
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
|
||||
/* clear TIMER flag */
|
||||
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
|
||||
|
||||
#endif /* GD32E10X_TIMER_H */
|
||||
@ -0,0 +1,373 @@
|
||||
/*!
|
||||
\file gd32f10x_usart.h
|
||||
\brief definitions for the USART
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_USART_H
|
||||
#define GD32F10X_USART_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
|
||||
#define USART1 USART_BASE /*!< USART1 base address */
|
||||
#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */
|
||||
#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */
|
||||
#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */
|
||||
#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */
|
||||
#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */
|
||||
#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */
|
||||
#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */
|
||||
#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */
|
||||
#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */
|
||||
#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */
|
||||
|
||||
/* bits definitions */
|
||||
/* USARTx_STAT */
|
||||
#define USART_STAT_PERR BIT(0) /*!< parity error flag */
|
||||
#define USART_STAT_FERR BIT(1) /*!< frame error flag */
|
||||
#define USART_STAT_NERR BIT(2) /*!< noise error flag */
|
||||
#define USART_STAT_ORERR BIT(3) /*!< overrun error */
|
||||
#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */
|
||||
#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */
|
||||
#define USART_STAT_TC BIT(6) /*!< transmission complete */
|
||||
#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */
|
||||
#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
|
||||
#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
|
||||
|
||||
/* USARTx_DATA */
|
||||
#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */
|
||||
|
||||
/* USARTx_BAUD */
|
||||
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */
|
||||
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */
|
||||
|
||||
/* USARTx_CTL0 */
|
||||
#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
|
||||
#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
|
||||
#define USART_CTL0_REN BIT(2) /*!< enable receiver */
|
||||
#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */
|
||||
#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */
|
||||
#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */
|
||||
#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */
|
||||
#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */
|
||||
#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */
|
||||
#define USART_CTL0_PM BIT(9) /*!< parity mode */
|
||||
#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */
|
||||
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
|
||||
#define USART_CTL0_WL BIT(12) /*!< word length */
|
||||
#define USART_CTL0_UEN BIT(13) /*!< enable USART */
|
||||
|
||||
/* USARTx_CTL1 */
|
||||
#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
|
||||
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
|
||||
#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */
|
||||
#define USART_CTL1_CLEN BIT(8) /*!< CK length */
|
||||
#define USART_CTL1_CPH BIT(9) /*!< CK phase */
|
||||
#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
|
||||
#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */
|
||||
#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
|
||||
#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */
|
||||
|
||||
/* USARTx_CTL2 */
|
||||
#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */
|
||||
#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */
|
||||
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
|
||||
#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
|
||||
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
|
||||
#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */
|
||||
#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */
|
||||
#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */
|
||||
#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */
|
||||
#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */
|
||||
#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */
|
||||
|
||||
/* USARTx_GP */
|
||||
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
|
||||
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the USART bit position and its register index offset */
|
||||
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6)))
|
||||
#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU))
|
||||
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
|
||||
#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */
|
||||
#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */
|
||||
#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */
|
||||
#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */
|
||||
|
||||
/* USART flags */
|
||||
typedef enum
|
||||
{
|
||||
/* flags in STAT register */
|
||||
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
|
||||
USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
|
||||
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
|
||||
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
|
||||
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
|
||||
USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
|
||||
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
|
||||
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
|
||||
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
|
||||
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
|
||||
}usart_flag_enum;
|
||||
|
||||
/* USART interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in CTL0 register */
|
||||
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
|
||||
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
|
||||
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
|
||||
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
|
||||
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
|
||||
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
|
||||
/* interrupt flags in CTL1 register */
|
||||
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
|
||||
/* interrupt flags in CTL2 register */
|
||||
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
|
||||
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
|
||||
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
|
||||
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
|
||||
}usart_interrupt_flag_enum;
|
||||
|
||||
/* USART interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt in CTL0 register */
|
||||
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
|
||||
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
|
||||
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
|
||||
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
|
||||
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
|
||||
/* interrupt in CTL1 register */
|
||||
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
|
||||
/* interrupt in CTL2 register */
|
||||
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
|
||||
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
|
||||
}usart_interrupt_enum;
|
||||
|
||||
/* configure USART receiver */
|
||||
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
|
||||
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
|
||||
|
||||
/* configure USART transmitter */
|
||||
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
|
||||
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
|
||||
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
|
||||
|
||||
/* USART parity bits definitions */
|
||||
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
|
||||
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
|
||||
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
|
||||
|
||||
/* USART wakeup method in mute mode */
|
||||
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||
#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
|
||||
#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
|
||||
|
||||
/* USART word length definitions */
|
||||
#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
|
||||
#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
|
||||
#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
|
||||
|
||||
/* USART stop bits definitions */
|
||||
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
|
||||
#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
|
||||
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
|
||||
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
|
||||
|
||||
/* USART LIN break frame length */
|
||||
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
|
||||
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */
|
||||
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */
|
||||
|
||||
/* USART CK length */
|
||||
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
|
||||
#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
|
||||
|
||||
/* USART clock phase */
|
||||
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
|
||||
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
|
||||
|
||||
/* USART clock polarity */
|
||||
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
|
||||
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
|
||||
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
|
||||
|
||||
/* configure USART DMA */
|
||||
#define CLT2_RECEIVE_DMAEN(regval) (BIT(6) & ((uint32_t)(regval) << 6))
|
||||
#define CTL2_TRANSMIT_DMAEN(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||
#define USART_RECEIVE_DMA_ENABLE CLT2_RECEIVE_DMAEN(1) /* enable DMA request for reception */
|
||||
#define USART_RECEIVE_DMA_DISABLE CLT2_RECEIVE_DMAEN(0) /* disable DMA request for reception */
|
||||
#define USART_TRANSMIT_DMA_ENABLE CTL2_TRANSMIT_DMAEN(1) /* enable DMA request for transmission */
|
||||
#define USART_TRANSMIT_DMA_DISABLE CTL2_TRANSMIT_DMAEN(0) /* disable DMA request for transmission */
|
||||
|
||||
/* configure USART RTS */
|
||||
#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||
#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */
|
||||
#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */
|
||||
|
||||
/* configure USART CTS */
|
||||
#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||
#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */
|
||||
#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */
|
||||
|
||||
/* enable USART IrDA low-power */
|
||||
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
|
||||
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset USART */
|
||||
void usart_deinit(uint32_t usart_periph);
|
||||
/* configure USART baud rate value */
|
||||
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
|
||||
/* configure USART parity function */
|
||||
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
|
||||
/* configure USART word length */
|
||||
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
|
||||
/* configure USART stop bit length */
|
||||
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
|
||||
|
||||
/* USART normal mode communication */
|
||||
/* enable USART */
|
||||
void usart_enable(uint32_t usart_periph);
|
||||
/* disable USART */
|
||||
void usart_disable(uint32_t usart_periph);
|
||||
/* configure USART transmitter */
|
||||
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
|
||||
/* configure USART receiver */
|
||||
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
|
||||
/* USART transmit data function */
|
||||
void usart_data_transmit(uint32_t usart_periph, uint16_t data);
|
||||
/* USART receive data function */
|
||||
uint16_t usart_data_receive(uint32_t usart_periph);
|
||||
|
||||
/* multi-processor communication */
|
||||
/* configure address of the USART */
|
||||
void usart_address_config(uint32_t usart_periph, uint8_t addr);
|
||||
/* enable mute mode */
|
||||
void usart_mute_mode_enable(uint32_t usart_periph);
|
||||
/* disable mute mode */
|
||||
void usart_mute_mode_disable(uint32_t usart_periph);
|
||||
/* configure wakeup method in mute mode */
|
||||
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
|
||||
|
||||
/* LIN mode communication */
|
||||
/* enable LIN mode */
|
||||
void usart_lin_mode_enable(uint32_t usart_periph);
|
||||
/* disable LIN mode */
|
||||
void usart_lin_mode_disable(uint32_t usart_periph);
|
||||
/* configure LIN break frame length */
|
||||
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
|
||||
/* send break frame */
|
||||
void usart_send_break(uint32_t usart_periph);
|
||||
|
||||
/* half-duplex communication */
|
||||
/* enable half-duplex */
|
||||
void usart_halfduplex_enable(uint32_t usart_periph);
|
||||
/* disable half-duplex */
|
||||
void usart_halfduplex_disable(uint32_t usart_periph);
|
||||
|
||||
/* synchronous communication */
|
||||
/* enable CK pin in synchronous mode */
|
||||
void usart_synchronous_clock_enable(uint32_t usart_periph);
|
||||
/* disable CK pin in synchronous mode */
|
||||
void usart_synchronous_clock_disable(uint32_t usart_periph);
|
||||
/* configure usart synchronous mode parameters */
|
||||
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
|
||||
|
||||
/* smartcard communication */
|
||||
/* configure guard time value in smartcard mode */
|
||||
void usart_guard_time_config(uint32_t usart_periph,uint8_t gaut);
|
||||
/* enable smartcard mode */
|
||||
void usart_smartcard_mode_enable(uint32_t usart_periph);
|
||||
/* disable smartcard mode */
|
||||
void usart_smartcard_mode_disable(uint32_t usart_periph);
|
||||
/* enable NACK in smartcard mode */
|
||||
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
|
||||
/* disable NACK in smartcard mode */
|
||||
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
|
||||
|
||||
/* IrDA communication */
|
||||
/* enable IrDA mode */
|
||||
void usart_irda_mode_enable(uint32_t usart_periph);
|
||||
/* disable IrDA mode */
|
||||
void usart_irda_mode_disable(uint32_t usart_periph);
|
||||
/* configure the peripheral clock prescaler */
|
||||
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
|
||||
/* configure IrDA low-power */
|
||||
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
|
||||
|
||||
/* hardware flow communication */
|
||||
/* configure hardware flow control RTS */
|
||||
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
|
||||
/* configure hardware flow control CTS */
|
||||
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
|
||||
|
||||
/* DMA communication */
|
||||
/* configure USART DMA for reception */
|
||||
void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig);
|
||||
/* configure USART DMA for transmission */
|
||||
void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag in STAT register */
|
||||
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
|
||||
/* clear flag in STAT register */
|
||||
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
|
||||
|
||||
/* interrupt functions */
|
||||
/* enable USART interrupt */
|
||||
void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt);
|
||||
/* disable USART interrupt */
|
||||
void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt);
|
||||
/* get USART interrupt and flag status */
|
||||
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
|
||||
/* clear interrupt flag in STAT register */
|
||||
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag);
|
||||
#endif /* GD32F10X_USART_H */
|
||||
@ -0,0 +1,91 @@
|
||||
/*!
|
||||
\file gd32f10x_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F10X_WWDGT_H
|
||||
#define GD32F10X_WWDGT_H
|
||||
|
||||
#include "gd32f10x.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/* write value to WWDGT_CTL_CNT bit field */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
/* write value to WWDGT_CFG_WIN bit field */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
|
||||
#endif /* GD32F10X_WWDGT_H */
|
||||
@ -0,0 +1,929 @@
|
||||
/*!
|
||||
\file gd32f10x_adc.c
|
||||
\brief ADC driver
|
||||
|
||||
\version 2024-01-05, V2.3.0, firmware for GD32F10x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2024, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f10x_adc.h"
|
||||
|
||||
/* discontinuous mode macro*/
|
||||
#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
|
||||
|
||||
/* ADC regular channel macro */
|
||||
#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U)
|
||||
#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U)
|
||||
#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
|
||||
#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U)
|
||||
|
||||
/* ADC sampling time macro */
|
||||
#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
|
||||
#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U)
|
||||
#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U)
|
||||
|
||||
/* ADC inserted channel macro */
|
||||
#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U)
|
||||
#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U)
|
||||
|
||||
/* ADC inserted channel offset macro */
|
||||
#define ADC_OFFSET_LENGTH ((uint8_t)3U)
|
||||
#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U)
|
||||
|
||||
/*!
|
||||
\brief reset ADC
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_deinit(uint32_t adc_periph)
|
||||
{
|
||||
switch(adc_periph){
|
||||
case ADC0:
|
||||
/* reset ADC0 */
|
||||
rcu_periph_reset_enable(RCU_ADC0RST);
|
||||
rcu_periph_reset_disable(RCU_ADC0RST);
|
||||
break;
|
||||
case ADC1:
|
||||
/* reset ADC1 */
|
||||
rcu_periph_reset_enable(RCU_ADC1RST);
|
||||
rcu_periph_reset_disable(RCU_ADC1RST);
|
||||
break;
|
||||
#ifndef GD32F10X_CL
|
||||
case ADC2:
|
||||
rcu_periph_reset_enable(RCU_ADC2RST);
|
||||
rcu_periph_reset_disable(RCU_ADC2RST);
|
||||
break;
|
||||
#endif /* GD32F10X_CL */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the ADC sync mode
|
||||
\param[in] mode: ADC mode
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_MODE_FREE: all the ADCs work independently
|
||||
\arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
|
||||
\arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
|
||||
\arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
|
||||
\arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
|
||||
\arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
|
||||
\arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
|
||||
\arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
|
||||
\arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
|
||||
\arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_mode_config(uint32_t mode)
|
||||
{
|
||||
ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
|
||||
ADC_CTL0(ADC0) |= mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable or disable ADC special function
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] function: the function to config
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_SCAN_MODE: scan mode select
|
||||
\arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
|
||||
\arg ADC_CONTINUOUS_MODE: continuous mode select
|
||||
\param[in] newvalue: ENABLE or DISABLE
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
|
||||
{
|
||||
if(newvalue){
|
||||
if(0U != (function & ADC_SCAN_MODE)){
|
||||
/* enable scan mode */
|
||||
ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
|
||||
}
|
||||
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
|
||||
/* enable inserted channel group convert automatically */
|
||||
ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
|
||||
}
|
||||
if(0U != (function & ADC_CONTINUOUS_MODE)){
|
||||
/* enable continuous mode */
|
||||
ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
|
||||
}
|
||||
}else{
|
||||
if(0U != (function & ADC_SCAN_MODE)){
|
||||
/* disable scan mode */
|
||||
ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
|
||||
}
|
||||
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
|
||||
/* disable inserted channel group convert automatically */
|
||||
ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
|
||||
}
|
||||
if(0U != (function & ADC_CONTINUOUS_MODE)){
|
||||
/* disable continuous mode */
|
||||
ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC data alignment
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] data_alignment: data alignment select
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_DATAALIGN_RIGHT: LSB alignment
|
||||
\arg ADC_DATAALIGN_LEFT: MSB alignment
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
|
||||
{
|
||||
if(ADC_DATAALIGN_RIGHT != data_alignment){
|
||||
/* MSB alignment */
|
||||
ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
|
||||
}else{
|
||||
/* LSB alignment */
|
||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable ADC interface
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_enable(uint32_t adc_periph)
|
||||
{
|
||||
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
|
||||
/* enable ADC */
|
||||
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable ADC interface
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_disable(uint32_t adc_periph)
|
||||
{
|
||||
/* disable ADC */
|
||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief ADC calibration and reset calibration(GD32F10x_MD series without this function)
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_calibration_enable(uint32_t adc_periph)
|
||||
{
|
||||
/* reset the selected ADC1 calibration registers */
|
||||
ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
|
||||
/* check the RSTCLB bit state */
|
||||
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
|
||||
}
|
||||
/* enable ADC calibration process */
|
||||
ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
|
||||
/* check the CLB bit state */
|
||||
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the temperature sensor and Vrefint channel
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_tempsensor_vrefint_enable(void)
|
||||
{
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the temperature sensor and Vrefint channel
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_tempsensor_vrefint_disable(void)
|
||||
{
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DMA request
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_dma_mode_enable(uint32_t adc_periph)
|
||||
{
|
||||
/* enable DMA request */
|
||||
ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DMA request
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_dma_mode_disable(uint32_t adc_periph)
|
||||
{
|
||||
/* disable DMA request */
|
||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC discontinuous mode
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel_group: select the channel group
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
||||
\arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
|
||||
\param[in] length: number of conversions in discontinuous mode,the number can be 1..8
|
||||
for regular channel, the number has no effect for inserted channel
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
|
||||
{
|
||||
/* disable discontinuous mode of regular & inserted channel */
|
||||
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
|
||||
switch(adc_channel_group){
|
||||
case ADC_REGULAR_CHANNEL:
|
||||
/* config the number of conversions in discontinuous mode */
|
||||
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
|
||||
ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
||||
/* enable regular channel group discontinuous mode */
|
||||
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL:
|
||||
/* enable inserted channel group discontinuous mode */
|
||||
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
|
||||
break;
|
||||
case ADC_CHANNEL_DISCON_DISABLE:
|
||||
/* disable discontinuous mode of regular & inserted channel */
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the length of regular channel group or inserted channel group
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel_group: select the channel group
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
||||
\param[in] length: the length of the channel
|
||||
regular channel 1-16
|
||||
inserted channel 1-4
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
|
||||
{
|
||||
switch(adc_channel_group){
|
||||
case ADC_REGULAR_CHANNEL:
|
||||
/* configure the length of regular channel group */
|
||||
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
|
||||
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL:
|
||||
/* configure the length of inserted channel group */
|
||||
ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
|
||||
ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC regular channel
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
|
||||
\param[in] adc_channel: the selected ADC channel
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
|
||||
\param[in] sample_time: the sample time value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
|
||||
\arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
|
||||
\arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
|
||||
\arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
|
||||
\arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
|
||||
\arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
|
||||
\arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
|
||||
\arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
|
||||
{
|
||||
uint32_t rsq,sampt;
|
||||
|
||||
/* ADC regular sequence config */
|
||||
if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
|
||||
/* the regular group sequence rank is smaller than six */
|
||||
rsq = ADC_RSQ2(adc_periph);
|
||||
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
|
||||
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
|
||||
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
|
||||
ADC_RSQ2(adc_periph) = rsq;
|
||||
}else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
|
||||
/* the regular group sequence rank is smaller than twelve */
|
||||
rsq = ADC_RSQ1(adc_periph);
|
||||
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
|
||||
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
|
||||
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
|
||||
ADC_RSQ1(adc_periph) = rsq;
|
||||
}else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
|
||||
/* the regular group sequence rank is smaller than sixteen */
|
||||
rsq = ADC_RSQ0(adc_periph);
|
||||
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
|
||||
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
|
||||
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
|
||||
ADC_RSQ0(adc_periph) = rsq;
|
||||
}else{
|
||||
}
|
||||
|
||||
/* ADC sampling time config */
|
||||
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
|
||||
/* the regular group sequence rank is smaller than ten */
|
||||
sampt = ADC_SAMPT1(adc_periph);
|
||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
|
||||
/* channel sample time set*/
|
||||
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
|
||||
ADC_SAMPT1(adc_periph) = sampt;
|
||||
}else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
|
||||
/* the regular group sequence rank is smaller than eighteen */
|
||||
sampt = ADC_SAMPT0(adc_periph);
|
||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
|
||||
/* channel sample time set*/
|
||||
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
|
||||
ADC_SAMPT0(adc_periph) = sampt;
|
||||
}else{
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC inserted channel
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
|
||||
\param[in] adc_channel: the selected ADC channel
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
|
||||
\param[in] sample_time: The sample time value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
|
||||
\arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
|
||||
\arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
|
||||
\arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
|
||||
\arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
|
||||
\arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
|
||||
\arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
|
||||
\arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
|
||||
{
|
||||
uint8_t inserted_length;
|
||||
uint32_t isq,sampt;
|
||||
/* get inserted channel group length */
|
||||
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
|
||||
/* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
|
||||
isq = ADC_ISQ(adc_periph);
|
||||
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)));
|
||||
isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH));
|
||||
ADC_ISQ(adc_periph) = isq;
|
||||
|
||||
/* ADC sampling time config */
|
||||
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
|
||||
/* the inserted group sequence rank is smaller than ten */
|
||||
sampt = ADC_SAMPT1(adc_periph);
|
||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
|
||||
/* channel sample time set*/
|
||||
sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
|
||||
ADC_SAMPT1(adc_periph) = sampt;
|
||||
}else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
|
||||
/* the inserted group sequence rank is smaller than eighteen */
|
||||
sampt = ADC_SAMPT0(adc_periph);
|
||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
|
||||
/* channel sample time set*/
|
||||
sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
|
||||
ADC_SAMPT0(adc_periph) = sampt;
|
||||
}else{
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC inserted channel offset
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] inserted_channel: insert channel select
|
||||
only one parameter can be selected
|
||||
\arg ADC_INSERTED_CHANNEL_0: inserted channel0
|
||||
\arg ADC_INSERTED_CHANNEL_1: inserted channel1
|
||||
\arg ADC_INSERTED_CHANNEL_2: inserted channel2
|
||||
\arg ADC_INSERTED_CHANNEL_3: inserted channel3
|
||||
\param[in] offset: the offset data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
|
||||
{
|
||||
uint8_t inserted_length;
|
||||
uint32_t num = 0U;
|
||||
|
||||
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
|
||||
num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
|
||||
|
||||
if(num <= ADC_OFFSET_LENGTH){
|
||||
/* calculate the offset of the register */
|
||||
num = num * ADC_OFFSET_SHIFT_LENGTH;
|
||||
/* config the offset of the selected channels */
|
||||
REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC external trigger source
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel_group: select the channel group
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
||||
\param[in] external_trigger_source: regular or inserted group trigger source
|
||||
only one parameter can be selected
|
||||
for regular channel:
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select
|
||||
\arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
|
||||
\arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select
|
||||
\arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select
|
||||
\arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
|
||||
\arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select
|
||||
\arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select
|
||||
\arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select
|
||||
\arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select
|
||||
\arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger
|
||||
for inserted channel:
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
|
||||
\arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select
|
||||
\arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select
|
||||
\arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
|
||||
{
|
||||
switch(adc_channel_group){
|
||||
case ADC_REGULAR_CHANNEL:
|
||||
/* configure ADC regular group external trigger source */
|
||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
|
||||
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL:
|
||||
/* configure ADC inserted group external trigger source */
|
||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
|
||||
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC external trigger
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel_group: select the channel group
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
||||
\param[in] newvalue: ENABLE or DISABLE
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
|
||||
{
|
||||
if(newvalue){
|
||||
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
|
||||
/* enable ADC regular channel group external trigger */
|
||||
ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
|
||||
}
|
||||
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
|
||||
/* enable ADC inserted channel group external trigger */
|
||||
ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
|
||||
}
|
||||
}else{
|
||||
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
|
||||
/* disable ADC regular channel group external trigger */
|
||||
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
|
||||
}
|
||||
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
|
||||
/* disable ADC regular channel group external trigger */
|
||||
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable ADC software trigger
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel_group: select the channel group
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
|
||||
{
|
||||
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
|
||||
/* enable ADC regular channel group software trigger */
|
||||
ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
|
||||
}
|
||||
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
|
||||
/* enable ADC inserted channel group software trigger */
|
||||
ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read ADC regular group data register
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the conversion value
|
||||
*/
|
||||
uint16_t adc_regular_data_read(uint32_t adc_periph)
|
||||
{
|
||||
return (uint16_t)(ADC_RDATA(adc_periph));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read ADC inserted group data register
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] inserted_channel: insert channel select
|
||||
only one parameter can be selected
|
||||
\arg ADC_INSERTED_CHANNEL_0: inserted Channel0
|
||||
\arg ADC_INSERTED_CHANNEL_1: inserted channel1
|
||||
\arg ADC_INSERTED_CHANNEL_2: inserted Channel2
|
||||
\arg ADC_INSERTED_CHANNEL_3: inserted Channel3
|
||||
\param[out] none
|
||||
\retval the conversion value
|
||||
*/
|
||||
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
|
||||
{
|
||||
uint32_t idata;
|
||||
/* read the data of the selected channel */
|
||||
switch(inserted_channel){
|
||||
case ADC_INSERTED_CHANNEL_0:
|
||||
/* read the data of channel 0 */
|
||||
idata = ADC_IDATA0(adc_periph);
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL_1:
|
||||
/* read the data of channel 1 */
|
||||
idata = ADC_IDATA1(adc_periph);
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL_2:
|
||||
/* read the data of channel 2 */
|
||||
idata = ADC_IDATA2(adc_periph);
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL_3:
|
||||
/* read the data of channel 3 */
|
||||
idata = ADC_IDATA3(adc_periph);
|
||||
break;
|
||||
default:
|
||||
idata = 0U;
|
||||
break;
|
||||
}
|
||||
return (uint16_t)idata;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the last ADC0 and ADC1 conversion result data in sync mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the conversion value
|
||||
*/
|
||||
uint32_t adc_sync_mode_convert_value_read(void)
|
||||
{
|
||||
/* return conversion value */
|
||||
return ADC_RDATA(ADC0);
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief configure ADC analog watchdog single channel
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel: the selected ADC channel
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
|
||||
{
|
||||
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
|
||||
/* analog watchdog channel select */
|
||||
ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
|
||||
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC analog watchdog group channel
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_channel_group: the channel group use analog watchdog
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
||||
\arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
|
||||
{
|
||||
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
|
||||
/* select the group */
|
||||
switch(adc_channel_group){
|
||||
case ADC_REGULAR_CHANNEL:
|
||||
/* regular channel analog watchdog enable */
|
||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
|
||||
break;
|
||||
case ADC_INSERTED_CHANNEL:
|
||||
/* inserted channel analog watchdog enable */
|
||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
|
||||
break;
|
||||
case ADC_REGULAR_INSERTED_CHANNEL:
|
||||
/* regular and inserted channel analog watchdog enable */
|
||||
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable ADC analog watchdog
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_watchdog_disable(uint32_t adc_periph)
|
||||
{
|
||||
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure ADC analog watchdog threshold
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] low_threshold: analog watchdog low threshold, 0..4095
|
||||
\param[in] high_threshold: analog watchdog high threshold, 0..4095
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
|
||||
{
|
||||
ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
|
||||
ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get the ADC flag bits
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_flag: the adc flag bits
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_FLAG_WDE: analog watchdog event flag
|
||||
\arg ADC_FLAG_EOC: end of group conversion flag
|
||||
\arg ADC_FLAG_EOIC: end of inserted group conversion flag
|
||||
\arg ADC_FLAG_STIC: start flag of inserted channel group
|
||||
\arg ADC_FLAG_STRC: start flag of regular channel group
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
|
||||
{
|
||||
FlagStatus reval = RESET;
|
||||
if(ADC_STAT(adc_periph) & adc_flag){
|
||||
reval = SET;
|
||||
}
|
||||
return reval;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear the ADC flag bits
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_flag: the adc flag bits
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg ADC_FLAG_WDE: analog watchdog event flag
|
||||
\arg ADC_FLAG_EOC: end of group conversion flag
|
||||
\arg ADC_FLAG_EOIC: end of inserted group conversion flag
|
||||
\arg ADC_FLAG_STIC: start flag of inserted channel group
|
||||
\arg ADC_FLAG_STRC: start flag of regular channel group
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
|
||||
{
|
||||
ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get the bit state of ADCx software start conversion
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
|
||||
{
|
||||
FlagStatus reval = RESET;
|
||||
if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
|
||||
reval = SET;
|
||||
}
|
||||
return reval;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get the bit state of ADCx software inserted channel start conversion
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
|
||||
{
|
||||
FlagStatus reval = RESET;
|
||||
if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
|
||||
reval = SET;
|
||||
}
|
||||
return reval;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get the ADC interrupt bits
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_interrupt: the adc interrupt bits
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
|
||||
\arg ADC_INT_FLAG_EOC: end of group conversion interrupt
|
||||
\arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
|
||||
{
|
||||
FlagStatus interrupt_flag = RESET;
|
||||
uint32_t state;
|
||||
/* check the interrupt bits */
|
||||
switch(adc_interrupt){
|
||||
case ADC_INT_FLAG_WDE:
|
||||
/* get the ADC analog watchdog interrupt bits */
|
||||
state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
|
||||
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
|
||||
interrupt_flag = SET;
|
||||
}
|
||||
break;
|
||||
case ADC_INT_FLAG_EOC:
|
||||
/* get the ADC end of group conversion interrupt bits */
|
||||
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
|
||||
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
|
||||
interrupt_flag = SET;
|
||||
}
|
||||
break;
|
||||
case ADC_INT_FLAG_EOIC:
|
||||
/* get the ADC end of inserted group conversion interrupt bits */
|
||||
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
|
||||
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
|
||||
interrupt_flag = SET;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return interrupt_flag;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear the ADC flag
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_interrupt: the adc status flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
|
||||
\arg ADC_INT_FLAG_EOC: end of group conversion interrupt
|
||||
\arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
|
||||
{
|
||||
ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable ADC interrupt
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_interrupt: the adc interrupt
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg ADC_INT_WDE: analog watchdog interrupt flag
|
||||
\arg ADC_INT_EOC: end of group conversion interrupt flag
|
||||
\arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
|
||||
{
|
||||
/* enable ADC analog watchdog interrupt */
|
||||
if(0U != (adc_interrupt & ADC_INT_WDE)){
|
||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
|
||||
}
|
||||
/* enable ADC end of group conversion interrupt */
|
||||
if(0U != (adc_interrupt & ADC_INT_EOC)){
|
||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
|
||||
}
|
||||
/* enable ADC end of inserted group conversion interrupt */
|
||||
if(0U != (adc_interrupt & ADC_INT_EOIC)){
|
||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable ADC interrupt
|
||||
\param[in] adc_periph: ADCx, x=0,1,2
|
||||
\param[in] adc_interrupt: the adc interrupt flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg ADC_INT_WDE: analog watchdog interrupt flag
|
||||
\arg ADC_INT_EOC: end of group conversion interrupt flag
|
||||
\arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
|
||||
{
|
||||
/* disable ADC analog watchdog interrupt */
|
||||
if(0U != (adc_interrupt & ADC_INT_WDE)){
|
||||
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
|
||||
}
|
||||
/* disable ADC end of group conversion interrupt */
|
||||
if(0U != (adc_interrupt & ADC_INT_EOC)){
|
||||
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
|
||||
}
|
||||
/* disable ADC end of inserted group conversion interrupt */
|
||||
if(0U != (adc_interrupt & ADC_INT_EOIC)){
|
||||
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
|
||||
}
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user