diff --git a/boot_project/DebugConfig/hongri_boot_STM32_STM32F105RC.dbgconf b/boot_project/DebugConfig/hongri_boot_STM32_STM32F105RC.dbgconf
new file mode 100644
index 0000000..90dabd8
--- /dev/null
+++ b/boot_project/DebugConfig/hongri_boot_STM32_STM32F105RC.dbgconf
@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// Debug MCU Configuration
+// DBG_SLEEP
+// Debug Sleep Mode
+// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+// DBG_STOP
+// Debug Stop Mode
+// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+// DBG_STANDBY
+// Debug Standby Mode
+// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+// DBG_IWDG_STOP
+// Debug independent watchdog stopped when core is halted
+// 0: The watchdog counter clock continues even if the core is halted
+// 1: The watchdog counter clock is stopped when the core is halted
+// DBG_WWDG_STOP
+// Debug window watchdog stopped when core is halted
+// 0: The window watchdog counter clock continues even if the core is halted
+// 1: The window watchdog counter clock is stopped when the core is halted
+// DBG_TIM1_STOP
+// Timer 1 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_TIM2_STOP
+// Timer 2 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_TIM3_STOP
+// Timer 3 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_TIM4_STOP
+// Timer 4 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_CAN1_STOP
+// Debug CAN1 stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: CAN1 receive registers are frozen
+// DBG_I2C1_SMBUS_TIMEOUT
+// I2C1 SMBUS timeout mode stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: The SMBUS timeout is frozen
+// DBG_I2C2_SMBUS_TIMEOUT
+// I2C2 SMBUS timeout mode stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: The SMBUS timeout is frozen
+// DBG_TIM8_STOP
+// Timer 8 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM5_STOP
+// Timer 5 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM6_STOP
+// Timer 6 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM7_STOP
+// Timer 7 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_CAN2_STOP
+// Debug CAN2 stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: CAN2 receive registers are frozen
+// DBG_TIM12_STOP
+// Timer 12 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM13_STOP
+// Timer 13 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM14_STOP
+// Timer 14 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM9_STOP
+// Timer 9 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM10_STOP
+// Timer 10 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM11_STOP
+// Timer 11 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/boot_project/DebugConfig/hongri_boot_STM_STM32F105RC.dbgconf b/boot_project/DebugConfig/hongri_boot_STM_STM32F105RC.dbgconf
new file mode 100644
index 0000000..90dabd8
--- /dev/null
+++ b/boot_project/DebugConfig/hongri_boot_STM_STM32F105RC.dbgconf
@@ -0,0 +1,97 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+// Debug MCU Configuration
+// DBG_SLEEP
+// Debug Sleep Mode
+// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
+// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
+// DBG_STOP
+// Debug Stop Mode
+// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
+// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
+// DBG_STANDBY
+// Debug Standby Mode
+// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+// DBG_IWDG_STOP
+// Debug independent watchdog stopped when core is halted
+// 0: The watchdog counter clock continues even if the core is halted
+// 1: The watchdog counter clock is stopped when the core is halted
+// DBG_WWDG_STOP
+// Debug window watchdog stopped when core is halted
+// 0: The window watchdog counter clock continues even if the core is halted
+// 1: The window watchdog counter clock is stopped when the core is halted
+// DBG_TIM1_STOP
+// Timer 1 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_TIM2_STOP
+// Timer 2 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_TIM3_STOP
+// Timer 3 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_TIM4_STOP
+// Timer 4 counter stopped when core is halted
+// 0: The clock of the involved Timer Counter is fed even if the core is halted
+// 1: The clock of the involved Timer counter is stopped when the core is halted
+// DBG_CAN1_STOP
+// Debug CAN1 stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: CAN1 receive registers are frozen
+// DBG_I2C1_SMBUS_TIMEOUT
+// I2C1 SMBUS timeout mode stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: The SMBUS timeout is frozen
+// DBG_I2C2_SMBUS_TIMEOUT
+// I2C2 SMBUS timeout mode stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: The SMBUS timeout is frozen
+// DBG_TIM8_STOP
+// Timer 8 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM5_STOP
+// Timer 5 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM6_STOP
+// Timer 6 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM7_STOP
+// Timer 7 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_CAN2_STOP
+// Debug CAN2 stopped when Core is halted
+// 0: Same behavior as in normal mode
+// 1: CAN2 receive registers are frozen
+// DBG_TIM12_STOP
+// Timer 12 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM13_STOP
+// Timer 13 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM14_STOP
+// Timer 14 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM9_STOP
+// Timer 9 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM10_STOP
+// Timer 10 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+// DBG_TIM11_STOP
+// Timer 11 counter stopped when core is halted
+// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
+// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
+//
+DbgMCU_CR = 0x00000007;
+// <<< end of configuration section >>>
\ No newline at end of file
diff --git a/boot_project/LED.map b/boot_project/LED.map
new file mode 100644
index 0000000..6722ac0
Binary files /dev/null and b/boot_project/LED.map differ
diff --git a/boot_project/Listings/boot.map b/boot_project/Listings/boot.map
index 45e0867..a92edcb 100644
Binary files a/boot_project/Listings/boot.map and b/boot_project/Listings/boot.map differ
diff --git a/boot_project/Listings/boot_GD32F105RC.map b/boot_project/Listings/boot_GD32F105RC.map
new file mode 100644
index 0000000..e3ace1e
Binary files /dev/null and b/boot_project/Listings/boot_GD32F105RC.map differ
diff --git a/boot_project/Listings/boot_STM32F105.map b/boot_project/Listings/boot_STM32F105.map
new file mode 100644
index 0000000..a03a494
Binary files /dev/null and b/boot_project/Listings/boot_STM32F105.map differ
diff --git a/boot_project/Listings/boot_STM32F105RC.map b/boot_project/Listings/boot_STM32F105RC.map
new file mode 100644
index 0000000..97d9f7e
Binary files /dev/null and b/boot_project/Listings/boot_STM32F105RC.map differ
diff --git a/boot_project/Listings/boot_gd32F105.map b/boot_project/Listings/boot_gd32F105.map
new file mode 100644
index 0000000..af7c643
Binary files /dev/null and b/boot_project/Listings/boot_gd32F105.map differ
diff --git a/boot_project/Listings/startup_gd32f10x_cl.lst b/boot_project/Listings/startup_gd32f10x_cl.lst
new file mode 100644
index 0000000..74ce9b8
Binary files /dev/null and b/boot_project/Listings/startup_gd32f10x_cl.lst differ
diff --git a/boot_project/Listings/startup_stm32f10x_cl.lst b/boot_project/Listings/startup_stm32f10x_cl.lst
index ff1bcd0..ff1e9a4 100644
Binary files a/boot_project/Listings/startup_stm32f10x_cl.lst and b/boot_project/Listings/startup_stm32f10x_cl.lst differ
diff --git a/boot_project/Objects/ExtDll.iex b/boot_project/Objects/ExtDll.iex
deleted file mode 100644
index 6c0896e..0000000
--- a/boot_project/Objects/ExtDll.iex
+++ /dev/null
@@ -1,2 +0,0 @@
-[EXTDLL]
-Count=0
diff --git a/boot_project/Objects/boot.axf b/boot_project/Objects/boot.axf
deleted file mode 100644
index c5d0669..0000000
Binary files a/boot_project/Objects/boot.axf and /dev/null differ
diff --git a/boot_project/Objects/boot.build_log.htm b/boot_project/Objects/boot.build_log.htm
deleted file mode 100644
index c6fd0f7..0000000
--- a/boot_project/Objects/boot.build_log.htm
+++ /dev/null
@@ -1,116 +0,0 @@
-
-
-
-µVision Build Log
-Tool Versions:
-IDE-Version: ¦ÌVision V5.25.2.0
-Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Zachary Administrator, Zachary, LIC=TIVNB-2IHDY-01WP1-C2K2G-5HIE0-XG8NS
-
-Tool Versions:
-Toolchain: MDK-ARM Plus Version: 5.25.2.0
-Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler: Armcc.exe V5.06 update 6 (build 750)
-Assembler: Armasm.exe V5.06 update 6 (build 750)
-Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
-Library Manager: ArmAr.exe V5.06 update 6 (build 750)
-Hex Converter: FromElf.exe V5.06 update 6 (build 750)
-CPU DLL: SARMCM3.DLL V5.25.2.0
-Dialog DLL: DCM.DLL V1.17.1.0
-Target DLL: Segger\JL2CM3.dll V2.99.29.0
-Dialog DLL: TCM.DLL V1.35.1.0
-
-Project:
-E:\liudagui\project\HONGRI\code\boot_up\boot_project\hongri_boot.uvprojx
-Project File Date: 11/04/2024
-
-Output:
-*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Rebuild target 'hongri_boot'
-assembling startup_stm32f10x_cl.s...
-compiling misc.c...
-compiling stm32f10x_dma.c...
-compiling led.c...
-compiling stm32f10x_pwr.c...
-compiling stm32f10x_can.c...
-compiling stm32f10x_iwdg.c...
-compiling stm32f10x_flash.c...
-compiling 24cxx.c...
-compiling core_cm3.c...
-compiling stm32f10x_rcc.c...
-compiling stm32f10x_gpio.c...
-compiling bsp_i2c_gpio.c...
-compiling stm32f10x_it.c...
-compiling can2.c...
-compiling dev_flashApi.c...
-compiling dev_crc32.c...
-compiling dev_eerom.c...
-compiling system_stm32f10x.c...
-compiling dev_sys.c...
-compiling UDS.c...
-compiling iso15765-2_entry.c...
-compiling Can_Transceiver.c...
-compiling Diag_Eeprom_C301.c...
-compiling iso15765-2.c...
-compiling CanCtrl_C301.c...
-compiling CanConfig_C301.c...
-compiling UDS_SA_C301.c...
-..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c(48): warning: #177-D: function "BL_BE32_TO_MCU" was declared but never referenced
- static uint32_t BL_BE32_TO_MCU(uint8_t *pBuf)
-..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c: 1 warning, 0 errors
-compiling app_can.c...
-compiling main.c...
-..\boot_source\code_app\main\src\main.c(163): warning: #188-D: enumerated type mixed with another type
- RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP,ENABLE );//
-..\boot_source\code_app\main\src\main.c(164): warning: #188-D: enumerated type mixed with another type
- PWR_BackupAccessCmd(ENABLE);//
-..\boot_source\code_app\main\src\main.c(198): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_1MS = RESET;
-..\boot_source\code_app\main\src\main.c(207): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_5MS = RESET;
-..\boot_source\code_app\main\src\main.c(213): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_10MS = RESET;
-..\boot_source\code_app\main\src\main.c(222): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_20MS = RESET;
-..\boot_source\code_app\main\src\main.c(226): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_50MS = RESET;
-..\boot_source\code_app\main\src\main.c(230): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_100MS = RESET;
-..\boot_source\code_app\main\src\main.c(234): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_1000MS = RESET;
-..\boot_source\code_app\main\src\main.c(89): warning: #177-D: function "Task_RunToAppCheckValide" was declared but never referenced
- static uint8_t Task_RunToAppCheckValide(void)
-..\boot_source\code_app\main\src\main.c: 10 warnings, 0 errors
-compiling Diag_Appl_C301.c...
-..\boot_source\code_app\driver\inc\dev_eerom.h(32): warning: #1-D: last line of file ends without a newline
- /** EOF */
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(1329): warning: #177-D: variable "crc32" was declared but never referenced
- uint32_t crc32=0;
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2026): warning: #550-D: variable "CRC_16" was set but never used
- uint16_t CRC_16=0xFFFF;
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2121): warning: #223-D: function "GetCrc32Chk" declared implicitly
- if(GetCrc32Chk() == transSequenceValue)
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(289): warning: #177-D: function "Diag_ExtMemorySecFAAFlagSave" was declared but never referenced
- static void Diag_ExtMemorySecFAAFlagSave(uint8_t cnt)
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c: 5 warnings, 0 errors
-linking...
-Program Size: Code=22124 RO-data=980 RW-data=252 ZI-data=12716
-FromELF: creating hex file...
-".\Objects\boot.axf" - 0 Error(s), 16 Warning(s).
-
-Software Packages used:
-
-Package Vendor: Keil
- http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.1.0.pack
- Keil.STM32F1xx_DFP.2.1.0
- STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
-
-Collection of Component include folders:
- .\RTE\_hongri_boot
- C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-
-Collection of Component Files used:
-Build Time Elapsed: 00:00:06
-
-
-
diff --git a/boot_project/Objects/boot.hex b/boot_project/Objects/boot.hex
deleted file mode 100644
index 57be32b..0000000
--- a/boot_project/Objects/boot.hex
+++ /dev/null
@@ -1,1463 +0,0 @@
-:020000040800F2
-:10000000A832002085010008153E00088D2A00084E
-:10001000113E0008FD020008F9540008000000002D
-:10002000000000000000000000000000394200084D
-:100030006F10000800000000B53E00086143000892
-:100040009F0100089F0100089F0100089F01000810
-:100050009F0100089F0100089F0100089F01000800
-:100060009F0100089F0100089F0100089F010008F0
-:100070009F0100089F0100089F0100089F010008E0
-:100080009F0100089F0100089F0100089F010008D0
-:100090009F0100089F0100089F0100089F010008C0
-:1000A0009F0100089F0100089F0100089F010008B0
-:1000B0009F0100089F0100089F0100089F010008A0
-:1000C0009F0100089F0100089F0100089F01000890
-:1000D0009F0100089F0100089F0100089F01000880
-:1000E0009F0100089F0100089F0100080000000018
-:1000F0000000000000000000000000000000000000
-:1001000000000000000000009F0100089F0100089F
-:100110009F0100089F0100089F0100089F0100083F
-:100120009F0100089F0100089F0100089F0100082F
-:100130009F0100089F0100089F0100089F0100081F
-:100140009F010008B9040008E90400089F010008A5
-:10015000DFF80CD000F04CF800480047E9560008E2
-:10016000A8320020EFF30980704780F309887047B8
-:10017000EFF30880704780F30888704740BA7047F3
-:10018000C0BA70470648804706480047FEE7FEE7CA
-:10019000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE737
-:1001A000214400085101000840EA01039B0703D0E5
-:1001B00009E008C9121F08C0042AFAD203E011F8A6
-:1001C000013B00F8013B521EF9D27047D2B201E068
-:1001D00000F8012B491EFBD270470022F6E710B54C
-:1001E00013460A4604461946FFF7F0FF204610BDA5
-:1001F000064C074D06E0E06840F0010394E8070074
-:1002000098471034AC42F6D3FFF7A6FF205A0008F7
-:10021000405A00080FB470B5049D9DF81A000828D4
-:1002200002DD08208DF81A000C49049808609DF83A
-:100230001A008872002407E00DF11B00015D0748D9
-:100240000B300155601CC4B29DF81A00A042F3DCCB
-:10025000284600F005F870BC5DF814FB802A0020E9
-:1002600070B5044603254FF6D0702040B0F5806F7E
-:1002700004D1012500201149086010E040F2DF7030
-:10028000844203D040F20B70844204D10225002046
-:100290000A49086003E00325002008490860012D91
-:1002A00004D0022D03D0032D05D103E004E002F0B9
-:1002B000EBFE01E000E000BF00BF70BDF0000020D9
-:1002C00010B501214FF0C05003F0F6FD012003F0FE
-:1002D000EBFD10BD00BF0748006800F4E060064970
-:1002E0000843001D03490860BFF34F8F00BF00BFE4
-:1002F000FEE700000CED00E00000FA0500BFFEE79D
-:1003000002480068C043014908607047D8000020D7
-:1003100000B50648006838B901200549086005485D
-:100320000249086005F0EAF800BD0000E000002086
-:10033000DC0000202083B8ED4FF0FF300149086059
-:1003400070470000D800002030B503460C4609482D
-:100350000268002108E0605C5040C5B2064850F8D1
-:10036000250080EA1222491C9942F4D30148026018
-:10037000002030BDD80000208026002000B589B0C4
-:100380000121092003F0B8FD0121480603F094FD86
-:100390000121880603F090FD4FF40050ADF82000D5
-:1003A00003208DF8220018208DF8230008A940486A
-:1003B00002F08FFA4FF48050ADF8200048208DF8FD
-:1003C000230008A93A4802F084FA00208DF81A00A8
-:1003D00001208DF81B0000208DF81C008DF81D00F9
-:1003E0008DF81E008DF81F008DF8160001208DF885
-:1003F000170008208DF8180001208DF8190006203C
-:10040000ADF8140005A92B4800F0B9FA0E208DF8BC
-:100410000E0000208DF80F0001208DF81000002044
-:10042000ADF80400ADF80600ADF80800ADF80A001C
-:100430000120ADF80C008DF8110001A800F046F97C
-:10044000012210211B4800F091FA41208DF8000094
-:1004500001208DF8010000208DF8020001208DF8A8
-:100460000300684603F0DEFC012005F0A9F8012234
-:100470005102104800F07AFA012291020D4800F072
-:1004800075FA0122D1030B4800F070FA42208DF872
-:10049000000001208DF8010000208DF802000120ED
-:1004A0008DF80300684603F0BDFC002009B000BDD4
-:1004B000000C01400068004000B587B0012005F045
-:1004C0008BF802AA0121074800F0E3FA0698009091
-:1004D00002A80FC8FFF79EFE142102A8FFF77DFEB9
-:1004E00007B000BD0068004010B54FF400712D4802
-:1004F00000F0ACF9012820D12B492A4800F06AF914
-:10050000012815D100BF022808DA284911F8301057
-:1005100021B1264911F83010032900D104E002214D
-:10052000224A02F8301000BF1F491E4800F042F86E
-:100530004FF400711B4800F059F84FF480611948DE
-:1005400000F084F901282BD11749891C154800F0C7
-:1005500041F901281FD10124022C03DA134810F8B5
-:10056000340000B912E00320104901F8340001EB17
-:10057000C401081D002103F0A1FF1CB90C4800F0C4
-:1005800089F802E0074800F085F800BF0649891C99
-:10059000044800F00FF84FF48061024800F026F89C
-:1005A00010BD0000006800400200F010FC000020B8
-:1005B0000064004000220C4B994202D10023836169
-:1005C00011E0C1F3130201F000730BB1C2600AE045
-:1005D00001F080630BB1026105E001F000630BB133
-:1005E000826000E0426070477000F030B1F5007F3B
-:1005F0003AD00FDC202928D006DC01291CD00429A0
-:100600001DD0082940D11DE0402921D0B1F5807FBF
-:100610003AD126E0B1F5004F31D006DCB1F5806F5C
-:1006200025D0B1F5006F2FD124E0B1F5803F12D075
-:10063000B1F5003F28D111E0154A826025E008227B
-:10064000C26022E01022C2601FE0082202611CE0AA
-:100650001022026119E00822426016E01022426076
-:1006600013E00422426010E0042242600DE0042204
-:1006700042600AE0002282610422426005E000221A
-:1006800082610422426000E000BF00BF70470000AA
-:100690000101010010B504460B48844209D1012133
-:1006A000480603F019FC00214FF0007003F014FC21
-:1006B00008E00121880603F00FFC00214FF0806064
-:1006C00003F00AFC10BD00000064004010B50021DA
-:1006D000837A012202FA03F13D4A126842F00102D4
-:1006E0003B4B1A603A4A1C3212688A43384B1C331F
-:1006F0001A60027BCAB9364A0C3212688A43344BFC
-:100700000C331A604288C38842EA0343304A4032BD
-:10071000847A42F834300288838842EA03432C4AC0
-:100720004032847A02EBC4025360027B012A19D161
-:10073000274A0C3212680A43254B0C331A60428850
-:10074000038842EA0343224A4032847A42F8343032
-:10075000C288838842EA03431D4A4032847A02EB0E
-:10076000C4025360C27A3AB9194A121D12688A4308
-:10077000174B1B1D1A6006E0154A121D12680A432A
-:10078000134B1B1D1A60028932B9114A14321268C8
-:100790008A430F4B14331A600289012A06D10C4A8E
-:1007A000143212680A430A4B14331A60427B012A3E
-:1007B00006D1074A1C3212680A43054B1C331A60E3
-:1007C000034A126822F00102014B1A6010BD0000BA
-:1007D0000066004010B50246002001F4700343B1EA
-:1007E0009369C1F3130423400BB101202DE00020D5
-:1007F0002BE001F0807343B15368C1F3130423402D
-:100800000BB1012021E000201FE001F0006343B1A3
-:100810009368C1F3130423400BB1012015E00020BD
-:1008200013E001F0007343B1D368C1F31304234014
-:100830000BB1012009E0002007E01369C1F31304A4
-:1008400023400BB1012000E0002010BD70B504462C
-:100850000D46002660692840002871D0B5F5807FDC
-:100860005CD010DC082D35D006DC012D20D0022D07
-:1008700024D0042D72D127E0102D31D0202D35D079
-:10088000402D6BD138E0B5F5004F60D009DCB5F5EF
-:10089000007F49D0B5F5806F4CD0B5F5006F5DD1C4
-:1008A0004FE0B5F5803F2DD0B5F5003F56D12FE094
-:1008B000A0682D4900F0D2FB064651E0E068032114
-:1008C00000F0CCFB06464BE0E068082100F0C6FBD8
-:1008D000064645E0E068102100F0C0FB06463FE018
-:1008E0002069032100F0BAFB064639E0206908219F
-:1008F00000F0B4FB064633E02069102100F0AEFBA7
-:1009000006462DE06068082100F0A8FB064627E0B7
-:100910006068102100F0A2FB064621E0A0690121D9
-:1009200000F09CFB06461BE0A069022100F096FB4C
-:10093000064615E0A069042100F090FB06460FE092
-:100940000FE0A069702100F089FB064608E06068AE
-:10095000042100F083FB064602E0FFE7002600BF0B
-:1009600000E00026304670BD010101001AB1436964
-:100970000B43436102E043698B434361704730B5E9
-:10098000024600200023146824F002041460146856
-:1009900044F00104146000E05B1C546804F001049E
-:1009A0001CB94FF6FF74A342F6D1546804F0010459
-:1009B0000CB900206CE08C79012C04D1146844F04F
-:1009C0008004146003E0146824F080041460CC797F
-:1009D000012C04D1146844F04004146003E014684E
-:1009E00024F0400414600C7A012C04D1146844F003
-:1009F0002004146003E0146824F0200414604C7A8E
-:100A0000012C04D1146844F01004146003E014684D
-:100A100024F0100414608C7A012C04D1146844F082
-:100A20000804146003E0146824F008041460CC7A0D
-:100A3000012C04D1146844F00404146003E0146829
-:100A400024F0040414608C78A407CD7844EA05648B
-:100A50000D7944EA05444D7944EA05540D886D1E2C
-:100A60002C43D461146824F001041460002300E0D6
-:100A70005B1C546804F001041CB14FF6FF74A342E0
-:100A8000F6D1546804F001040CB1002000E001200C
-:100A900030BD10B500F5D87303EB01131B6803F0EC
-:100AA00004031372137A53B900F5D87303EB0113DF
-:100AB0001B6840F2FF7404EA5353136009E000F529
-:100AC000D87303EB01131B686FF0604404EAD3038F
-:100AD000536000F5D87303EB01131B6803F00203A6
-:100AE000537200F5D87303EB01135B6803F00F0337
-:100AF000937200F5D87303EB01135B681B0AD37480
-:100B000000F5D87303EB01139B68D37200F5D8731B
-:100B100003EB01139B681C0A147300F5D87303EBF5
-:100B200001139B681C0C547300F5D87303EB01137D
-:100B30009B681B0E937300F5D87303EB0113DB68FE
-:100B4000D37300F5D87303EB0113DB681C0A14742C
-:100B500000F5D87303EB0113DB681C0C547400F52B
-:100B6000D87303EB0113DB681B0E937421B9C368C0
-:100B700043F02003C36003E0036943F020030361F3
-:100B800010BD10B502460020936803F08063B3F1F6
-:100B9000806F00D110E0936803F00063B3F1006F41
-:100BA00001D1012008E0936803F08053B3F1805F26
-:100BB00001D1022000E00420042874D002F5C073A3
-:100BC00003EB00131B6803F0010402F5C07303EB91
-:100BD00000131C600B7A7BB94B7A0C8843EA4453B0
-:100BE00002F5C07404EB00142468234302F5C074BA
-:100BF00004EB0014236010E00B7A4C6843EAC40352
-:100C00004C7A234302F5C07404EB00142468234398
-:100C100002F5C07404EB001423608B7A03F00F0319
-:100C20008B7202F5C07303EB00135B6823F00F04B3
-:100C300002F5C07303EB00135C6002F5C07303EBB5
-:100C400000135B688C7A234302F5C07404EB001434
-:100C500063608B7B1C064B7B44EA03440B7B44EABA
-:100C60000323CC7A234302F5C07404EB0014A36081
-:100C70008B7C1C064B7C44EA03440B7C44EA032334
-:100C8000CC7B234302F5C07404EB0014E36002F54F
-:100C9000C07303EB00131B6843F0010402F5C0733B
-:100CA00003EB00131C6010BD10B50246002321B1F8
-:100CB000012907D002290FD109E090681D4C00EAF4
-:100CC00004030BE090681C4C00EA040306E0906803
-:100CD0001A4C00EA040301E0002300BF00BF184CD7
-:100CE000181BA34216D007DC83B16FF08060184454
-:100CF00070B1022818D111E0B0F5007F10D0114C6E
-:100D0000204448B1B0F5003F0ED10BE002230DE0C6
-:100D100000230BE0002309E0002307E0012305E0A6
-:100D2000012303E0012301E0002300BF00BFD8B28C
-:100D300010BD0000030000040003000800000310C1
-:100D4000000100080001FFF70FB430B585B00024A2
-:100D5000142208A96846FFF727FA012004F050FC86
-:100D600020B9012005B030BC5DF814FB69460E487F
-:100D7000FFF707FF0546002401E0601C84B2012054
-:100D800004F03EFC40B129460748FFF78DFF18B933
-:100D900040F6FF708442F0DB40F6FF70844201DBD6
-:100DA0000120DFE70020DDE70068004010B50020EB
-:100DB00000F00AF910BD70473048407820F040003C
-:100DC0002E4948700846407820F0200048700846B8
-:100DD000407820F0100048700846807820F00F001E
-:100DE00088700846807820F0F00088700846007807
-:100DF00020F0010008700846007820F00800087014
-:100E00000846007820F0040008700846007820F0BA
-:100E1000020008700846007820F02000087008469C
-:100E2000007820F0100008700846007820F080005C
-:100E300008700846007820F04000087008464078A6
-:100E400020F0010048700846407820F00200487009
-:100E50000846407820F00400487000204871C1F82E
-:100E6000F000C1F8F400C1F8F800C1F8FC00C1F8C6
-:100E7000EC004FF6FF70A1F8E600704770150020F7
-:100E80000148007870470000F600002010B50024EB
-:100E9000002012490870124908701249087012495E
-:100EA000087072B6FFF788FF00240DE000200F499C
-:100EB00008550F4908552146012001F041FE204602
-:100EC00001F030FE601CC4B2012CEFDB00F09AF898
-:100ED00001F0BEFF03F0A8FD62B610BDF7000020D0
-:100EE000F6000020F8000020F5000020F9000020A6
-:100EF000FA0000200949097842290DD107494978AB
-:100F00004F2909D105498978452905D10349C9786F
-:100F1000522901D1012000E0002070478E000020FE
-:100F200010B506480078002806DD04480078401E09
-:100F30000249087003F0D2FC10BD0000F800002048
-:100F400002480078401C014908707047F6000020F4
-:100F50000149087070470000F500002010B5FFF748
-:100F60002AFF02F0E5FC04F045F9FFF7E9FFFFF77F
-:100F7000D7FF10BD10B503480078012801D104F057
-:100F800029F910BDF700002000204FF4AC7000E0FC
-:100F9000401E0028FCD1704710B50446012C00DB30
-:100FA00010BD44B98021064801F068FD10210548B4
-:100FB00001F064FD00E000BF00BF00BFF0E70000EB
-:100FC00000100140000C014010B50446012C00DB6C
-:100FD00010BD74B91021094801F04EFD8021084868
-:100FE00001F04CFDFFF7D0FF8021054801F044FDE2
-:100FF00000E000BF00BF00BFEAE70000000C0140B6
-:101000000010014010B50020FFF7C6FF10BD000022
-:1010100010B500240F480078012817D1FFF79EFF74
-:101020000D480068B0F5FA6F0AD3FFF7BFFE06E07F
-:10103000601C84B2B4F5487F01DBFFF74BF9F7E79A
-:1010400005480068401C0449086002E0012001498D
-:10105000087010BDF7000020F000002002460020BC
-:1010600002EA01030BB1012000E000207047704745
-:101070000120014908707047C200002070B5044685
-:10108000012501F0FDFCA04200D10025284670BDDD
-:1010900038B502221021684604F0C8FA0546012D31
-:1010A00001D0002038BD002409E01DF8040006A18D
-:1010B000095D884201D00020F4E7601CC4B2022C14
-:1010C000F3DB0120EEE700004852000010B50548B0
-:1010D000807800F00F00012802D1FFF7D9FF10BD82
-:1010E0000120FCE77015002000200549897801F0F7
-:1010F0000F01012901D1012000E00120704700000B
-:101100007015002002460020A2F57143843B73B99C
-:101110000B78632B01DD012008E04B783C2B01DDCF
-:10112000012003E08B781F2B00DD012000E000BFD1
-:1011300000BF704770B5054604F0BCFA72B68B2D3F
-:1011400006D10E480068012182680D48904711E0E1
-:101150002E2D0FD1002404E0AA200A490855601C56
-:10116000C4B2082CF8DB054800680822054943682A
-:101170000348984704F0A6FA62B670BD2800002024
-:1011800000380208A8000020002004E0AA21034A39
-:101190001154411CC8B20828F8DB70478E000020AB
-:1011A000012802D0022800D000BF7047012802D0D9
-:1011B000022800D000BF70472DE9F0410446207995
-:1011C000401CC6B22068477820688578032E03DC6F
-:1011D000132003F0BBFF44E037B1032F1BD0802F57
-:1011E00003D0832F2ED117E000BF042E05D013208B
-:1011F00003F0ACFF03F0B6FC32E00220A081032D27
-:1012000001DC012D03DA312003F0A0FF02E02846C3
-:10121000FFF7CCFF24E000BF042E05D0132003F01D
-:1012200095FF03F09FFC1BE00220A081032D01DC51
-:10123000012D03DA312003F089FF02E02846FFF791
-:10124000AFFF0DE003F006FA18B1802003F0BCFFF9
-:1012500005E0002003F0B8FF122003F077FF00BF85
-:1012600000BF03F037FCBDE8F08170B5044620797B
-:10127000401CC6B22068457825F08005022E03D1B7
-:10128000132003F063FF1FE0012D02D0022D0CD1CB
-:1012900000E000BF032E05D0132003F057FF03F03A
-:1012A00061FC10E00220A0810DE003F0D3F918B139
-:1012B000802003F089FF05E0002003F085FF122065
-:1012C00003F044FF00BF00BF03F004FC70BD00004A
-:1012D00070B50246002028E00D5C2B02002421E0BE
-:1012E000134DB5F8E6505D4005F4004555B1104D7D
-:1012F000B5F8E65041F2210686EA45050C4EA6F8FF
-:10130000E65009E00A4DB5F8E6504FF6FF7606EADA
-:101310004505074EA6F8E6504FF6FF7505EA43036C
-:10132000651CECB2082CDBDB401C9042D4D370BDB2
-:10133000701500202DE9F04105460E4617464FF086
-:1013400000081448807800F00F00012805D01148EB
-:10135000807800F00F00022814D104F0ABF972B6C7
-:101360000D4800683A46314643682846984780460B
-:1013700004F0A8F962B6B8F1000F01D1002402E030
-:10138000012400E0012414B90120BDE8F08100200F
-:10139000FBE70000701500202800002070B504460F
-:1013A0002079401CC5B22068467826F08006022DC0
-:1013B00003DC132003F0CAFE2FE0012E02D0032E1F
-:1013C0001CD10DE0032D05D0132003F0BFFE03F068
-:1013D000C9FB04E00220A0810A20114908701BE02B
-:1013E000032D05D0132003F0B1FE03F0BBFB04E096
-:1013F0000220A0810A200B4908700DE003F02AF9B1
-:1014000018B1802003F0E0FE05E0002003F0DCFED0
-:10141000122003F09BFE00BF00BF03F05BFB70BD1A
-:1014200044000020450000202DE9F05F06460F46ED
-:1014300090461B48B0F8E84000252BE04FF44830B8
-:10144000B5FBF0F100FB115010B9404603F02EFA45
-:1014500017F805B04FEA0B294FF0000A16E084EAAE
-:10146000090000F4004028B141F2210080EA440064
-:1014700084B203E04FF6FF7000EA44044FF6FF70B9
-:1014800000EA49090AF1010000F0FF0ABAF1080F69
-:10149000E5DB6D1CB542D1D32046BDE8F09F0000CE
-:1014A00070150020704710B50346002003E01C5C57
-:1014B0000C54441CE0B29042F9DB10BD10B5034659
-:1014C000002002E00C5C1C54401C9042FAD310BD7A
-:1014D0001D48007820F0800080301B4908700020F3
-:1014E000C1F8EC00C1F8F400C1F8F00008464078FB
-:1014F00020F0010048700846007820F002000870D3
-:101500000846007820F0040008700846007820F0B3
-:10151000200008700846007820F001000870084696
-:10152000007820F0080008700846407820F010008D
-:1015300048700846807820F00F0088700846807850
-:1015400020F0F000887070477015002070B50646D6
-:101550000C461546224629463046FFF7AFFF70BDC0
-:101560002DE9F04F9BB007464FF00008C34600241A
-:101570003879401C00F0FF0801201A90B8F1040FE0
-:101580000FD0B8F1060F0CD0B8F1080F09D0B8F1A0
-:101590000A0F06D0B8F10C0F03D0132003F0D6FDCC
-:1015A00083E04FF0010BBBF1050F01DD4FF0050BA0
-:1015B000012400255BE0012101EB45013868405C16
-:1015C0000DF804001DF804004FEA002A601CC4B2A4
-:1015D000022101EB45013868405C0DF804001DF85C
-:1015E000040040EA0A0A601CC4B2002019900026D8
-:1015F0002DE0304800EB06100088504525D1012031
-:1016000019902C4800EB0610407A012803D12A4992
-:1016100051F8260080474FF000090DE0254800EB07
-:101620000610406810F809000DF80400601CC4B2F0
-:1016300009F1010000F0FF091E4800EB0610007AD6
-:101640004845EBDC00201A9003E0701CC6B2052E62
-:10165000CFDB00BF03F050F910B100201A9008E072
-:10166000199810B901201A9003E0681CC5B25D45B5
-:10167000A1DB00BFBC81012505E01DF80500B968AC
-:101680004855681CC5B2A542F7DB1A9801280CD151
-:1016900002F0E0FF18B1802003F096FD05E0002085
-:1016A00003F092FD312003F051FD03F013FA1BB05B
-:1016B000BDE8F08FB8590008085A0008002005E07E
-:1016C0000449095C044A1154411CC8B20528F7DBDF
-:1016D0007047000033580008B0000020002005E0EB
-:1016E0000449095C044A1154411CC8B20928F7DBBB
-:1016F000704700002A5800083D150020002004E033
-:10170000FF21034A1154411CC8B20628F8DB704778
-:10171000B500002070470000002005E00449095C86
-:10172000044A1154411CC8B20928F7DB7047000075
-:1017300021580008341500202DE9FC410446257984
-:1017400020684678206887780B2D03D0132003F09B
-:10175000FDFC46E10EB9442F03D0312003F0F6FC26
-:101760003FE1C5480078C0F3400018B1702003F095
-:10177000EDFC36E12068C0788DF80400206800791F
-:101780008DF80500206840798DF806002068807982
-:101790008DF807002068C0798DF800002068007A75
-:1017A0008DF801002068407A8DF802002068807A68
-:1017B0008DF803009DF8040000069DF8051000EB6D
-:1017C00001409DF8061000EB01209DF80710084429
-:1017D000A949C1F8F8009DF8000000069DF8011025
-:1017E00000EB01409DF8021000EB01209DF8031072
-:1017F0000844A149C1F8FC0008460078C0F3C000C5
-:10180000002857D10846D0F8FC00B0F5805F0AD810
-:101810000846D0F8F800401C28B10846D0F8F80077
-:101820009649884203D0312003F090FCD9E09248D9
-:10183000D0F8F8009149884207D18F48807820F08D
-:10184000F00010308C4988700CE08B48D0F8F8001C
-:101850008B49884206D18848807820F0F0002030FB
-:10186000854988708448007820F008000830824953
-:1018700008700846007820F00200801C08700020E4
-:10188000C1F8EC00C1F8F000C1F8F4004FF6FF70A9
-:10189000A1F8E6002020A16848700420A1688870A3
-:1018A0000020A168C8700420A081FEF731FDFEF77A
-:1018B00043FD96E07048D0F8F800724988420FD096
-:1018C0006D48D0F8F800B0F5601F09D06A48D0F82C
-:1018D000F800B0F1805F03D0312003F037FC7AE0EC
-:1018E0006548D0F8F8006749884205D16248D0F8C9
-:1018F000FC00B0F5CC3F17D85F48D0F8F800B0F541
-:10190000601F05D15C48D0F8FC00B0F5002F0BD863
-:101910005948D0F8F800B0F1805F09D15648D0F8A6
-:10192000FC00B0F1806F03D9312003F00FFC52E0CE
-:1019300051484078C0F3800018B9222003F006FC1B
-:1019400049E04D48D0F8F8004E49884207D14A484E
-:10195000807820F00F00401C474988701AE0464804
-:10196000D0F8F800B0F5601F07D14348807820F028
-:101970000F00801C404988700CE03F48D0F8F80008
-:10198000B0F1805F06D13C48807820F00F00801CC9
-:10199000394988703848007820F00200801C3649A8
-:1019A00008700020C1F8EC00C1F8F000C1F8F400A4
-:1019B0004FF6FF70A1F8E6002020A16848700420CF
-:1019C000A16888700020A168C8700420A081FEF77B
-:1019D0009FFCFEF7B1FC2848007820F0080026495B
-:1019E000087002F089FF98B32348007820F00200C5
-:1019F000214908700846007820F040000870084629
-:101A0000007820F0800008700846407820F001003F
-:101A100048700846807820F00F008870084680786B
-:101A200020F0F00088700020C1F8F800C1F8FC0038
-:101A3000C1F8F4004FF6FF70A1F8E6000020C1F8ED
-:101A4000EC00C1F8F000887500210B48C1750176E3
-:101A50000948007820F010000749087008464078CF
-:101A600020F0100048700846407820F020004870B0
-:101A700003F030F8BDE8FC817015002000F0002074
-:101A800000D8BFFE00A000082DE9F04105460E4633
-:101A900000270F48854214D1B6F5CC3F11D803F08A
-:101AA00009FE72B60B4800683321826808489047E7
-:101AB000074603F007FE62B60FB9002402E00124D6
-:101AC00000E0012414B90120BDE8F0810020FBE70B
-:101AD00000A000082800002070B504464FF6FF76ED
-:101AE0002579012D03D0132003F030FB86E0454813
-:101AF000007800F0010040B142484078C0F3800017
-:101B000018B9222003F022FB78E03E480078C0F3A9
-:101B1000400020B13B484078C0F3001018B92420A1
-:101B200003F014FB6AE03748007820F01000103012
-:101B3000344908700846407820F010004870084684
-:101B4000007820F0200008700846007820F002009D
-:101B500008700846407820F0040048700846407835
-:101B600020F02000487000204871C1F8EC00C1F856
-:101B7000FC00C1F8F8000846007800F0010010B938
-:101B80000020C1F8F4001F480078C0F3C00018B16D
-:101B90001C48B0F8E6602DE01A48807800F00F008D
-:101BA000012808D117493722D1F8F4001649FFF768
-:101BB0003BFC06461EE01348807800F00F00022828
-:101BC00009D110493722D1F8F4004FF46011FFF722
-:101BD0002BFC06460EE00B48807800F00F00022830
-:101BE00008D108493722D1F8F4004FF08051FFF7AF
-:101BF0001BFC0646FEF784FB0120A08102F06AFF71
-:101C000070BD00007015002000A000082DE9FC5FE9
-:101C100004464FF0000B2579206846782068C0788C
-:101C20002168897800EB01201FFA80FA042D06DA7A
-:101C3000132003F08BFA02F04DFFBDE8FC9F5046E5
-:101C4000BAF57F4F73D009DCA0F2022040B3A0F5B3
-:101C50005C40A0F5EF7000286AD107E06FF47F4187
-:101C60000844002877D00128F6D168E002F036FE5B
-:101C7000032803D07F2003F069FA10E0052D03D07C
-:101C8000132003F063FA0AE0012E03D0122003F0C0
-:101C90005DFA04E00020A16808710520A08169E1D7
-:101CA0002068007900062168497900EB014021682D
-:101CB000897900EB01202168C97900EB0109082D21
-:101CC00003D0132003F042FA38E0012E03D0122093
-:101CD00003F03CFA32E0AA480078C0F3001018B9CB
-:101CE000222003F033FA29E0312002F0DFFD4846DC
-:101CF000FFF7C4F9E8B9A248807800F00F00012886
-:101D000002D19F49C87002E001209D4908719C489A
-:101D1000007820F010009A4908700846007820F0FA
-:101D20000100401C08700020A168087104E025E053
-:101D300012E10120A16808710520A0811AE102F0DA
-:101D4000CDFD032808D002F0C9FD022804D07F2071
-:101D500003F0FCF911E0B7E0042D03D0132003F0E9
-:101D6000F5F90AE0012E03D0122003F0EFF904E0A8
-:101D70000020A16808710520A081FBE00D2D03D192
-:101D800020680079442803D0132003F0DFF99AE09B
-:101D9000012E03D0122003F0D9F994E02068407995
-:101DA0008DF80400206880798DF805002068C079DE
-:101DB0008DF806002068007A8DF807002068407AC8
-:101DC0008DF800002068807A8DF801002068C07AC4
-:101DD0008DF802002068007B8DF803009DF8040058
-:101DE00000069DF8051000EB01409DF8061000EB81
-:101DF00001209DF8071047189DF8000000069DF887
-:101E0000011000EB01409DF8021000EB01209DF84D
-:101E1000031000EB01085B48874251D1B8F5CC3F75
-:101E200005D8574880780121B1EB101F18D05448CD
-:101E3000007820F00200524908700846007820F02F
-:101E4000080008700846407820F0400048700846B6
-:101E5000807820F0F0008870312003F077F932E0CC
-:101E6000312002F023FD41463846FFF70DFE0128E0
-:101E700022D14348407820F00400001D40494870BA
-:101E80000846407820F0400048700846407820F02E
-:101E90000800487000F06AFA8B20FFF74BF9002029
-:101EA000A16808710520A0813548007820F0010064
-:101EB000401C3349087006E0722003F047F902E045
-:101EC000312003F043F955E0042D03D0132003F033
-:101ED0003DF940E0012E03D0122003F037F93AE03B
-:101EE00027484078C0F3801018B9222003F02EF95B
-:101EF00031E0FFF7EBF8012821D1FFF7F5F80128D1
-:101F00001DD11F480079012819D11D48C07801282A
-:101F100015D1FFF739F92E20FFF70CF91848407852
-:101F200020F008000830164948700020A1680871A8
-:101F30000520A081002012490871C87002E022200B
-:101F400003F004F900200E49C1F8F4000846807837
-:101F500020F00F0088700DE002F07CFB18B18020AB
-:101F600003F032F905E0002003F02EF9312003F0F0
-:101F7000EDF800BF00BF02F0ADFD00BF5DE6000060
-:101F80007015002000A000082DE9FE43054602F070
-:101F9000ABFC07462879401CC6B2286890F801803F
-:101FA000022E03DC132003F0D1F8CDE1B8F1010FCC
-:101FB00009D0B8F1020F6CD0B8F1050F6FD0B8F1AD
-:101FC000060F6DD13EE1012F03D17F2003F0BEF853
-:101FD0005EE0032E03D0132003F0B8F858E0DC488D
-:101FE000007801280ED1A9684870002405E000217E
-:101FF000A01CAA681154601CC4B2042CF7DB062094
-:10200000A88145E0D348007A012803D0D148807ADE
-:10201000012803D1372003F099F839E00120A9689D
-:102020004870CD480078012812D1CA48007B0328A7
-:102030000EDB362003F08AF80120C64988720020A2
-:102040008880C648007810B90120C44908707AE138
-:10205000C148007810B9C24802F0BEF8002406E07A
-:10206000BF48015DA01CAA681154601CC4B2042CB6
-:10207000F6DB02ABBB4A0421B94802F025F8002088
-:10208000B449087208800120B34908700620A8816D
-:1020900059E1012F05D17F2003F058F868E068E08E
-:1020A00043E1072E03D0132003F050F860E0AA4864
-:1020B0000078012859D10020A7490870A548807AE6
-:1020C000012803D1362003F041F849E0002406E05E
-:1020D000A01C2968085C0DF80400601CC4B2042C24
-:1020E000F6DB9DF800008DF804009DF801008DF8E6
-:1020F00005009DF802008DF806009DF803008DF89C
-:102100000700042201A9974801F0CCFF90B10220FA
-:10211000A9684870A881002003F01EF801208C49AE
-:10212000087000208D4908708A49087302208E4982
-:10213000087015E0352003F009F88648007B401C44
-:10214000844908730846007B032809DB0120887254
-:10215000002088808148007810B901207F490870EC
-:1021600000207C490880087202E0242002F0EEFF83
-:10217000E9E0012F03D17F2002F0E8FF61E0032EA8
-:1021800003D0132002F0E2FF5BE0714840780128A1
-:102190000FD10520A9684870002405E00021A01C8B
-:1021A000AA681154601CC4B2042CF7DB0620A88175
-:1021B00047E06848407A012803D06648C07A012881
-:1021C00003D1372002F0C2FF3BE00520A968487028
-:1021D00061484078012812D15E48407B03280EDB1D
-:1021E000362002F0B3FF01215A48C1720021C1809C
-:1021F0005A48407810B9012058494870A3E0564821
-:10220000407810B9564801F0E7FF002406E0544832
-:10221000015DA01CAA681154601CC4B2042CF6DB3A
-:1022200002AB504A04214E4801F092FF0021494878
-:1022300041720020474948800120474948700620E4
-:10224000A88180E0012F03D17F2002F07FFF6BE0A7
-:10225000072E03D0132002F079FF65E03E48407856
-:1022600001285ED100203C4948703A48C07A0128D4
-:1022700003D1362002F06AFF4CE0002406E0A01CE7
-:102280002968085C0DF80400601CC4B2042CF6DB5D
-:102290009DF800008DF804009DF801008DF8050000
-:1022A0009DF802008DF806009DF803008DF80700E8
-:1022B000042201A92B4801F0F5FEA0B10620A9686F
-:1022C00048700220A881002002F046FF012020492A
-:1022D000487000202149487000211E4841730420A5
-:1022E0002149087016E0352002F030FF1948407B84
-:1022F000401CC1B217484173407B03280ADB01210F
-:102300001448C1720021C1801448407810B90120DE
-:102310001249487000200F49488000210D48417241
-:1023200002E0242002F012FF0DE002F093F918B150
-:10233000802002F049FF05E0002002F045FF122056
-:1023400002F004FF00BF00BF02F0C4FBBDE8FE8343
-:10235000C000002070260020BD0000208C0000205E
-:10236000C7000020C3000020C20000204220044912
-:1023700008704F204870452088705220C870704700
-:102380008E0000202DE9F04705460024A246A14614
-:10239000A888801E86B228684778FD4890F8058096
-:1023A00008F1010000F0FF08012E02DA132002F00C
-:1023B000CDFEB6F5806F03DD712002F0C7FEFCE1B3
-:1023C000F3480078C0F3800050B9F148D0F8F0002D
-:1023D000B0F5406F04D8EE484078C0F3001070B1FB
-:1023E000EB48407820F01000E949487008464078F2
-:1023F00020F040004870702002F0A8FEDDE1E448C3
-:102400000078C0F3801028B9E14800780121B1EBD1
-:10241000D01F03D1722002F099FECEE1DC48007893
-:10242000C0F3400018B9242002F090FEC5E1D8485E
-:102430004078C0F3401028B9012F03D0732002F078
-:1024400085FEBAE1781C804502D10220A881B4E162
-:10245000B84503D0732002F079FEAEE1CC48007895
-:1024600000F0010040B1CA484078C0F3800018B9BC
-:10247000222002F06BFEA0E1C548007820F0200089
-:102480002030C34908700846407820F020002030F2
-:10249000487008464771007800F0010000287CD0A1
-:1024A000002415E0A01C2968085CB949D1F8F01097
-:1024B000B84A5054B648D0F8F000401CB449C1F8AE
-:1024C000F0000846D0F8F400401CC1F8F400641C89
-:1024D000B442E7D32868811C3046FDF735FFAC488D
-:1024E000D0F8F400AA49D1F8FC10884277D3A84864
-:1024F000D0F8F000B0F5006F2DD3A5494FF400627D
-:10250000D1F8F800A349FEF715FF40B9FEF7E0FF48
-:10251000722002F01BFE02F0DDFABDE8F0879C4855
-:10252000D0F8F80000F500609949C1F8F8000846B5
-:10253000D0F8F000A0F50060C1F8F000002405E03C
-:1025400004F500609349085C0855641C9048D0F875
-:10255000F000A042F4D88E48D0F8F000F0B18C48DA
-:10256000D0F8F09005E0FF208A4901F8090009F150
-:102570000109B9F5006FF6D385494FF40062D1F82F
-:10258000F8008449FEF7D6FE40B9FEF7A1FF72209D
-:1025900002F0DCFD02F09EFABFE7A5E000207C49D6
-:1025A000C1F8F0000846407820F001004870084665
-:1025B000007820F0040008700846007820F0200021
-:1025C00008700846407820F04000403048700846C7
-:1025D000407820F01000103048707EE0FFE76C4833
-:1025E000D0F8F000B0F5006F77D36948407820F05C
-:1025F0000100401C664948700846007820F004003D
-:10260000001D08704FF40062D1F8F8006149FEF730
-:1026100091FE38B9FEF75CFF722002F097FD02F0E0
-:1026200059FA7AE75A48007820F080005849087033
-:102630000846D0F8F80000F50060C1F8F800084638
-:10264000D0F8F000A0F50060C1F8F000002405E02B
-:1026500004F500604F49085C0855641C4C48D0F8EC
-:10266000F000A042F4D84A48D0F8EC00401C484999
-:10267000C1F8EC000846807800F00F00012805D171
-:102680000846D0F8EC00B0F5607F17D84048807855
-:1026900000F00F00022805D13D48D0F8EC00B0F55D
-:1026A000607F0BD83A48807800F00F0002280ED1E6
-:1026B0003748D0F8EC00B0F5802F08D9FEF708FFB6
-:1026C000722002F043FD02F005FA26E705E03048EB
-:1026D000007820F040002E4908702D48007820F046
-:1026E00004002B49087066E0B6F5805F58DA0024D4
-:1026F0000FE0A01C2968085C2549D1F8F010254A94
-:1027000050542348D0F8F000401C2149C1F8F00093
-:10271000641CB442EDD31E49D1F8F0001D49FEF708
-:10272000D7FD2868811C3046FDF70EFE1848D0F80A
-:10273000F400194900EB010A154880780121B1EB3A
-:10274000101F0BD10AEB06001449884206D210482C
-:10275000104AD0F8F0105046FEF7F8FE0C48D0F8BA
-:10276000F4000B49D1F8F01008440949C1F8F4000D
-:102770000846D0F8F400D1F8FC10884217D304487A
-:10278000407820F010001030014948700FE0000040
-:10279000701500207016002000F00020FFFF0020C0
-:1027A00000200B49C1F8F400312002F0CFFC0020DA
-:1027B0000749C1F8F0000220A8810548007820F000
-:1027C00010000349087002F085F900BFA5E600007B
-:1027D000701500202DE9F047054695F8048028681B
-:1027E000407806022868807806432868C71C4FF0A6
-:1027F0000109B8F1030F03DC132002F0A7FC5CE031
-:10280000002447E02F4800EB04100088B0423FD17D
-:102810002C4800EB0410407A072839D1294800EBF6
-:102820000410007AC01C404505D0132002F08EFC35
-:102830004FF0000930E039463046FEF763FC0128CE
-:1028400005D1312002F082FC4FF0000924E0032082
-:10285000A8811C4800EB0410027A1A4800EB04100F
-:1028600041683846FEF71FFE164800EB041000884A
-:102870004FF28411884208D100F028F812484078BD
-:1028800020F00200801C104948704FF0000903E05E
-:10289000601CC4B2052CB5DB00BFB9F1010F0CD12F
-:1028A00001F0D8FE18B1802002F08EFC05E0002077
-:1028B00002F08AFC312002F049FC02F00BF9BDE87D
-:1028C000F0870000B8590008701500200146FF206D
-:1028D00070472DE9F0410246002500260020002324
-:1028E0000024002791F803C00CF00F0591F803C0F5
-:1028F0000CF0100CBCF1000F03D091F802C04CEAB0
-:10290000050591F800C0BCF1000F31D0146800201B
-:102910002BE04FF0010C0CFA00F3B1F800C00CEA08
-:1029200003069E4220D183004FF00F0C0CFA03F7F0
-:10293000BC4305FA03FC4CEA040491F803C0BCF163
-:10294000280F06D14FF0010C0CFA00FCC2F814C09D
-:102950000AE091F803C0BCF1480F05D14FF0010C1B
-:102960000CFA00FCC2F810C0401C0828D1D3146037
-:10297000B1F800C0BCF1FF0F34DD546800202EE038
-:1029800000F1080C4FF0010808FA0CF3B1F800C090
-:102990000CEA03069E4221D183004FF00F0C0CFA83
-:1029A00003F7BC4305FA03FC4CEA040491F803C0A6
-:1029B000BCF1280F05D100F1080C08FA0CF8C2F898
-:1029C000148091F803C0BCF1480F07D100F1080C46
-:1029D0004FF0010808FA0CF8C2F81080401C0828D3
-:1029E000CED35460BDE8F081F0B50A460023002440
-:1029F0000021002500F00046B6F1004F02D11D4E27
-:102A0000F16901E01B4E7168C0F3034583B200F425
-:102A10004016B6F5401F08D121F07061154E76685A
-:102A200026F07066134F7E6012E000F48016B6F553
-:102A3000801F06D1032606FA05F4A14341F0706118
-:102A400006E0460D360103FA06F6B14341F0706127
-:102A500022B1460D360103FA06F6314300F0004676
-:102A6000B6F1004F02D1034EF16101E0014E7160F9
-:102A7000F0BD0000000001404161704701617047F6
-:102A80000148006870470000D800002000BFFEE742
-:102A9000704700002DE9F04F95B004468A469046F5
-:102AA0001E460025402105A8FDF797FB0020049055
-:102AB0000027012003904FF0000B194800EB441051
-:102AC00000680490164800EB44104779FF2E00D0B0
-:102AD0003746402F00D94027114800EB4410D0F86A
-:102AE0001C90002505E019F8050005A94855681C4B
-:102AF000C5B2BD42F7D305ABCDE90074514640469F
-:102B0000049A00F029F88346BBF1000F02D101209E
-:102B1000039001E000200390039815B0BDE8F08F0A
-:102B20003858000810B50446012C06DA0020034985
-:102B300008552146012000F003F810BDFB000020DD
-:102B4000012803D10122034B5A5402E00022014B19
-:102B50005A547047F40000202DE9F04F87B0064624
-:102B60008B4617469846DDE910954FF0000A012E76
-:102B700003DB012007B0BDE8F08F1F48C0F80490C8
-:102B800000201D4948721D4800EB4510007908706F
-:102B90001A4800EB4510407C08B1012000E00020FD
-:102BA00015498872154800EB4510807C08B101205A
-:102BB00000E000201049087200208DF810000297F4
-:102BC000084600798DF8120000208DF811000024CD
-:102BD00006E018F804100DF113000155601CC4B292
-:102BE0009DF81200A042F4DC0698009002A80FC8DD
-:102BF000FEF7AAF85046BDE7982A0020385800088A
-:102C00002DE9F04106460C46154600270848005DB0
-:102C100008B1012C02DB0020BDE8F0812B462246E2
-:102C200039463046FFF736FF80464046F4E700005D
-:102C3000F400002010B54FF400600B49086002F06A
-:102C40004BFD4FF480600849091F086002F044FD05
-:102C50004FF480600449086002F03EFD4FF40060CC
-:102C60000149091F086010BD140C014010B54FF454
-:102C700000600949086002F02FFD4FF480600649AA
-:102C8000086002F029FD4FF480600349091D0860C7
-:102C900002F022FD10BD0000100C014070B5054689
-:102CA0000024002618E06006040E4FF480600F49EF
-:102CB000086002F011FD0D480838006800F400605B
-:102CC00008B1601CC4B24FF480600849091D086057
-:102CD00002F002FD701CC6B2082EE4DB15B9FFF746
-:102CE000C5FF01E0FFF7A6FF204670BD100C0140B4
-:102CF00070B50446002524E004F0800020B14FF4B4
-:102D000000601149086004E04FF400600E49091D9D
-:102D1000086002F0E1FC4FF480600B49086002F0AB
-:102D2000DBFC4FF480600849091D0860072D02D1C3
-:102D30004000091F08606006040E02F0CDFC681C0C
-:102D4000C5B2082DD8DB70BD100C014010B54FF492
-:102D500000600A4908604010086002F0BDFC4FF4B2
-:102D600000600649091D086002F0B6FC4FF480605F
-:102D70000249091D086002F0AFFC10BD100C0140B3
-:102D800010B54FF40060074908604010091F086043
-:102D900002F0A2FC4FF400600249091F086002F033
-:102DA0009BFC10BD140C014010B54FF400600E499F
-:102DB000086002F091FC4FF480600B49086002F05B
-:102DC0008BFC09480838006800F4006008B1012451
-:102DD00000E000244FF480600349091D086002F000
-:102DE0007BFC204610BD0000100C014010B50446CD
-:102DF0000548827A00212046FFF702FF012800D112
-:102E000010BD0020FCE700001C15002070B5054631
-:102E10000C46224600212846FFF7F2FE012800D189
-:102E200070BD0020FCE7000010B50446044800789F
-:102E300010B900F0E1FD01E000F034FC10BD00002D
-:102E40006600002010B500F04DFC00F01DFE10BD26
-:102E500010B50020044908710449C870FF200449D6
-:102E60000870FFF7EFFF10BD600000205A0000203F
-:102E7000660000203EB57948006878498988084492
-:102E800001907748C078052806D0062834D0072856
-:102E900076D0082875D1A1E07048C088082817DBD3
-:102EA00000207049096808706C4880796D4909688C
-:102EB00048706C480068801C00906848C088ADF875
-:102EC00008006649C988891C88B200F00DFD12E02F
-:102ED0006248807963490968087062480068401C4C
-:102EE00000905E48C088ADF808005C49C988491C5C
-:102EF00088B200F0F9FCA8E05849C88800F0F4FC5A
-:102F00005648C088B0F5805F3CDB10205549096801
-:102F10000870544800680078524909680870002019
-:102F20005049096848704D48C08800164D490968E5
-:102F3000887000204B490968C8704848C088000A5A
-:102F400048490968087145488079464909684871C7
-:102F500044480068801D00904048807A801F80B2FD
-:102F6000ADF808003D48807A801F3C4988800846BB
-:102F7000408920F4706048810020394988702CE035
-:102F80002DE060E010203749096808703548006876
-:102F900000783249C988C1F30321084331490968DF
-:102FA00008702E4880792F49096848702D480068BC
-:102FB000801C00902948807A801E80B2ADF80800FD
-:102FC0002648807A801E254988800846408920F45A
-:102FD0007060488100202249887036E000BF2020C0
-:102FE0002049096808701F48006800781B49498912
-:102FF000C1F3032108431B49096808701948006898
-:10300000401C00901648C078082808D11348C08892
-:1030100012498988401A80B2ADF8080005E00F48CF
-:10302000807A401E80B2ADF808000C488188807A12
-:10303000401E084409498880BDF80810491C88B220
-:1030400000F052FC01E001203EBD00BF06480168CF
-:103050006846884704462046F6E700001C15002015
-:103060005A0000206C00002084000020002005E0B1
-:10307000AA21044A12681154411CC8B20828F7DB7F
-:10308000704700006C00002070B5FE48867A082E5C
-:1030900001D0002070BDFB48C07A00F0F00038B1CC
-:1030A000102804D020287DD030287CD154E200BFE5
-:1030B000F548007998B1F4480079012801D1002041
-:1030C000E8E7F048C07A022826D1EE48007B3E2887
-:1030D00022D1EC48407B80281ED10020DAE7E94865
-:1030E000C07A022818D1E748007B3E2814D1E54871
-:1030F000407B802810D1E548008828B9E448008842
-:1031000010B9E448007938B10020E0490880012076
-:10311000E14908700020BDE700F0E4FA0220DA4936
-:1031200008710020DD498880D648C07A00F0F000A0
-:1031300000287DD010287CD1D2480088C0F30A0036
-:1031400040F2DF71884206D10120CF49087100F0BA
-:1031500005FB00209EE7D248C078022807D0D0485F
-:10316000C078032803D0CE48C078082806D10120B3
-:10317000C549087100F0F2FA00208BE7082E7AD1D9
-:10318000C048C07A00F00F004FF6FF7101EA00203E
-:10319000C249C8800846C088BA49097B0843BF496C
-:1031A000C88001E0DEE06AE20846C088072869DDE1
-:1031B00000204881B3480D3008600B46D988B14BD8
-:1031C0001B88C3F30A00B74B1A689047B3490860DD
-:1031D0000846807A00F0030088B102280ED103204F
-:1031E000A9490880072008710846808820F480706B
-:1031F00000F58070888000F0BBFA42E000BFA7486D
-:103200000068C8B39F48407BA449096808709D487E
-:10321000807BA249096848709A48C07B9F49096829
-:1032200088709848007C9D490968C870954801E0FD
-:1032300035E08FE0407C9949096808719148807CAD
-:103240009649096848710620944988800846008993
-:1032500020F00F00401C088103208B4908800520C6
-:1032600008710846808820F4807000F5807088809E
-:1032700000F07EFA04E00BE0FFE7002082490871CD
-:1032800000BF0AE001208049087100F067FA04E0FD
-:1032900001207D49087100F061FA0020FAE67948C2
-:1032A0000088C0F30A00804908807648C07A7B49CC
-:1032B000C8800846C088401CB04244DC0846C0882C
-:1032C00007283ADC0846C08880B3002048816D4852
-:1032D0000C3008600B46D9886A4B1B88C3F30A0080
-:1032E000704B1A6890476D49086008460068F0B155
-:1032F0000846807A00F00300C8B9002407E061485E
-:103300000C30005D654909680855601CC4B263480B
-:103310008079401EC0B2A042F1DA01205A490871FA
-:103320005E4AD088614A1168884711E005E00120B3
-:103330005549087100F012FA0AE00120524908715B
-:1033400000F00CFA04E001204F49087100F006FA81
-:1033500000209FE601204C49087100F0FFF900BFF2
-:1033600000BF8DE147480088C0F30A0040F2DF71DA
-:10337000884206D101204449087100F0EFF900208D
-:1033800088E641480079032803D03F4800790528A2
-:1033900076D13D48007905280FD13B488088C0F39D
-:1033A000002040B942490878FFF772FB404908788D
-:1033B000FFF73AFD01E000206CE638488088C01D28
-:1033C0003649C988884237DB3448C0883349898800
-:1033D000401A401CB0420EDC2A48C07A00F00F00B0
-:1033E0002E49097A01F00F01884205D001202649B3
-:1033F000087100F0B3F9ACE000240AE021480C3079
-:10340000005D26490968254A928811440855601CC8
-:10341000C4B2224881790079401C081AC0B2A04287
-:10342000ECDA012018490871002008801B4AD08876
-:103430001E4A116888478CE0082E0BD11148C07ACB
-:1034400000F00F001549097A01F00F01884202D0FF
-:1034500000F048F97DE00B48017B104800680F4AF6
-:10346000928881540748407B0C4909680B4A92882E
-:10347000114448700348807B08490968074A19E0ED
-:1034800069E00000802A0020600000205200002037
-:10349000540000204800002056000020281500207D
-:1034A0005A0000207C0000205800002070000020FE
-:1034B000680000209288114488707348C07B73496B
-:1034C0000968724A92881144C8706F48017C6F483D
-:1034D00000686E4A9288104401716B48407C6B49C9
-:1034E00009686A4A9288114448716748817C674834
-:1034F0000068664A92881044817164488088C01DC3
-:10350000624988800846007A401C098960F30301FB
-:103510005E4801815E488078B0B15D488078401E89
-:103520005B4988700846807870B9052008710320CF
-:1035300008800846808820F4807000F580708880BC
-:1035400000F016F90020A5E50F205149088003205E
-:10355000087100209EE593E04B480088C0F30A0004
-:103560004C49098888420ED047480088C0F30A00B9
-:1035700040F2DF71884206D101204549087100F010
-:10358000EDF8002086E54448C078022807D042487C
-:10359000C078062803D04048C07807286ED13E483E
-:1035A000007900F00100A0B93B48C078062807D098
-:1035B0003948C07807280ED13748807801280AD1C9
-:1035C00036490878FFF764FA34490878FFF72CFC8D
-:1035D00001E000205EE53048C07802284CD1032E7F
-:1035E0004ADB2948C07A302804D0312839D0322823
-:1035F0003ED13AE028480079C0F38000F8B9264867
-:10360000808820F00400001D234988801E48007B2C
-:10361000234908721C48457B0A2D02DA01204872B2
-:1036200016E005F0800058B1F02D05DDF92D03DC22
-:1036300001201B4948720BE00E201949487207E02F
-:1036400005F109000A2190FBF1F0401C1449487271
-:103650001348007A10498870012008800320C87040
-:1036600009E00F200C49088005E000F00DFA02E0A7
-:1036700000F00AFA00BF00BF00200BE500E000BF29
-:1036800000BF002006E50000802A00202815002049
-:1036900060000020580000205A0000206800002030
-:1036A0001C1500200D480079052802D007280DD1EF
-:1036B00007E00F200949088003200871FF20C87027
-:1036C00005E0002005490880087100E0704700BF50
-:1036D000FF200349087000BFF8E7000060000020E9
-:1036E0006600002010B518480079012809DD164849
-:1036F0000079082805D00820134908711349086883
-:10370000804700201049088008710846808820F40E
-:10371000807088800846808820F4007088800C487B
-:10372000008920F00F000A490881002048810948DB
-:103730000078802806D108490878FFF7A9F9FF200A
-:103740000449087010BD00006000002074000020D3
-:1037500028150020660000206800002010B5FFF743
-:10376000C1FF10BD014A508170470000281500209C
-:1037700070B538488088C0F34020D8B1354DA8884E
-:10378000C0F34020002863D02846808820F40070D1
-:103790002946888030490878FFF728FB0446002C2A
-:1037A00056D12846808820F4007000F50070294624
-:1037B00088804DE027488088C0F30020002847D04B
-:1037C000244DA888C0F30020002841D02348007869
-:1037D000FF283DD18020214908702846808820F4A8
-:1037E00080702946888008201D498872002605E0DF
-:1037F000AA201C4909688855701CC6B21848807AEE
-:10380000B042F5DC13480079072804D1322015496D
-:103810000968087003E03020124909680870002028
-:1038200010490968487001200E4909688870002015
-:103830000849887008490878FFF7D8FA04463CB967
-:103840000448808820F4007000F5007001498880E9
-:1038500070BD0000600000206800002066000020AD
-:103860001C1500206C00002010B51E4800880028A0
-:1038700036D01C4C2088002832D020460088401EBC
-:10388000214608800846008840BB08460079032886
-:1038900006D0052807D0062809D007281CD103E048
-:1038A000FFF720FF19E000BFFFF71CFF15E00D48F0
-:1038B000C07810B9FFF716FF0DE003200949088012
-:1038C000052008710846808820F4807000F580701B
-:1038D0008880FFF74DFF00E000BF01E0FFF748FFE1
-:1038E00010BD0000600000200C4A12780C4B03EB66
-:1038F00042125179884202DB0A4A91720CE0C2B24C
-:10390000094B9A5C094B9A5C064B9A721A46927A5A
-:10391000082A01DA08229A72704700006800002025
-:10392000385800081C150020CC570008BC57000868
-:1039300010B5FFF799FF00F067F910BD10B5034609
-:1039400009B9012010BD1648C07808B10320F9E775
-:103950001448807A082801DD022200E00122114883
-:10396000807A801A80B2884203DB05200C4CE0701C
-:1039700002E006200A4CE0700320094C2080094830
-:1039800003600020074CA0802046C1800448808846
-:1039900020F00100401C024CA0800020D2E7000073
-:1039A0005A0000201C15002011484089000A401CC4
-:1039B0000F49498960F30B210D4841818188807A44
-:1039C000401E80B208440A49C988884203DB0820A7
-:1039D0000849C87002E007200649C870032005495D
-:1039E00008800846808820F00100401C88807047CD
-:1039F0001C1500205A00002010B51F48C07805286B
-:103A000006D006280ED0072817D008282CD100E0B1
-:103A100000BF1A4801680020884700201649088026
-:103A2000C87022E00F20144908800220C8700846A0
-:103A3000808820F00400888017E00F48807860B10B
-:103A40000D488078401E0C4988700846807820B95F
-:103A50000F2008800220C87007E00948407A064914
-:103A600008800320C87000E010BD00BFFF2005499A
-:103A7000087000BFF8E700005A000020780000201E
-:103A80001C1500206600002010B501241B48C078DA
-:103A900001280EDD1948C07809280AD009201749E5
-:103AA000C870174908688047044614B900201349B4
-:103AB000C8700020114908800846808820F0010065
-:103AC00088800846808820F00200888054B1002059
-:103AD000C8700C4908720846408920F4706048811B
-:103AE000082088720848007830B908490878FEF73D
-:103AF000CFFFFF200449087010BD00005A000020CD
-:103B0000800000201C1500206600002068000020B6
-:103B100070B539480079C0F34000D0B1364DA8885F
-:103B2000C0F34000002866D02846808820F00200BC
-:103B30002946888031490878FFF758F90446002C57
-:103B400059D12846808820F00200801C29468880B0
-:103B500051E02948007900F0010000284BD0264DA3
-:103B6000A88800F00100002845D025480078FF28EB
-:103B700041D10020224908702846808820F00100A9
-:103B800029468880FFF772FAFFF774F906466EB986
-:103B90001A490878FFF72AF9044664BB284680884A
-:103BA00020F00200801C2946888024E01248C0785A
-:103BB000072807D01048C078082803D00E48C078DE
-:103BC00006280ED10C48C078062803D100200D49E4
-:103BD000888006E00B488188807A401E081A0949CF
-:103BE0008880FF20064908700348808820F0010083
-:103BF000401C0149888070BD5A00002068000020E8
-:103C0000660000201C15002010B51648008820B35F
-:103C1000144C208808B320460088401E21460880A6
-:103C200008460088D0B90846C078801E072813D2FD
-:103C3000DFE800F00407120C0D0E0F00FFF724FF61
-:103C40000BE0FFF7B1FEFFF763FF06E000BF00BF28
-:103C500000BFFFF719FF00E000BF01E0FFF758FFCA
-:103C600010BD00005A00002008B5074840680090C9
-:103C700006490098086004490868FCF77CFA034884
-:103C80000068804708BD000000A00008E800002090
-:103C900008B501211C2000F02FF94FF40070ADF899
-:103CA000000010208DF8030003208DF80200694603
-:103CB0005348FEF70EFE4FF400715148FEF7DEFE4A
-:103CC0000120ADF8000010208DF8030003208DF8CE
-:103CD000020069464A48FEF7FCFD01214848FEF70C
-:103CE000CDFE40F20240ADF8000010208DF8030038
-:103CF00003208DF8020069464148FEF7EAFD0221E3
-:103D00003F48FEF7BBFE4FF480613D48FEF7B4FE2E
-:103D1000A020ADF8000010208DF8030003208DF8DE
-:103D2000020069463748FEF7D4FD20213548FEF7EA
-:103D3000A3FE80213348FEF7A1FE44F22720ADF810
-:103D4000000010208DF8030003208DF80200694662
-:103D50002D48FEF7BEFD4FF400712B48FEF78EFE96
-:103D600001212948FEF788FE02212748FEF784FE3C
-:103D700004212548FEF780FE4FF480412248FEF7DB
-:103D80007BFE20212048FEF777FE4FF48070ADF8CF
-:103D9000000048208DF8030069461948FEF799FD98
-:103DA0004FF40070ADF8000048208DF8030069461C
-:103DB0001448FEF78EFD0121084600F09DF8012110
-:103DC0001248FEF711FE1020ADF8000001208DF81A
-:103DD000020010208DF8030069460B48FEF779FDBC
-:103DE00010210948FEF74AFE4FF40050ADF80000DC
-:103DF00004208DF8030069460248FEF76AFD08BDFD
-:103E00000008014000100140000C0140000130009A
-:103E100000BFFEE7704710B54FF4A06000F03AF81D
-:103E200010BD000070B5002100230F22C47804B338
-:103E3000154C246804F4E064C4F5E064210AC1F17F
-:103E40000403CA40447804FA03F1847814402143FF
-:103E500009010E4C0678A155047804F01F050124D1
-:103E6000AC4005786D11AD0005F1E025C5F80041C5
-:103E700009E0047804F01F050124AC40044D0678E5
-:103E8000761145F8264070BD0CED00E000E400E03E
-:103E900080E100E002490143024A116070470000DE
-:103EA0000000FA050CED00E00149086270470000CF
-:103EB00000000E427047000029B1064AD269024351
-:103EC000044BDA6104E0034AD2698243014BDA61B0
-:103ED000704700000010024029B1064A12690243EF
-:103EE000044B1A6104E0034A12698243014B1A61D0
-:103EF000704700000010024029B1064A926902434F
-:103F0000044B9A6104E0034A92698243014B9A612F
-:103F100070470000001002402DE9F041002100220E
-:103F2000002500230026002400278C46DFF860814E
-:103F3000D8F8048008F00C0121B1042907D0082921
-:103F400059D109E0DFF84C81C0F8008058E0DFF873
-:103F50004481C0F8008053E0DFF83481D8F8048051
-:103F600008F47012DFF82881D8F8048008F480354E
-:103F7000920C0D2A01D0921C00E0062235B9DFF820
-:103F8000188102FB08F8C0F8008033E0DFF80081F8
-:103F9000D8F82C8008F48036DFF8F480D8F82C802C
-:103FA00008F00F0808F1010446B9DFF8E880B8FB13
-:103FB000F4F808FB02F8C0F800801BE0DFF8D080BE
-:103FC000D8F82C80C8F3031808F10107DFF8C08087
-:103FD000D8F82C80C8F3032808F1020CDFF8B4806D
-:103FE000B8FBF7F808FB0CF8B8FBF4F808FB02F88C
-:103FF000C0F8008004E0DFF89C80C0F8008000BFBB
-:1040000000BFDFF88C80D8F8048008F0F0010909BF
-:10401000DFF8888018F80130D0F8008028FA03F81B
-:10402000C0F80480DFF86880D8F8048008F4E06104
-:10403000090ADFF8688018F80130D0F8048028FAFF
-:1040400003F8C0F80880DFF84880D8F8048008F446
-:104050006051C90ADFF8448018F80130D0F80480B4
-:1040600028FA03F8C0F80C80DFF82480D8F8048020
-:1040700008F44041890BDFF8288018F80130D0F8A7
-:104080000C80B8FBF3F8C0F81080BDE8F0810000A8
-:104090000010024000127A0000093D0000000020DC
-:1040A0001000002070B503460C460120002107E0F7
-:1040B000655C5E5CB54201D0002003E04D1CE9B2B6
-:1040C0009142F5DB00BF70BD78B50C46057845B967
-:1040D000457835B9857825B9C57815B900251D709D
-:1040E00078BD002107E0455C184E765C75400DF800
-:1040F00001504D1CE9B20429F5DB9DF8015005F093
-:10410000F0059DF8006006F00F0645EA06151570EB
-:104110009DF801502D072D0E9DF8026045EA1615F9
-:1041200055709DF8025005F0F0059DF8036045EAD2
-:10413000161595709DF8035005F00F069DF8005078
-:1041400066F31F15D5701C7000BFC9E71C5A000824
-:1041500078B50C46057845B9457835B9857825B9DF
-:10416000C57815B900251D7078BD002107E0455CB4
-:10417000184E765C75400DF801504D1CE9B20429CB
-:10418000F5DB9DF8005005F00F069DF8015066F331
-:104190001F1515709DF801502D099DF8026006F05D
-:1041A0000F0645EA061555709DF8035005F0F00519
-:1041B0009DF8026045EA161595709DF8035005F0CC
-:1041C0000F059DF8006045EA1615D5701C7000BFFC
-:1041D000CAE700001C5A00082DE9F0410446FCF72C
-:1041E0004FFE0546134800782844C5B2002612E069
-:1041F000691C42F2BB02514343F2390202EB410017
-:10420000C11700EB11610912A0EB0127FDB204F800
-:10421000015B701CC6B2042EEADB06480078401C25
-:104220000449087008460078642801D1002008700D
-:10423000BDE8F081E4000020704710B500F002F8FE
-:1042400010BD00000CB500200190009040480068AF
-:1042500040F480303E49086000BF3D48006800F4EB
-:10426000003000900198401C0190009820B94FF652
-:10427000FF7101988842F0D13548006800F40030A1
-:1042800010B10120009001E000200090009801286A
-:104290005CD13048006840F010002E4908600846A4
-:1042A000006820F0030008600846006840F0020043
-:1042B00008602748406826494860084640684860CA
-:1042C0000846406840F4806048600846C06A224959
-:1042D00008401F49C8620846C06A204908431C4973
-:1042E000C8620846006840F08060086000BF184857
-:1042F000006800F000600028F9D01548406820F4FC
-:104300007C10134948600846406840F4E810486053
-:104310000846006840F08070086000BF0C480068E4
-:1043200000F000700028F9D00948406820F0030030
-:10433000074948600846406840F00200486000BFF6
-:104340000348406800F00C000828F9D10CBD0000BB
-:10435000001002400020024000F0FEFF140801009F
-:104360000F480068401C0E4908600E480068401C59
-:104370000C4908600A4800684FF47A71B0FBF1F20A
-:1043800001FB1200012804D107480068401C0649BF
-:1043900008600648007810B9012004490870704789
-:1043A000340000202C0000203800002030000020C5
-:1043B00030B5164800684FF47A72B0FBF2F1B1F1F3
-:1043C000807F01D301201DE021F07F40401E4FF08F
-:1043D000E022506150170F22002807DA13071D0E44
-:1043E0000B4B00F00F04241F1D5503E013071C0E98
-:1043F000084B1C5400BF00204FF0E02290610720C2
-:104400001061002008B100BFFEE730BD140000209D
-:1044100018ED00E000E400E010B5FFF725FC10BD4A
-:1044200010B51648006840F00100144908600846BD
-:10443000406813490840114948600846006811491E
-:1044400008400E4908600846006820F48020086093
-:104450000846406820F4FE0048600846006820F0E6
-:10446000A05008604FF47F0088600020C862FFF70A
-:10447000E4FE4FF000600449086010BD00100240E7
-:104480000000FFF0FFFFF6FE08ED00E010B50A485F
-:104490000078401C084908700846007803280ADBA9
-:1044A00000200870002401E0601CC4B2012CFBDB7A
-:1044B00072B6FFF7B1FF10BDEC00002002460023EA
-:1044C00021B90D4800681060012070470A48036850
-:1044D0001068984205D81068181A884209D301203C
-:1044E000F3E71068C0F1FF301844884201D301207F
-:1044F000EBE70020E9E70000340000204F48007897
-:1045000001280AD14E484089401C4D49488101206C
-:10451000087000204949087000E070474848408909
-:10452000052190FBF1F201FB120030B944484089AB
-:1045300018B101204249487000E0EEE74048408948
-:104540000A2190FBF1F201FB120028B93C48408996
-:1045500010B101203A49887039484089142190FBF4
-:10456000F1F201FB120028B93548408910B1012051
-:104570003349C87032484089322190FBF1F201FB87
-:10458000120028B92E48408910B101202C49087129
-:104590002B484089642190FBF1F201FB120028B9FD
-:1045A0002748408910B10120254948712448408995
-:1045B0004FF4FA7190FBF1F201FB120028B9204888
-:1045C000408910B101201E4988711D4840894FF46F
-:1045D0007A7190FBF1F201FB120028B9184840896A
-:1045E00010B101201649C8711548408940F2DC51CC
-:1045F00090FBF1F201FB120028B91148408910B17B
-:1046000001200F4908720E4840894FF4FA6190FB6F
-:10461000F1F201FB120028B90948408910B10120CC
-:10462000074948720648408941F27071884202DBAE
-:1046300000200349488100BF6FE7000030000020E0
-:104640000C01002000200249087048804860704733
-:104650003C00002003484078022801D10120704727
-:104660000020FCE75801002010B504462046FCF766
-:10467000A3FD10BD70B53848007900F04000B8B116
-:104680003548007920F0400033490871012408467C
-:10469000407900B104243148007818B124F00104B5
-:1046A00044F0020404F0010010B1002000F05AFDB3
-:1046B0002948007902281AD104202749087128487E
-:1046C00080680078274948700020244908702448F1
-:1046D0008089C82802DA2248858900E0C825EAB224
-:1046E0001F4B19699868FCF7DEFE00F049FA1A487A
-:1046F000007900F0100068B300201B4908801748BB
-:10470000007878280AD11948007838B11348007821
-:10471000782814D115484088012810D120200E494E
-:1047200008710E48007808B9012000E002200C4909
-:1047300088700F490A480161083000F0ADFE074853
-:104740000078782806D109480078012802D1022093
-:104750000149087170BD0000480000205000002091
-:104760005801002070010020520000203C00002071
-:104770003D0B002010B504462046FCF776FD10BD29
-:1047800070B5044601252289D4E9000100F003F840
-:104790000025284670BD03E0531E9AB28B5C8354FB
-:1047A000002AF9D1704700002DE9F041044638484D
-:1047B000007800F07F072068457825F0800594F8A0
-:1047C0000480B8F1010F03D1132000F0BFFC5BE0BF
-:1047D000012D04D0022D04D0032D44D100E000BFF0
-:1047E00000BFB8F1020F05D0132000F0AFFC00F0BD
-:1047F000B9F948E0012F01D1022D03D0022F07D1D2
-:10480000032D05D17E2000F0A1FC00F0ABF93AE0C9
-:10481000032F04D1022D02D101201D49087100206F
-:1048200000F0A0FC002606E000201A4988551A492D
-:104830008855701CC6B2022EF6DBFCF719FC062068
-:10484000A0810020A16888703220A168C870012072
-:10485000A1680871F420A1684871032D02D10120DC
-:10486000FCF776FB0FE0FFF7F5FE20B180200B4947
-:104870000968C87006E0002008490968C87012205D
-:1048800000F064FC00BF00BF00F024F9BDE8F08137
-:1048900058010020BD000020C0000020480000207A
-:1048A00010B504462046FCF779FD10BD10B504464E
-:1048B0000320094908707F204870084684707820DA
-:1048C000C870AA20087148718871C8710821002039
-:1048D000FEF79CFA10BD0000180100200148007886
-:1048E00070470000580100200248007800F07F0067
-:1048F0007047000058010020014800787047000010
-:10490000500000200A4A127902F0FE02084B1A7188
-:1049100049B91A461268824205D11A46127942F004
-:1049200002021A7170470122024B1A7000BFF9E7A8
-:10493000480000205600002070B504460D46A078BF
-:10494000012804D0022803D0032806D104E000BFC8
-:10495000284600F057F801E000E000BF00BF00204B
-:10496000A07070BD01460120044A127942F0010294
-:10497000024B1A711A46116000207047480000204F
-:104980002DE9F04104460D46002740F6C41085424B
-:1049900003DD0220FEF7E6FE16E040F2DF708442FF
-:1049A00003D102200A49487006E040F20B708442AD
-:1049B00002D101200649487005488581FFF7D2FFE2
-:1049C00006460EB9024887683846BDE8F081000007
-:1049D0005801002010B5044600210448FFF792FF5B
-:1049E000FEF7BCFE05200249088010BD58010020DA
-:1049F0005200002010B503210148FFF783FF10BDCE
-:104A0000580100200021054A1180054948714021C4
-:104A1000034A11710121034A1170704752000020AE
-:104A2000480000205600002010B500201E49887064
-:104A300001200870087148710020C8701B48886008
-:104A40001B491948016100201A49487108717F20EB
-:104A50001949087078208870002018490870184992
-:104A60000870FFF7EFFD1748007820F02000154987
-:104A7000087000240EE0002113480155801E0155E6
-:104A8000001F20F8141000200F490A3921F81400E3
-:104A9000601CC4B2022CEEDBFCF7EAFA00200B49E2
-:104AA00008800B49088010BD5801002079010020C2
-:104AB0003D0B002048000020700100205000002025
-:104AC00056000020BB0000207A2600205400002061
-:104AD0005200002010B517480079042822D116484A
-:104AE0000269846823781548007848B17F201070E7
-:104AF000537012480078907003210F48818208E0BB
-:104B00000C480068C078802803D003F14000107082
-:104B1000521C0A480078782801D0FFF793FD08203E
-:104B2000044908710348007940F0100001490871F8
-:104B300010BD000048000020580100205000002057
-:104B400010B504462046FCF70BFD10BD10B5044619
-:104B50002046FCF7F1FD10BD10B504462046FCF7D9
-:104B6000BBFF10BD002002490968C87070470000F3
-:104B70004800002010B504462046FDF747F810BD58
-:104B80002DE9F05F4FF00008F8488468067B207834
-:104B9000F749085C00EB4000F64901EB80004578DE
-:104BA0002078F349085C00EB4000F24901EB8000FB
-:104BB00090F804902078EE49085C00EB4000ED4945
-:104BC00001EB800090F805A0FFF78EFE074694F8F1
-:104BD00000B02078862800DBC346E7480078C0F3A1
-:104BE000401058B1E1484078022807D18020E349BD
-:104BF0000968C870FFF76EFFBDE8F09FDC4810F849
-:104C00000B00FF2874D0012F04D0022F71D0032F86
-:104C100070D14DE0D5484078022848D12078272827
-:104C20000ED020782E280BD020782F2808D020787E
-:104C3000312805D02078342802D02078372809D1AF
-:104C40007F20CF4908708020CC490968C870FFF7E1
-:104C500041FFD1E7607800F0800040B32078C4497C
-:104C6000085C00EB4000C34901EB8000C078F0B164
-:104C70002078192802D02078282804D18020BF4924
-:104C80000968C87013E02078B949085C00EB40005F
-:104C9000B84911F82000B04205D01320B849087077
-:104CA000FFF718FFA8E78020B4490968C8709FE0A3
-:104CB000AE48407802284BD1207827280ED02078A3
-:104CC0002E280BD020782F2808D02078312805D026
-:104CD0002078342802D0207837280CD17F20A849AA
-:104CE00008708020A5490968C870FFF7F3FE83E7C4
-:104CF000C8E12EE07BE0607800F0800040B32078CF
-:104D00009B49085C00EB40009A4901EB8000C078A9
-:104D1000F0B12078192802D02078282804D18020EA
-:104D200096490968C87013E020789149085C00EB47
-:104D30004000904911F82000B04205D0132090495E
-:104D40000870FFF7C7FE57E780208C490968C870D4
-:104D50004EE086484078022848D1207827280ED097
-:104D600020782E280BD020782F2808D020783128C2
-:104D700005D02078342802D02078372809D17F2028
-:104D80007F49087080207D490968C870FFF7A2FE3E
-:104D900032E7607800F0800040B320787449085C06
-:104DA00000EB4000734901EB8000C078F0B120783F
-:104DB000192802D02078282804D180206F4909685A
-:104DC000C87013E020786A49085C00EB400069492C
-:104DD00011F82000B04205D0132069490870FFF790
-:104DE00079FE09E7802065490968C87000E000BFC6
-:104DF00000BF20785E49085C00EB40005D4901EB94
-:104E00008000C078002875D0607800F0800000280D
-:104E100071D0012E6FDD207828285AD004DC1028AC
-:104E200007D0112868D105E03E287CD08528F9D12B
-:104E3000D4E000BF607881280ED0607883280BD042
-:104E40006078822802D12078112805D060788228E5
-:104E50002DD1207810282AD1022E03D013204849C2
-:104E6000087035E0FFF740FD012816D1062D01D06E
-:104E7000042D09D1002042490870607800F08000BC
-:104E80003E490968C87023E0B8F1000F20D14FF007
-:104E900001087E203A4908701AE00020384908705D
-:104EA000607800F0800035490968C87010E02F482C
-:104EB0004078022806D1802030490968C870FFF781
-:104EC00009FE99E6607800F080002C490968C870F6
-:104ED000CDE0032E11D02548407802280DD123487B
-:104EE0004078022841D1802024490968C870FFF722
-:104EF000F1FD81E6C1E0BBE0B2E06078802802D03D
-:104F00006078832823D1FFF7EFFC012815D1052D08
-:104F10000AD100201A490870607800F08000174913
-:104F20000968C87021E02DE0B8F1000F1DD14FF0E5
-:104F300001087E201249087017E00020104908700F
-:104F4000607800F080000D490968C8700DE00748DE
-:104F50004078022806D1802008490968C870FFF708
-:104F6000B9FD49E612200649087080E0580100208A
-:104F7000305900089458000870150020480000209F
-:104F8000500000206078802819D1FFF7ADFC01287F
-:104F90000BD1042D21D1002060490870607800F009
-:104FA00080005F490968C87017E000205B490870FD
-:104FB000607800F080005A490968C8700DE05948CF
-:104FC0004078022806D1802055490968C870FFF74B
-:104FD00081FD11E612205149087048E0022E07D0E9
-:104FE00050484078022803D113204C49087036E01D
-:104FF0006078812802D06078822822D1FFF774FC83
-:10500000012814D1032D09D100204449087060788B
-:1050100000F0800042490968C87020E0B8F1000F34
-:105020001DD14FF001087E203C49087017E0002098
-:105030003A490870607800F0800039490968C87002
-:105040000DE038484078022806D1802034490968AC
-:10505000C870FFF73FFDCFE512203049087006E029
-:10506000607800F080002E490968C87000BF17E022
-:1050700000202B490968C87012E0002028490968FF
-:10508000C8700DE011202549087026484078022894
-:1050900006D1802022490968C870FFF71BFDABE5E7
-:1050A0001E48007888BB022D01D1022F07D1032DA5
-:1050B00001D1032F03D1052D07D1012F05D17F2069
-:1050C00016490870FFF706FD26E01648007900EA49
-:1050D000090020B91348407900EA0A0028B13320BA
-:1050E0000E490870FFF7F6FC16E005200E4908800F
-:1050F00020780E4A105C00EB40000D4A02EB800065
-:10510000816808480830884706E0FFE70020044926
-:105110000968C870FFF7DEFC00BF6DE55000002095
-:10512000480000205801002052000020305900089B
-:105130009458000810B504462046FCF725FF10BD22
-:10514000014948717047000058010020014908706A
-:1051500070470000500000200149087170470000AE
-:105160005801002070B5044612488068057811483F
-:105170008068407800F07F06012C03D1012000F008
-:1051800047F904E0102D02D1304600F041F9FFF755
-:10519000ABFB01280CD10020FBF7DAFEFBF778FF10
-:1051A000012805D1FBF7A6FE10B90A2002490870B4
-:1051B00070BD000058010020440000200149087122
-:1051C000704700005801002001490968C870704705
-:1051D0004800002010B50348007908B1FFF74AFAEB
-:1051E00010BD00004800002010B5FBF711FFFFF7CD
-:1051F0004DF910BD10B500F02BF810BD70B5044688
-:105200002068457825F080052679012E03D11320EA
-:10521000FFF79CFF19E06DB9022E05D01320FFF7B0
-:1052200095FFFFF79FFC10E00020A1684870022066
-:10523000A0810AE01220FFF789FFFFF793FCFFF738
-:1052400009FA10B18020FFF7BFFFFFF743FC70BDE4
-:1052500010B56548008818B364480078012806D165
-:105260000020624908704FF4FA705F490880604876
-:105270000079A8B95C480088401E5B490880084650
-:10528000008868B9002008800120FFF76BFF002428
-:1052900004E0002057490855601CC4B2022CF8DB1A
-:1052A0005348007900F00C00C0B153480088A8B101
-:1052B00051480088401E504908800846008868B957
-:1052C0004B480068807830B90320494909688870E4
-:1052D00000F0CEF802E0012047490880002455E0A4
-:1052E000464830F81400B0F57A7F06DB4348001DCD
-:1052F00030F81400B0F57A7F46DA4048001D30F8E7
-:105300001400401C81B23D48001D20F81410001FFD
-:1053100030F81400401C394921F8140001F108004C
-:10532000005D012810D1084630F81400B0F57A7FEE
-:105330002ADB002021F814000021304808300155F4
-:1053400000202F4908551FE02C480A30005D012835
-:105350001AD12A48001D30F81400B0F57A7F13DB0B
-:105360000020274908550021244808300155001F16
-:1053700020F81410801D0155801C005D032803DBFC
-:1053800002211E480C300155601CC4B2022CA7DB60
-:105390001C480078002809DD1A480078401E194989
-:1053A00008700846007808B9FAF794FF16480078A4
-:1053B000002809DD14480078401E1349087008468B
-:1053C000007808B9FAF786FF10480078002809DD50
-:1053D0000E480078401E0D4908700846007808B94C
-:1053E000FAF778FF10BD000054000020560000209E
-:1053F00048000020C000002052000020702600203D
-:10540000BD00002044000020450000204600002090
-:1054100010B50446FFF768FA01280AD1FFF7CEFE5F
-:1054200004F07F00012810D04FF4FA700B49088077
-:105430000BE004F07F00012807D1FFF7BFFE012039
-:10544000FFF77EFE0020054908800548047004F03F
-:105450007F00012801D1FBF7AFFC10BD54000020F4
-:105460005801002010B504462046FCF78BFF10BD04
-:1054700010B506490648016103218182083000F019
-:105480000BF84FF4FA700349088010BD700100203A
-:10549000580100205200002070B5044608480068FA
-:1054A000C078802805D0A189A068FEF747FA054694
-:1054B00002E00025FFF756FB284600F003F870BD18
-:1054C0004800002070B504460CB1032000E0002025
-:1054D000054629460148FFF72FFA70BD5801002004
-:1054E00010B50320FFF7EEFF002010BD10B50446F5
-:1054F0002046FDF76FF910BD00BFFEE7002114E064
-:10550000084608220BE00B4B1B68034023B10A4BF3
-:105510001B6883EA500000E04008531EDAB2002AFC
-:10552000F1DC064B43F82100491C054B1B689942EE
-:10553000E6D37047DC000020E00000208026002039
-:10554000D000002002E008C8121F08C1002AFAD1CA
-:1055500070477047002001E001C1121F002AFBD1F3
-:105560007047000008B501210820FEF7C5FC0320A4
-:105570008DF8020014208DF803004FF48060ADF820
-:10558000000069460D48FDF7A4F903208DF80200DC
-:105590004FF40060ADF8000014208DF80300694658
-:1055A0000648FDF796F94FF480610448FDF766FA66
-:1055B0004FF400610148FDF761FA08BD000C01409D
-:1055C000022800DB70470121024A02F8301000BFB8
-:1055D000F8E70000FC000020022803DA074911F870
-:1055E000301001B970470121044A02F8301000213F
-:1055F00002EBC002517000BFF4E70000FC00002085
-:105600000146022908DA064810F8310020B10448A2
-:1056100010F83100032801D1002070470120FCE779
-:10562000FC00002010B5FFF79DFF10BD2DE9F041F3
-:1056300007460C461646FDF789FBA020FDF758FBF0
-:10564000FDF7B2FB00B130E0A046E11704EB1161B9
-:10565000C1F30720FDF74CFBFDF7A6FB00B124E0EA
-:10566000E0B2FDF745FBFDF79FFB00B11DE0FDF744
-:105670006DFBA120FDF73CFBFDF796FB00B114E0AC
-:1056800000250BE0711EA94201D0012100E000219C
-:105690000846FDF703FB7855681C85B2B542F1DB7F
-:1056A000FDF76EFB0120BDE8F081FDF769FB0020EE
-:1056B000F9E70000014802490860704700F0002047
-:1056C0002800002003480068006810B1002001494C
-:1056D0000860704728000020002001E0411C88B2CB
-:1056E0003C28FBDB7047000086B0FEF799FEFAF716
-:1056F000E7FDFEF75DFE01A8FEF70EFCFEF78BFB53
-:10570000FEF7C6FAFFF78EFFFBF7C0FBFAF736FE8F
-:105710004FF400712548FDF7AFF9FBF7B7FBFBF736
-:10572000C1FE41E0FEF7EAFE21480078012805D1DC
-:1057300000201F49087000F03DF835E01C48407813
-:10574000012803D100201A4948702DE018488078BC
-:10575000012805D1002016498870FFF745FD23E098
-:105760001348C078012803D100201149C8701BE0FC
-:105770000F480079012803D100200D49087113E07A
-:105780000B484079012803D10020094948710BE0FA
-:105790000748C079012807D100200549C8714FF496
-:1057A00000710248FDF768F9BCE70000000C0140F9
-:1057B0000C01002010B5FBF7DDFB10BD000102035A
-:1057C00004050607080C10141820304000010203DD
-:1057D0000405060708090909090A0A0A0A0B0B0B3E
-:1057E0000B0C0C0C0C0D0D0D0D0D0D0D0D0E0E0EEC
-:1057F0000E0E0E0E0E0E0E0E0E0E0E0E0E0F0F0FC6
-:105800000F0F0F0F0F0F0F0F0F0F0F0F0F39323139
-:10581000343830312D4446303200000000000000A2
-:105820000056480012566E00000056480012566E90
-:1058300000000001170B10001B0700000008040007
-:105840000000020000000000000000000000000056
-:10585000292E0008180100200B070000FF07000098
-:1058600000000800DF070000FF070000000008003C
-:105870002D010000FF0700000000080000000000EC
-:105880000000000000000000000000000000000018
-:10589000000000000206031000000000A9470008F5
-:1058A0000206031000000000A148000803060300E0
-:1058B00000000000414B0008060501000000000048
-:1058C000355100080303031000000000694600087A
-:1058D0001402010001000000ED540008060501005B
-:1058E00000000000754B00080B02010001000000E1
-:1058F0004D4B0008FF020100010000006554000844
-:105900000102010001000000594B000802060310CB
-:1059100000000000FD510008020303100000000019
-:1059200075470008000000000000000000000000B3
-:10593000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77
-:105940000001FFFFFFFFFFFFFFFFFFFFFFFFFFFF64
-:10595000FFFF02FFFFFFFF0304FFFFFFFFFF05FF45
-:10596000FF06FFFF07FF0809FFFFFFFFFFFF0AFF1A
-:10597000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF37
-:10598000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF27
-:10599000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF17
-:1059A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF07
-:1059B000FFFFFFFFFF0B000094F100003D150020EA
-:1059C00009010000FFFF000095F10000B500002074
-:1059D00006010000FFFF000093F10000B00000206E
-:1059E00005010000FFFF00008CF1000046150020BB
-:1059F00013010000FFFF000080F1000034150020BB
-:105A000009010000FFFF0000DD160008FD16000878
-:105A1000BD16000815170008191700083E53E17B52
-:105A2000405A000800000020FC0000004455000817
-:105A30003C5B0008FC000020AC310000545500081D
-:105A40000000000001020304010203040607080924
-:105A50000204060800A24A04000000000000000042
-:105A6000010203040607080900000000000000000E
-:105A70000000000000000000000000000000000026
-:105A80000000000000000000000000000000000016
-:105A90000000000000000000000000000000000006
-:105AA00000000000000000000000000018010020BD
-:105AB000D5490008F5490008C55400088149000887
-:105AC000E1540008814700080000000000000000C9
-:105AD00000000000000000000000000000000000C6
-:105AE00000000000000000000000000000000000B6
-:105AF00000000000000000000000000000000000A6
-:105B00000000000000000000000000000000000095
-:105B1000000100000800000000000000000000007C
-:105B20000000000000000000000000000000000075
-:0C5B300000000000000000000000000069
-:04000005080001519D
-:00000001FF
diff --git a/boot_project/Objects/boot.htm b/boot_project/Objects/boot.htm
deleted file mode 100644
index 062cea8..0000000
--- a/boot_project/Objects/boot.htm
+++ /dev/null
@@ -1,1916 +0,0 @@
-
-
-Static Call Graph - [.\Objects\boot.axf]
-
-Static Call Graph for image .\Objects\boot.axf
-
#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Tue Nov 05 09:42:11 2024
-
-
Maximum Stack Usage = 384 bytes + Unknown(Cycles, Untraceable Function Pointers)
-Call chain for Maximum Stack Depth:
-CAN2_RX1_IRQHandler ⇒ APP_CAN_FifoMessageReceive ⇒ APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
-Mutually Recursive functions
-
ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
-
-
-
-Function Pointers
-
- - ADC1_2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_RX0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_TX_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_RX0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_RX1_IRQHandler from can2.o(i.CAN2_RX1_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_SCE_IRQHandler from can2.o(i.CAN2_SCE_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_TX_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel6_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel7_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- Diag_Read_ECUSoftwareCode_F193 from diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F193) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_ECUSoftwareCode_F194 from diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F194) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_ECUSoftwareCode_F195 from diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F195) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_F18C from diag_eeprom_c301.o(i.Diag_Read_F18C) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_FBLVersionInformation from diag_eeprom_c301.o(i.Diag_Read_FBLVersionInformation) referenced from diag_appl_c301.o(.constdata)
-
- ETH_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- ETH_WKUP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI9_5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- ISO15765_DrvConfirmation from iso15765-2.o(i.ISO15765_DrvConfirmation) referenced from canconfig_c301.o(.constdata)
-
- MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- OTG_FS_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- OTG_FS_WKUP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- PVD_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- RCC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- RTCAlarm_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- RTC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- Reset_Handler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SPI3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- SysTick_Handler from dev_sys.o(i.SysTick_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_cl.o(.text)
-
- TAMPER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_BRK_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_UP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM6_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM7_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- UART4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- UART5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- USART1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- USART2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- USART3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- Uds_CommunicationControl from uds.o(i.Uds_CommunicationControl) referenced from canconfig_c301.o(.constdata)
-
- Uds_ControlDTCSetting from uds.o(i.Uds_ControlDTCSetting) referenced from canconfig_c301.o(.constdata)
-
- Uds_CopyToCAN from uds.o(i.Uds_CopyToCAN) referenced from iso15765-2_entry.o(.data)
-
- Uds_DiagControlSession from uds.o(i.Uds_DiagControlSession) referenced from canconfig_c301.o(.constdata)
-
- Uds_ECUReset from uds.o(i.Uds_ECUReset) referenced from canconfig_c301.o(.constdata)
-
- Uds_PhysFuncGetBuffer from uds.o(i.Uds_PhysFuncGetBuffer) referenced from iso15765-2_entry.o(.data)
-
- Uds_PhysReqInd from uds.o(i.Uds_PhysReqInd) referenced from iso15765-2_entry.o(.data)
-
- Uds_PhysRxErrorIndication from uds.o(i.Uds_PhysRxErrorIndication) referenced from iso15765-2_entry.o(.data)
-
- Uds_ReadDataByIdentifier from uds.o(i.Uds_ReadDataByIdentifier) referenced from canconfig_c301.o(.constdata)
-
- Uds_RequestDownload from uds.o(i.Uds_RequestDownload) referenced from canconfig_c301.o(.constdata)
-
- Uds_RequestTransferExit from uds.o(i.Uds_RequestTransferExit) referenced from canconfig_c301.o(.constdata)
-
- Uds_RoutineControl from uds.o(i.Uds_RoutineControl) referenced from canconfig_c301.o(.constdata)
-
- Uds_SecurityAccess from uds.o(i.Uds_SecurityAccess) referenced from canconfig_c301.o(.constdata)
-
- Uds_TesterPresent from uds.o(i.Uds_TesterPresent) referenced from canconfig_c301.o(.constdata)
-
- Uds_TransferData from uds.o(i.Uds_TransferData) referenced from canconfig_c301.o(.constdata)
-
- Uds_TxConfirmation from uds.o(i.Uds_TxConfirmation) referenced from iso15765-2_entry.o(.data)
-
- Uds_TxErrorIndication from uds.o(i.Uds_TxErrorIndication) referenced from iso15765-2_entry.o(.data)
-
- Uds_WriteDataByIdentifier from uds.o(i.Uds_WriteDataByIdentifier) referenced from canconfig_c301.o(.constdata)
-
- UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_cl.o(.text)
-
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
-
-
__get_PSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__set_PSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__get_MSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__set_MSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text))
-
[Called By]
-
-__REV16 (Thumb, 4 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__REVSH (Thumb, 4 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
-
-CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-__aeabi_memcpy (Thumb, 36 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED)
-
-
__aeabi_memcpy4 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text))
-
[Called By]
-
-__aeabi_memcpy8 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED)
-
-
__aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
[Called By]
- >> _memset$wrapper
-
- >> __aeabi_memclr
-
-
-__aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
__aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
__aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
[Calls]
-
-__aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
-
[Called By]
- >> CAN2_RX1_IRQHandler
-
- >> IF_CAN_CopyDataAndStartTx
-
-
-__aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
_memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
-
[Calls]
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
APP_CAN_FifoMessageReceive (Thumb, 72 bytes, Stack size 32 bytes, app_can.o(i.APP_CAN_FifoMessageReceive))
-
[Stack]
- Max Depth = 352
- Call Chain = APP_CAN_FifoMessageReceive ⇒ APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> APP_CAN_MessageTypeHandle
-
-
[Called By]
-
-BSP_BKP_Init (Thumb, 20 bytes, Stack size 8 bytes, main.o(i.BSP_BKP_Init))
-
[Stack]
- Max Depth = 8
- Call Chain = BSP_BKP_Init
-
-
[Calls]- >> RCC_APB1PeriphClockCmd
-
- >> PWR_BackupAccessCmd
-
-
[Called By]
-
-BSP_vSystemReset (Thumb, 30 bytes, Stack size 0 bytes, app_can.o(i.BSP_vSystemReset))
-
[Called By]
- >> Uds_TimerTask
-
- >> Can_Task
-
-
-BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-Bzip2_Finish (Thumb, 12 bytes, Stack size 0 bytes, uds_sa_c301.o(i.Bzip2_Finish))
-
[Called By]
- >> Diag_RequestTransferExit
-
-
-Bzip2_Init (Thumb, 26 bytes, Stack size 4 bytes, uds_sa_c301.o(i.Bzip2_Init))
-
[Stack]
- Max Depth = 4
- Call Chain = Bzip2_Init
-
-
[Calls]
-
[Called By]- >> Diag_RequestDownload
-
-
-Bzip2_Start (Thumb, 10 bytes, Stack size 0 bytes, uds_sa_c301.o(i.Bzip2_Start))
-
[Called By]
- >> Diag_RequestDownload
-
-
-Bzip2_Update (Thumb, 44 bytes, Stack size 12 bytes, uds_sa_c301.o(i.Bzip2_Update))
-
[Stack]
- Max Depth = 12
- Call Chain = Bzip2_Update
-
-
[Called By]
-
-CAN2_Mode_Init (Thumb, 308 bytes, Stack size 40 bytes, can2.o(i.CAN2_Mode_Init))
-
[Stack]
- Max Depth = 64
- Call Chain = CAN2_Mode_Init ⇒ GPIO_Init
-
-
[Calls]- >> CAN_Init
-
- >> CAN_ITConfig
-
- >> CAN_FilterInit
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_APB1PeriphClockCmd
-
- >> GPIO_Init
-
- >> NVIC_Init
-
- >> can_bus_open_hook
-
-
[Called By]
-
-CAN2_RX1_IRQHandler (Thumb, 44 bytes, Stack size 32 bytes, can2.o(i.CAN2_RX1_IRQHandler))
-
[Stack]
- Max Depth = 384
- Call Chain = CAN2_RX1_IRQHandler ⇒ APP_CAN_FifoMessageReceive ⇒ APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_Receive
-
- >> APP_CAN_FifoMessageReceive
-
- >> can_bus_ready_hook
-
- >> __aeabi_memclr4
-
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
-
-CAN2_SCE_IRQHandler (Thumb, 186 bytes, Stack size 8 bytes, can2.o(i.CAN2_SCE_IRQHandler))
-
[Stack]
- Max Depth = 24
- Call Chain = CAN2_SCE_IRQHandler ⇒ CAN_GetITStatus
-
-
[Calls]- >> CAN_GetITStatus
-
- >> CAN_GetFlagStatus
-
- >> CAN_DeInit
-
- >> CAN_ClearITPendingBit
-
- >> CAN_ClearFlag
-
- >> TickOut
-
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
-
-CAN_ClearFlag (Thumb, 52 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ClearFlag))
-
[Called By]
-
-CAN_ClearITPendingBit (Thumb, 162 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ClearITPendingBit))
-
[Called By]
-
-CAN_DeInit (Thumb, 50 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_DeInit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_DeInit
-
-
[Calls]- >> RCC_APB1PeriphResetCmd
-
-
[Called By]
-
-CAN_FilterInit (Thumb, 258 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_FilterInit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_FilterInit
-
-
[Called By]
-
-CAN_GetFlagStatus (Thumb, 120 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_GetFlagStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_GetFlagStatus
-
-
[Called By]
-
-CAN_GetITStatus (Thumb, 284 bytes, Stack size 16 bytes, stm32f10x_can.o(i.CAN_GetITStatus))
-
[Stack]
- Max Depth = 16
- Call Chain = CAN_GetITStatus
-
-
[Calls]
-
[Called By]
-
-CAN_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ITConfig))
-
[Called By]
-
-CAN_Init (Thumb, 276 bytes, Stack size 12 bytes, stm32f10x_can.o(i.CAN_Init))
-
[Stack]
- Max Depth = 12
- Call Chain = CAN_Init
-
-
[Called By]
-
-CAN_Receive (Thumb, 240 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_Receive))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Receive
-
-
[Called By]
-
-CAN_Transmit (Thumb, 294 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_Transmit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Transmit
-
-
[Called By]
-
-CAN_TransmitStatus (Thumb, 138 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_TransmitStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_TransmitStatus
-
-
[Called By]
-
-Can2_Send_Message (Thumb, 96 bytes, Stack size 48 bytes, can2.o(i.Can2_Send_Message))
-
[Stack]
- Max Depth = 56
- Call Chain = Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
- >> can_bus_send_ready
-
- >> __aeabi_memcpy4
-
-
[Called By]
-
-CanExt_CanTransShutdown (Thumb, 10 bytes, Stack size 8 bytes, app_can.o(i.CanExt_CanTransShutdown))
-
[Stack]
- Max Depth = 16
- Call Chain = CanExt_CanTransShutdown ⇒ CanTrans_GoToSleep
-
-
[Calls]
-
[Called By]
-
-CanTask_BusErrorDetection (Thumb, 2 bytes, Stack size 0 bytes, app_can.o(i.CanTask_BusErrorDetection))
-
[Called By]
- >> CanTask_TimerProcess
-
-
-CanTask_FBLInit (Thumb, 196 bytes, Stack size 0 bytes, app_can.o(i.CanTask_FBLInit))
-
[Called By]
- >> Uds_TransSessionType
-
- >> CanTask_InitProcess
-
-
-CanTask_GetSaRandom (Thumb, 6 bytes, Stack size 0 bytes, app_can.o(i.CanTask_GetSaRandom))
-
[Called By]
-
-CanTask_InitProcess (Thumb, 80 bytes, Stack size 8 bytes, app_can.o(i.CanTask_InitProcess))
-
[Stack]
- Max Depth = 32
- Call Chain = CanTask_InitProcess ⇒ ISO15765_InitPowerOn ⇒ ISO15765_Init ⇒ ISO15765_TxInit
-
-
[Calls]- >> IF_CAN_IsOnLine
-
- >> CanTrans_Init
-
- >> ISO15765_InitPowerOn
-
- >> CanTask_FBLInit
-
- >> Uds_PowerOnInit
-
- >> IF_CAN_InitLoaclStatus
-
-
[Called By]
-
-CanTask_IsAppBeenErased (Thumb, 40 bytes, Stack size 0 bytes, app_can.o(i.CanTask_IsAppBeenErased))
-
[Called By]
-
-CanTask_SetStayInBootFlagValue (Thumb, 6 bytes, Stack size 0 bytes, app_can.o(i.CanTask_SetStayInBootFlagValue))
-
[Called By]
- >> Uds_DiagControlSession
-
- >> Uds_SetState
-
-
-CanTask_UdsStateProcess (Thumb, 16 bytes, Stack size 8 bytes, app_can.o(i.CanTask_UdsStateProcess))
-
[Stack]
- Max Depth = 112
- Call Chain = CanTask_UdsStateProcess ⇒ Uds_StateTask ⇒ Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> uds_SysTick_Process_1ms
-
-
-CanTrans_GoToNormal (Thumb, 38 bytes, Stack size 8 bytes, can_transceiver.o(i.CanTrans_GoToNormal))
-
[Stack]
- Max Depth = 8
- Call Chain = CanTrans_GoToNormal
-
-
[Calls]
-
[Called By]
-
-CanTrans_GoToSleep (Thumb, 50 bytes, Stack size 8 bytes, can_transceiver.o(i.CanTrans_GoToSleep))
-
[Stack]
- Max Depth = 8
- Call Chain = CanTrans_GoToSleep
-
-
[Calls]- >> GPIO_SetBits
-
- >> GPIO_ResetBits
-
- >> CanTrans_Delay
-
-
[Called By]- >> CanExt_CanTransShutdown
-
-
-CanTrans_Init (Thumb, 10 bytes, Stack size 8 bytes, can_transceiver.o(i.CanTrans_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = CanTrans_Init ⇒ CanTrans_GoToNormal
-
-
[Calls]
-
[Called By]
-
-Can_Task (Thumb, 68 bytes, Stack size 8 bytes, app_can.o(i.Can_Task))
-
[Stack]
- Max Depth = 320
- Call Chain = Can_Task ⇒ CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> BSP_vSystemReset
-
- >> CanExt_CanTransShutdown
-
- >> CanTask_TimerProcess
-
-
[Called By]- >> Uds_SysTick_Process_10ms
-
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-Diag_AppDataInit (Thumb, 8 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_AppDataInit))
-
[Called By]
- >> Uds_PowerOnInit
-
- >> Uds_DiagControlSession
-
-
-Diag_CheckTransmitSequence (Thumb, 20 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_CheckTransmitSequence))
-
[Stack]
- Max Depth = 16
- Call Chain = Diag_CheckTransmitSequence
-
-
[Calls]
-
[Called By]
-
-Diag_CheckValidApp1 (Thumb, 54 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_CheckValidApp1))
-
[Stack]
- Max Depth = 64
- Call Chain = Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> Diag_CheckValidApplication
-
- >> Uds_SetState
-
-
-Diag_CheckValidApplication (Thumb, 24 bytes, Stack size 8 bytes, diag_appl_c301.o(i.Diag_CheckValidApplication))
-
[Stack]
- Max Depth = 72
- Call Chain = Diag_CheckValidApplication ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]
-
-Diag_CheckVerifyUpgradePacket (Thumb, 22 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CheckVerifyUpgradePacket))
-
[Called By]
-
-Diag_CheckWriteDIDRange (Thumb, 48 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CheckWriteDIDRange))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
-
-Diag_ClrAPP1UpdateMark (Thumb, 72 bytes, Stack size 16 bytes, diag_eeprom_c301.o(i.Diag_ClrAPP1UpdateMark))
-
[Stack]
- Max Depth = 16
- Call Chain = Diag_ClrAPP1UpdateMark
-
-
[Calls]- >> flashdnit
-
- >> flashInit
-
-
[Called By]
-
-Diag_ClrEepromUpdateMark (Thumb, 20 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_ClrEepromUpdateMark))
-
[Called By]
-
-Diag_CommunicationControl (Thumb, 178 bytes, Stack size 24 bytes, diag_appl_c301.o(i.Diag_CommunicationControl))
-
[Stack]
- Max Depth = 32
- Call Chain = Diag_CommunicationControl ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_CommEnable
-
- >> Diag_CommDisable
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_CommunicationControl
-
-
-Diag_ControlDTCSetting (Thumb, 100 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_ControlDTCSetting))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_ControlDTCSetting ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_ControlDTCSetting
-
-
-Diag_DataCalcCRC (Thumb, 96 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_DataCalcCRC))
-
[Stack]
- Max Depth = 16
- Call Chain = Diag_DataCalcCRC
-
-
[Called By]
-
-Diag_DataProgram (Thumb, 94 bytes, Stack size 24 bytes, diag_appl_c301.o(i.Diag_DataProgram))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_DataProgram
-
-
[Calls]- >> flashdnit
-
- >> flashInit
-
-
[Called By]
-
-Diag_EcuReset (Thumb, 132 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_EcuReset))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_EcuReset ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]
-
-Diag_FlashCalcCRC (Thumb, 118 bytes, Stack size 40 bytes, diag_appl_c301.o(i.Diag_FlashCalcCRC))
-
[Stack]
- Max Depth = 328
- Call Chain = Diag_FlashCalcCRC ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Uds_ForceTransmitResPending
-
-
[Called By]- >> Diag_RequestTransferExit
-
-
-Diag_HndUpdataEV (Thumb, 2 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_HndUpdataEV))
-
[Called By]
-
-Diag_MemCopy (Thumb, 22 bytes, Stack size 8 bytes, diag_eeprom_c301.o(i.Diag_MemCopy))
-
[Stack]
- Max Depth = 8
- Call Chain = Diag_MemCopy
-
-
[Called By]- >> Diag_WriteDataByIdentifier
-
- >> Uds_ContextTask
-
-
-Diag_MemCpy (Thumb, 20 bytes, Stack size 8 bytes, diag_appl_c301.o(i.Diag_MemCpy))
-
[Stack]
- Max Depth = 8
- Call Chain = Diag_MemCpy
-
-
[Called By]
-
-Diag_ProgramFailedDataInit (Thumb, 120 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_ProgramFailedDataInit))
-
[Called By]
-
-Diag_RamWrite (Thumb, 20 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_RamWrite))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_RamWrite ⇒ Diag_MemCpy
-
-
[Calls]
-
[Called By]
-
-Diag_ReadDataByIdentifier (Thumb, 340 bytes, Stack size 144 bytes, diag_appl_c301.o(i.Diag_ReadDataByIdentifier))
-
[Stack]
- Max Depth = 152
- Call Chain = Diag_ReadDataByIdentifier ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetNRC
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_ReadDataByIdentifier
-
-
-Diag_Read_ECUSoftwareCode_F193 (Thumb, 22 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F193))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_ECUSoftwareCode_F194 (Thumb, 22 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F194))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_ECUSoftwareCode_F195 (Thumb, 20 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F195))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_F18C (Thumb, 2 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_F18C))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_FBLVersionInformation (Thumb, 22 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_FBLVersionInformation))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_RequestDownload (Thumb, 832 bytes, Stack size 32 bytes, diag_appl_c301.o(i.Diag_RequestDownload))
-
[Stack]
- Max Depth = 40
- Call Chain = Diag_RequestDownload ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Bzip2_Start
-
- >> Bzip2_Init
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetNRC
-
-
[Called By]
-
-Diag_RequestEraseFlash (Thumb, 72 bytes, Stack size 24 bytes, diag_appl_c301.o(i.Diag_RequestEraseFlash))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_RequestEraseFlash
-
-
[Calls]- >> flashdnit
-
- >> flashInit
-
-
[Called By]
-
-Diag_RequestTransferExit (Thumb, 298 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_RequestTransferExit))
-
[Stack]
- Max Depth = 344
- Call Chain = Diag_RequestTransferExit ⇒ Diag_FlashCalcCRC ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Bzip2_Finish
-
- >> Diag_FlashCalcCRC
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
-
[Called By]- >> Uds_RequestTransferExit
-
-
-Diag_RoutineControl (Thumb, 882 bytes, Stack size 48 bytes, diag_appl_c301.o(i.Diag_RoutineControl))
-
[Stack]
- Max Depth = 336
- Call Chain = Diag_RoutineControl ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Diag_RequestEraseFlash
-
- >> Diag_CheckVerifyUpgradePacket
-
- >> Diag_CheckValidApplication
-
- >> Diag_CheckTransmitSequence
-
- >> Diag_SetEepromAppErasureMark
-
- >> Diag_ClrEepromUpdateMark
-
- >> Diag_ClrAPP1UpdateMark
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetCurSessionAccessStatus
-
- >> Uds_ForceTransmitResPending
-
- >> Uds_CheckAdrrType
-
-
[Called By]
-
-Diag_SecurityAccess (Thumb, 968 bytes, Stack size 40 bytes, diag_appl_c301.o(i.Diag_SecurityAccess))
-
[Stack]
- Max Depth = 64
- Call Chain = Diag_SecurityAccess ⇒ SA_Random
-
-
[Calls]- >> SA_GenerateKeyFBL
-
- >> SA_GenerateKey
-
- >> SA_Compare
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetProtect
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetCurSessionState
-
- >> Uds_CheckAdrrType
-
- >> SA_Random
-
-
[Called By]
-
-Diag_SetEepromAppErasureMark (Thumb, 20 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_SetEepromAppErasureMark))
-
[Called By]
-
-Diag_TransferData (Thumb, 1098 bytes, Stack size 32 bytes, diag_appl_c301.o(i.Diag_TransferData))
-
[Stack]
- Max Depth = 56
- Call Chain = Diag_TransferData ⇒ Diag_RamWrite ⇒ Diag_MemCpy
-
-
[Calls]- >> Bzip2_Update
-
- >> Diag_RamWrite
-
- >> Diag_ProgramFailedDataInit
-
- >> Diag_DataProgram
-
- >> Diag_DataCalcCRC
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
-
[Called By]
-
-Diag_WriteDataByIdentifier (Thumb, 238 bytes, Stack size 32 bytes, diag_appl_c301.o(i.Diag_WriteDataByIdentifier))
-
[Stack]
- Max Depth = 40
- Call Chain = Diag_WriteDataByIdentifier ⇒ Diag_MemCopy
-
-
[Calls]- >> EED_WriteDID
-
- >> Diag_CheckWriteDIDRange
-
- >> Diag_MemCopy
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_WriteDataByIdentifier
-
-
-EED_WriteDID (Thumb, 6 bytes, Stack size 0 bytes, app_can.o(i.EED_WriteDID))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
-
-GPIO_Init (Thumb, 278 bytes, Stack size 24 bytes, stm32f10x_gpio.o(i.GPIO_Init))
-
[Stack]
- Max Depth = 24
- Call Chain = GPIO_Init
-
-
[Called By]- >> CAN2_Mode_Init
-
- >> bsp_InitI2C
-
- >> LED_Init
-
-
-GPIO_PinRemapConfig (Thumb, 138 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_PinRemapConfig))
-
[Stack]
- Max Depth = 20
- Call Chain = GPIO_PinRemapConfig
-
-
[Called By]
-
-GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits))
-
[Called By]
- >> LED_Init
-
- >> CanTrans_GoToSleep
-
- >> main
-
-
-GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits))
-
[Called By]
- >> bsp_InitI2C
-
- >> LED_Init
-
- >> CanTrans_GoToSleep
-
- >> CanTrans_GoToNormal
-
-
-GetCrc32Chk (Thumb, 6 bytes, Stack size 0 bytes, uds_sa_c301.o(i.GetCrc32Chk))
-
[Called By]
- >> Diag_CheckTransmitSequence
-
-
-HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-IF_CAN_CancelTransmitMsg (Thumb, 2 bytes, Stack size 0 bytes, app_can.o(i.IF_CAN_CancelTransmitMsg))
-
[Called By]
- >> ISO15765_Precopy
-
- >> ISO15765_TxInit
-
- >> ISO15765_RxInit
-
-
-IF_CAN_InitLoaclStatus (Thumb, 24 bytes, Stack size 8 bytes, app_can.o(i.IF_CAN_InitLoaclStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = IF_CAN_InitLoaclStatus
-
-
[Calls]
-
[Called By]
-
-IF_CAN_IsOnLine (Thumb, 20 bytes, Stack size 0 bytes, app_can.o(i.IF_CAN_IsOnLine))
-
[Called By]
- >> IF_CAN_InitLoaclStatus
-
- >> CanTask_InitProcess
-
-
-IF_CAN_SendCanData (Thumb, 160 bytes, Stack size 64 bytes, app_can.o(i.IF_CAN_SendCanData))
-
[Stack]
- Max Depth = 120
- Call Chain = IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> IF_CAN_CopyDataAndStartTx
-
-
-IF_CAN_TransmitMsg (Thumb, 46 bytes, Stack size 24 bytes, app_can.o(i.IF_CAN_TransmitMsg))
-
[Stack]
- Max Depth = 264
- Call Chain = IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> IF_CAN_CopyDataAndStartTx
-
-
[Called By]- >> ISO15765_CanTransmitMsg
-
- >> ISO15765_CanTransmitMsgWithDlc
-
-
-IIC_Ack (Thumb, 52 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Ack))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Ack
-
-
[Calls]
-
[Called By]
-
-IIC_NAck (Thumb, 42 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_NAck))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_NAck
-
-
[Calls]
-
[Called By]
-
-IIC_Read_Byte (Thumb, 80 bytes, Stack size 16 bytes, bsp_i2c_gpio.o(i.IIC_Read_Byte))
-
[Stack]
- Max Depth = 24
- Call Chain = IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> IIC_NAck
-
- >> IIC_Ack
-
- >> i2c_Delay
-
-
[Called By]
-
-IIC_Send_Byte (Thumb, 88 bytes, Stack size 16 bytes, bsp_i2c_gpio.o(i.IIC_Send_Byte))
-
[Stack]
- Max Depth = 16
- Call Chain = IIC_Send_Byte
-
-
[Calls]
-
[Called By]
-
-IIC_Start (Thumb, 48 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Start))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Start
-
-
[Calls]
-
[Called By]
-
-IIC_Stop (Thumb, 36 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Stop))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Stop
-
-
[Calls]
-
[Called By]
-
-IIC_Wait_Ack (Thumb, 62 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Wait_Ack))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Wait_Ack
-
-
[Calls]
-
[Called By]
-
-ISO15765_CanTransmitMsg (Thumb, 26 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_CanTransmitMsg))
-
[Stack]
- Max Depth = 272
- Call Chain = ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> ISO15765_TxStateTask
-
- >> ISO15765_RxStateTask
-
-
-ISO15765_CanTransmitMsgWithDlc (Thumb, 26 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_CanTransmitMsgWithDlc))
-
[Stack]
- Max Depth = 280
- Call Chain = ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> Uds_ForceTransmitResPending
-
-
-ISO15765_DrvConfirmation (Thumb, 22 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_DrvConfirmation))
-
[Stack]
- Max Depth = 16
- Call Chain = ISO15765_DrvConfirmation ⇒ ISO15765_TxFinishProcess
-
-
[Calls]- >> ISO15765_TxFinishProcess
-
- >> ISO15765_RxFinishProcess
-
-
[Called By]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-ISO15765_InitPowerOn (Thumb, 24 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_InitPowerOn))
-
[Stack]
- Max Depth = 24
- Call Chain = ISO15765_InitPowerOn ⇒ ISO15765_Init ⇒ ISO15765_TxInit
-
-
[Calls]
-
[Called By]
-
-ISO15765_Precopy (Thumb, 1534 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_Precopy))
-
[Stack]
- Max Depth = 304
- Call Chain = ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> IF_CAN_CancelTransmitMsg
-
- >> ISO15765_DrvConfirmation
-
- >> ISO15765_TxInit
-
- >> ISO15765_RxStateTask
-
- >> ISO15765_RxInit
-
- >> ISO15765_RxResetBus
-
-
[Called By]- >> APP_CAN_MessageTypeHandle
-
-
-ISO15765_RxResetBus (Thumb, 8 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_RxResetBus))
-
[Stack]
- Max Depth = 16
- Call Chain = ISO15765_RxResetBus ⇒ ISO15765_RxInit
-
-
[Calls]
-
[Called By]- >> ISO15765_Precopy
-
- >> Uds_PhysReqInd
-
-
-ISO15765_RxSetFCStatus (Thumb, 6 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_RxSetFCStatus))
-
[Called By]
- >> Uds_PhysFuncGetBuffer
-
-
-ISO15765_Task (Thumb, 12 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_Task))
-
[Stack]
- Max Depth = 304
- Call Chain = ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_TxTask
-
- >> ISO15765_RxTask
-
-
[Called By]- >> CanTask_TimerProcess
-
-
-ISO15765_Transmit (Thumb, 98 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_Transmit))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_Transmit
-
-
[Called By]- >> Uds_TransmitResponse
-
-
-LED_Init (Thumb, 368 bytes, Stack size 8 bytes, led.o(i.LED_Init))
-
[Stack]
- Max Depth = 32
- Call Chain = LED_Init ⇒ GPIO_Init
-
-
[Calls]- >> RCC_APB2PeriphClockCmd
-
- >> GPIO_SetBits
-
- >> GPIO_ResetBits
-
- >> GPIO_PinRemapConfig
-
- >> GPIO_Init
-
-
[Called By]
-
-MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-NVIC_Configuration (Thumb, 12 bytes, Stack size 8 bytes, dev_sys.o(i.NVIC_Configuration))
-
[Stack]
- Max Depth = 8
- Call Chain = NVIC_Configuration
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
-
[Called By]
-
-NVIC_Init (Thumb, 100 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = NVIC_Init
-
-
[Called By]
-
-NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
-
[Called By]
-
-PWR_BackupAccessCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_pwr.o(i.PWR_BackupAccessCmd))
-
[Called By]
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd))
-
[Called By]
- >> CAN2_Mode_Init
-
- >> BSP_BKP_Init
-
-
-RCC_APB1PeriphResetCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd))
-
[Called By]
-
-RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd))
-
[Called By]
- >> CAN2_Mode_Init
-
- >> bsp_InitI2C
-
- >> LED_Init
-
-
-RCC_GetClocksFreq (Thumb, 374 bytes, Stack size 24 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq))
-
[Stack]
- Max Depth = 24
- Call Chain = RCC_GetClocksFreq
-
-
[Called By]
-
-SA_Compare (Thumb, 36 bytes, Stack size 16 bytes, uds_sa_c301.o(i.SA_Compare))
-
[Stack]
- Max Depth = 16
- Call Chain = SA_Compare
-
-
[Called By]
-
-SA_GenerateKey (Thumb, 132 bytes, Stack size 20 bytes, uds_sa_c301.o(i.SA_GenerateKey))
-
[Stack]
- Max Depth = 20
- Call Chain = SA_GenerateKey
-
-
[Called By]
-
-SA_GenerateKeyFBL (Thumb, 130 bytes, Stack size 20 bytes, uds_sa_c301.o(i.SA_GenerateKeyFBL))
-
[Stack]
- Max Depth = 20
- Call Chain = SA_GenerateKeyFBL
-
-
[Called By]
-
-SA_Random (Thumb, 92 bytes, Stack size 24 bytes, uds_sa_c301.o(i.SA_Random))
-
[Stack]
- Max Depth = 24
- Call Chain = SA_Random
-
-
[Calls]
-
[Called By]
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SysTick_Handler (Thumb, 64 bytes, Stack size 0 bytes, dev_sys.o(i.SysTick_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SysTick_Init (Thumb, 92 bytes, Stack size 12 bytes, dev_sys.o(i.SysTick_Init))
-
[Stack]
- Max Depth = 12
- Call Chain = SysTick_Init
-
-
[Called By]
-
-SystemInit (Thumb, 92 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(.text)
-
-TickOut (Thumb, 58 bytes, Stack size 0 bytes, dev_sys.o(i.TickOut))
-
[Called By]
-
-TimeTaskDispatch_Flag (Thumb, 318 bytes, Stack size 0 bytes, dev_sys.o(i.TimeTaskDispatch_Flag))
-
[Called By]
-
-UDS_ForcPendingReset (Thumb, 12 bytes, Stack size 0 bytes, uds.o(i.UDS_ForcPendingReset))
-
[Called By]
- >> Uds_ProcessFinished
-
- >> Uds_PowerOnInit
-
-
-Uds_CheckAdrrType (Thumb, 16 bytes, Stack size 0 bytes, uds.o(i.Uds_CheckAdrrType))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
-
-Uds_CommunicationControl (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_CommunicationControl))
-
[Stack]
- Max Depth = 40
- Call Chain = Uds_CommunicationControl ⇒ Diag_CommunicationControl ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_CommunicationControl
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ControlDTCSetting (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_ControlDTCSetting))
-
[Stack]
- Max Depth = 32
- Call Chain = Uds_ControlDTCSetting ⇒ Diag_ControlDTCSetting ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_ControlDTCSetting
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_CopyToCAN (Thumb, 22 bytes, Stack size 16 bytes, uds.o(i.Uds_CopyToCAN))
-
[Stack]
- Max Depth = 16
- Call Chain = Uds_CopyToCAN
-
-
[Calls]
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_DiagControlSession (Thumb, 232 bytes, Stack size 24 bytes, uds.o(i.Uds_DiagControlSession))
-
[Stack]
- Max Depth = 104
- Call Chain = Uds_DiagControlSession ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> Diag_AppDataInit
-
- >> CanTask_SetStayInBootFlagValue
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
- >> Uds_SetState
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ECUReset (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_ECUReset))
-
[Stack]
- Max Depth = 32
- Call Chain = Uds_ECUReset ⇒ Diag_EcuReset ⇒ Uds_ProcessFinished
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ForceTransmitResPending (Thumb, 42 bytes, Stack size 8 bytes, uds.o(i.Uds_ForceTransmitResPending))
-
[Stack]
- Max Depth = 288
- Call Chain = Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_CanTransmitMsgWithDlc
-
-
[Called By]- >> Diag_FlashCalcCRC
-
- >> Diag_RoutineControl
-
-
-Uds_GetCurSessionAccessStatus (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_GetCurSessionAccessStatus))
-
[Called By]
- >> Diag_RoutineControl
-
- >> CanTask_ReprogrammingCheck
-
-
-Uds_GetCurSessionState (Thumb, 10 bytes, Stack size 0 bytes, uds.o(i.Uds_GetCurSessionState))
-
[Called By]
- >> Diag_SecurityAccess
-
- >> Uds_TransSessionType
-
- >> Uds_SetState
-
- >> Uds_Scheduler
-
-
-Uds_GetNRC (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_GetNRC))
-
[Called By]
- >> Diag_RequestDownload
-
- >> Diag_ReadDataByIdentifier
-
-
-Uds_PhysFuncGetBuffer (Thumb, 78 bytes, Stack size 24 bytes, uds.o(i.Uds_PhysFuncGetBuffer))
-
[Stack]
- Max Depth = 24
- Call Chain = Uds_PhysFuncGetBuffer
-
-
[Calls]- >> ISO15765_RxSetFCStatus
-
- >> Uds_NetLayerStartRec
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_PhysReqInd (Thumb, 24 bytes, Stack size 8 bytes, uds.o(i.Uds_PhysReqInd))
-
[Stack]
- Max Depth = 24
- Call Chain = Uds_PhysReqInd ⇒ ISO15765_RxResetBus ⇒ ISO15765_RxInit
-
-
[Calls]- >> ISO15765_RxResetBus
-
- >> Uds_NetLayerEndOfRec
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_PhysRxErrorIndication (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_PhysRxErrorIndication))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_PhysRxErrorIndication
-
-
[Calls]- >> Uds_NetLayerEndOfRec
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_PowerOnInit (Thumb, 128 bytes, Stack size 8 bytes, uds.o(i.Uds_PowerOnInit))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_PowerOnInit
-
-
[Calls]- >> Diag_AppDataInit
-
- >> UDS_ForcPendingReset
-
-
[Called By]
-
-Uds_ProcessFinished (Thumb, 94 bytes, Stack size 8 bytes, uds.o(i.Uds_ProcessFinished))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_ProcessFinished
-
-
[Calls]- >> UDS_ForcPendingReset
-
-
[Called By]- >> Diag_WriteDataByIdentifier
-
- >> Diag_TransferData
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_RequestTransferExit
-
- >> Diag_RequestDownload
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
- >> Uds_Scheduler
-
-
-Uds_ReadDataByIdentifier (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_ReadDataByIdentifier))
-
[Stack]
- Max Depth = 160
- Call Chain = Uds_ReadDataByIdentifier ⇒ Diag_ReadDataByIdentifier ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_ReadDataByIdentifier
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_RequestDownload (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_RequestDownload))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_RequestDownload ⇒ Diag_RequestDownload ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_RequestDownload
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_RequestTransferExit (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_RequestTransferExit))
-
[Stack]
- Max Depth = 352
- Call Chain = Uds_RequestTransferExit ⇒ Diag_RequestTransferExit ⇒ Diag_FlashCalcCRC ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Diag_RequestTransferExit
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ResponseEnable (Thumb, 10 bytes, Stack size 0 bytes, uds.o(i.Uds_ResponseEnable))
-
[Called By]
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
- >> Uds_TransmitResponse
-
-
-Uds_RoutineControl (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_RoutineControl))
-
[Stack]
- Max Depth = 344
- Call Chain = Uds_RoutineControl ⇒ Diag_RoutineControl ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_SecurityAccess (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_SecurityAccess))
-
[Stack]
- Max Depth = 72
- Call Chain = Uds_SecurityAccess ⇒ Diag_SecurityAccess ⇒ SA_Random
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_SetNRC (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetNRC))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
- >> Diag_TransferData
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_RequestTransferExit
-
- >> Diag_RequestDownload
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
-
-Uds_SetProtect (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetProtect))
-
[Called By]
-
-Uds_SetSupFuncEnableFlag (Thumb, 8 bytes, Stack size 0 bytes, uds.o(i.Uds_SetSupFuncEnableFlag))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
-
-Uds_StateTask (Thumb, 14 bytes, Stack size 8 bytes, uds.o(i.Uds_StateTask))
-
[Stack]
- Max Depth = 104
- Call Chain = Uds_StateTask ⇒ Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> CanTask_UdsStateProcess
-
-
-Uds_Task (Thumb, 8 bytes, Stack size 8 bytes, uds.o(i.Uds_Task))
-
[Stack]
- Max Depth = 96
- Call Chain = Uds_Task ⇒ Uds_TimerTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> CanTask_TimerProcess
-
-
-Uds_TesterPresent (Thumb, 84 bytes, Stack size 16 bytes, uds.o(i.Uds_TesterPresent))
-
[Stack]
- Max Depth = 24
- Call Chain = Uds_TesterPresent ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_TransSessionType (Thumb, 76 bytes, Stack size 8 bytes, uds.o(i.Uds_TransSessionType))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_TransSessionType
-
-
[Calls]- >> CanTask_FBLInit
-
- >> Uds_GetCurSessionState
-
- >> Uds_SetStateSessionAccess
-
- >> Uds_SetFlashProtect
-
-
[Called By]
-
-Uds_TransferData (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_TransferData))
-
[Stack]
- Max Depth = 64
- Call Chain = Uds_TransferData ⇒ Diag_TransferData ⇒ Diag_RamWrite ⇒ Diag_MemCpy
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_TxConfirmation (Thumb, 24 bytes, Stack size 16 bytes, uds.o(i.Uds_TxConfirmation))
-
[Stack]
- Max Depth = 32
- Call Chain = Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]- >> Uds_NetLayerEndOfTrans
-
-
[Called By]- >> Uds_TxErrorIndication
-
- >> Uds_TransmitResponse
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_TxErrorIndication (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_TxErrorIndication))
-
[Stack]
- Max Depth = 40
- Call Chain = Uds_TxErrorIndication ⇒ Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_WriteDataByIdentifier (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_WriteDataByIdentifier))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_WriteDataByIdentifier ⇒ Diag_WriteDataByIdentifier ⇒ Diag_MemCopy
-
-
[Calls]- >> Diag_WriteDataByIdentifier
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-_Bzip2_InitTable (Thumb, 56 bytes, Stack size 0 bytes, uds_sa_c301.o(i._Bzip2_InitTable))
-
[Called By]
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
bsp_InitI2C (Thumb, 88 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.bsp_InitI2C))
-
[Stack]
- Max Depth = 32
- Call Chain = bsp_InitI2C ⇒ GPIO_Init
-
-
[Calls]- >> RCC_APB2PeriphClockCmd
-
- >> GPIO_SetBits
-
- >> GPIO_Init
-
-
[Called By]
-
-ee_Init (Thumb, 8 bytes, Stack size 8 bytes, 24cxx.o(i.ee_Init))
-
[Stack]
- Max Depth = 40
- Call Chain = ee_Init ⇒ bsp_InitI2C ⇒ GPIO_Init
-
-
[Calls]
-
[Called By]
-
-ee_ReadBytes (Thumb, 134 bytes, Stack size 24 bytes, 24cxx.o(i.ee_ReadBytes))
-
[Stack]
- Max Depth = 48
- Call Chain = ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> IIC_Wait_Ack
-
- >> IIC_Stop
-
- >> IIC_Start
-
- >> IIC_Send_Byte
-
- >> IIC_Read_Byte
-
-
[Called By]
-
-flashInit (Thumb, 8 bytes, Stack size 0 bytes, dev_flashapi.o(i.flashInit))
-
[Called By]
- >> Diag_RequestEraseFlash
-
- >> Diag_DataProgram
-
- >> Diag_ClrAPP1UpdateMark
-
-
-flashdnit (Thumb, 16 bytes, Stack size 0 bytes, dev_flashapi.o(i.flashdnit))
-
[Called By]
- >> Diag_RequestEraseFlash
-
- >> Diag_DataProgram
-
- >> Diag_ClrAPP1UpdateMark
-
-
-main (Thumb, 194 bytes, Stack size 24 bytes, main.o(i.main))
-
[Stack]
- Max Depth = 352
- Call Chain = main ⇒ Uds_SysTick_Process_10ms ⇒ Can_Task ⇒ CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> RCC_GetClocksFreq
-
- >> GPIO_ResetBits
-
- >> SystemInit
-
- >> TimeTaskDispatch_Flag
-
- >> SysTick_Init
-
- >> NVIC_Configuration
-
- >> CAN2_Mode_Init
-
- >> ee_Init
-
- >> LED_Init
-
- >> Diag_HndUpdataEV
-
- >> CanTask_InitProcess
-
- >> BSP_BKP_Init
-
- >> uds_SysTick_Process_1ms
-
- >> Uds_SysTick_Process_10ms
-
-
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-Local Symbols
-
-CheckITStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CheckITStatus))
-
[Called By]
-
-i2c_Delay (Thumb, 14 bytes, Stack size 0 bytes, bsp_i2c_gpio.o(i.i2c_Delay))
-
[Called By]
- >> IIC_NAck
-
- >> IIC_Ack
-
- >> IIC_Wait_Ack
-
- >> IIC_Stop
-
- >> IIC_Start
-
- >> IIC_Send_Byte
-
- >> IIC_Read_Byte
-
-
-can_bus_open_hook (Thumb, 18 bytes, Stack size 0 bytes, can2.o(i.can_bus_open_hook))
-
[Called By]
-
-can_bus_ready_hook (Thumb, 34 bytes, Stack size 0 bytes, can2.o(i.can_bus_ready_hook))
-
[Called By]
-
-can_bus_send_ready (Thumb, 32 bytes, Stack size 0 bytes, can2.o(i.can_bus_send_ready))
-
[Called By]
-
-SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
-SetSysClockTo72 (Thumb, 266 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
-
-
[Called By]
-
-Uds_ContextTask (Thumb, 226 bytes, Stack size 16 bytes, uds.o(i.Uds_ContextTask))
-
[Stack]
- Max Depth = 96
- Call Chain = Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> Diag_MemCopy
-
- >> Uds_TransmitResponse
-
- >> Uds_SetState
-
- >> Uds_Scheduler
-
-
[Called By]
-
-Uds_CopyToCanMemCpy (Thumb, 16 bytes, Stack size 0 bytes, uds.o(i.Uds_CopyToCanMemCpy))
-
[Called By]
-
-Uds_NetLayerEndOfRec (Thumb, 44 bytes, Stack size 0 bytes, uds.o(i.Uds_NetLayerEndOfRec))
-
[Called By]
- >> Uds_PhysRxErrorIndication
-
- >> Uds_PhysReqInd
-
-
-Uds_NetLayerEndOfTrans (Thumb, 44 bytes, Stack size 16 bytes, uds.o(i.Uds_NetLayerEndOfTrans))
-
[Stack]
- Max Depth = 16
- Call Chain = Uds_NetLayerEndOfTrans
-
-
[Calls]
-
[Called By]
-
-Uds_NetLayerStartRec (Thumb, 24 bytes, Stack size 0 bytes, uds.o(i.Uds_NetLayerStartRec))
-
[Called By]
- >> Uds_PhysFuncGetBuffer
-
-
-Uds_PostProcessing (Thumb, 24 bytes, Stack size 0 bytes, uds.o(i.Uds_PostProcessing))
-
[Called By]
- >> Uds_NetLayerEndOfTrans
-
-
-Uds_Scheduler (Thumb, 1436 bytes, Stack size 40 bytes, uds.o(i.Uds_Scheduler))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_Scheduler ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_ProcessFinished
-
- >> Uds_GetCurSessionState
-
-
[Called By]
-
-Uds_SetFlashProtect (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetFlashProtect))
-
[Called By]
- >> Uds_TransSessionType
-
-
-Uds_SetState (Thumb, 78 bytes, Stack size 16 bytes, uds.o(i.Uds_SetState))
-
[Stack]
- Max Depth = 80
- Call Chain = Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> Diag_CheckValidApp1
-
- >> CanTask_SetStayInBootFlagValue
-
- >> CanTask_IsAppBeenErased
-
- >> Uds_TransSessionType
-
- >> Uds_GetCurSessionState
-
-
[Called By]- >> Uds_DiagControlSession
-
- >> Uds_TimerTask
-
- >> Uds_ContextTask
-
-
-Uds_SetStateSessionAccess (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetStateSessionAccess))
-
[Called By]
- >> Uds_TransSessionType
-
-
-Uds_TimerTask (Thumb, 406 bytes, Stack size 8 bytes, uds.o(i.Uds_TimerTask))
-
[Stack]
- Max Depth = 88
- Call Chain = Uds_TimerTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> BSP_vSystemReset
-
- >> Uds_TransmitResPending
-
- >> Uds_SetState
-
-
[Called By]
-
-Uds_TransmitResPending (Thumb, 28 bytes, Stack size 8 bytes, uds.o(i.Uds_TransmitResPending))
-
[Stack]
- Max Depth = 56
- Call Chain = Uds_TransmitResPending ⇒ Uds_TransmitResponse ⇒ Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]- >> Uds_TransmitResponse
-
-
[Called By]
-
-Uds_TransmitResponse (Thumb, 40 bytes, Stack size 16 bytes, uds.o(i.Uds_TransmitResponse))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_TransmitResponse ⇒ Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]- >> ISO15765_Transmit
-
- >> Uds_TxConfirmation
-
- >> Uds_ResponseEnable
-
-
[Called By]- >> Uds_TransmitResPending
-
- >> Uds_ContextTask
-
-
-ISO15765_Init (Thumb, 12 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = ISO15765_Init ⇒ ISO15765_TxInit
-
-
[Calls]- >> ISO15765_TxInit
-
- >> ISO15765_RxInit
-
-
[Called By]- >> ISO15765_InitPowerOn
-
-
-ISO15765_PreCanTransmit (Thumb, 486 bytes, Stack size 24 bytes, iso15765-2.o(i.ISO15765_PreCanTransmit))
-
[Stack]
- Max Depth = 24
- Call Chain = ISO15765_PreCanTransmit
-
-
[Calls]- >> ISO15765_SetOptimalDlc
-
-
[Called By]- >> ISO15765_TxStateTask
-
-
-ISO15765_PreTransmitClearCanDataPtr (Thumb, 22 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_PreTransmitClearCanDataPtr))
-
[Called By]
- >> ISO15765_TxStateTask
-
-
-ISO15765_RxFinishProcess (Thumb, 54 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_RxFinishProcess))
-
[Called By]
- >> ISO15765_DrvConfirmation
-
-
-ISO15765_RxInit (Thumb, 98 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_RxInit))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_RxInit
-
-
[Calls]- >> IF_CAN_CancelTransmitMsg
-
-
[Called By]- >> ISO15765_Precopy
-
- >> ISO15765_RxTask
-
- >> ISO15765_Init
-
- >> ISO15765_RxResetBus
-
-
-ISO15765_RxStateTask (Thumb, 226 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_RxStateTask))
-
[Stack]
- Max Depth = 288
- Call Chain = ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_CanTransmitMsg
-
-
[Called By]- >> ISO15765_Precopy
-
- >> ISO15765_RxTask
-
-
-ISO15765_RxTask (Thumb, 122 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_RxTask))
-
[Stack]
- Max Depth = 296
- Call Chain = ISO15765_RxTask ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_RxStateTask
-
- >> ISO15765_RxInit
-
-
[Called By]
-
-ISO15765_SetOptimalDlc (Thumb, 50 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_SetOptimalDlc))
-
[Called By]
- >> ISO15765_PreCanTransmit
-
-
-ISO15765_TransmitOfCF (Thumb, 72 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_TransmitOfCF))
-
[Called By]
-
-ISO15765_TxFinishProcess (Thumb, 126 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_TxFinishProcess))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_TxFinishProcess
-
-
[Called By]- >> ISO15765_DrvConfirmation
-
-
-ISO15765_TxInit (Thumb, 114 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_TxInit))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_TxInit
-
-
[Calls]- >> IF_CAN_CancelTransmitMsg
-
-
[Called By]- >> ISO15765_Precopy
-
- >> ISO15765_TxTask
-
- >> ISO15765_Init
-
-
-ISO15765_TxStateTask (Thumb, 232 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_TxStateTask))
-
[Stack]
- Max Depth = 288
- Call Chain = ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_CanTransmitMsg
-
- >> ISO15765_PreTransmitClearCanDataPtr
-
- >> ISO15765_PreCanTransmit
-
-
[Called By]
-
-ISO15765_TxTask (Thumb, 90 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_TxTask))
-
[Stack]
- Max Depth = 296
- Call Chain = ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_TxStateTask
-
- >> ISO15765_TxInit
-
- >> ISO15765_TransmitOfCF
-
-
[Called By]
-
-CanTrans_Delay (Thumb, 16 bytes, Stack size 0 bytes, can_transceiver.o(i.CanTrans_Delay))
-
[Called By]
-
-Diag_CommDisable (Thumb, 12 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CommDisable))
-
[Called By]
- >> Diag_CommunicationControl
-
-
-Diag_CommEnable (Thumb, 12 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CommEnable))
-
[Called By]
- >> Diag_CommunicationControl
-
-
-JumpToExecute (Thumb, 30 bytes, Stack size 8 bytes, main.o(i.JumpToExecute))
-
[Stack]
- Max Depth = 8
- Call Chain = JumpToExecute
-
-
[Calls]
-
[Called By]
-
-Sys_GotoApp (Thumb, 8 bytes, Stack size 8 bytes, main.o(i.Sys_GotoApp))
-
[Stack]
- Max Depth = 16
- Call Chain = Sys_GotoApp ⇒ JumpToExecute
-
-
[Calls]
-
[Called By]
-
-Task_RunToApp (Thumb, 44 bytes, Stack size 8 bytes, main.o(i.Task_RunToApp))
-
[Stack]
- Max Depth = 24
- Call Chain = Task_RunToApp ⇒ Sys_GotoApp ⇒ JumpToExecute
-
-
[Calls]
-
[Called By]- >> Uds_SysTick_Process_10ms
-
-
-Uds_SysTick_Process_10ms (Thumb, 12 bytes, Stack size 8 bytes, main.o(i.Uds_SysTick_Process_10ms))
-
[Stack]
- Max Depth = 328
- Call Chain = Uds_SysTick_Process_10ms ⇒ Can_Task ⇒ CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Can_Task
-
- >> Task_RunToApp
-
-
[Called By]
-
-uds_SysTick_Process_1ms (Thumb, 8 bytes, Stack size 8 bytes, main.o(i.uds_SysTick_Process_1ms))
-
[Stack]
- Max Depth = 120
- Call Chain = uds_SysTick_Process_1ms ⇒ CanTask_UdsStateProcess ⇒ Uds_StateTask ⇒ Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> CanTask_UdsStateProcess
-
-
[Called By]
-
-APP_CAN_MessageTypeHandle (Thumb, 92 bytes, Stack size 16 bytes, app_can.o(i.APP_CAN_MessageTypeHandle))
-
[Stack]
- Max Depth = 320
- Call Chain = APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> APP_CAN_FifoMessageReceive
-
-
-CanTask_ReprogrammingCheck (Thumb, 26 bytes, Stack size 8 bytes, app_can.o(i.CanTask_ReprogrammingCheck))
-
[Stack]
- Max Depth = 8
- Call Chain = CanTask_ReprogrammingCheck
-
-
[Calls]- >> Uds_GetCurSessionAccessStatus
-
-
[Called By]- >> CanTask_TimerProcess
-
-
-CanTask_SaRandomCounter (Thumb, 12 bytes, Stack size 0 bytes, app_can.o(i.CanTask_SaRandomCounter))
-
[Called By]
- >> CanTask_TimerProcess
-
-
-CanTask_TimerProcess (Thumb, 24 bytes, Stack size 8 bytes, app_can.o(i.CanTask_TimerProcess))
-
[Stack]
- Max Depth = 312
- Call Chain = CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_Task
-
- >> Uds_Task
-
- >> CanTask_BusErrorDetection
-
- >> CanTask_SaRandomCounter
-
- >> CanTask_ReprogrammingCheck
-
-
[Called By]
-
-IF_CAN_CopyDataAndStartTx (Thumb, 140 bytes, Stack size 120 bytes, app_can.o(i.IF_CAN_CopyDataAndStartTx))
-
[Stack]
- Max Depth = 240
- Call Chain = IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> __aeabi_memclr4
-
- >> IF_CAN_SendCanData
-
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/boot_project/Objects/boot.lnp b/boot_project/Objects/boot.lnp
deleted file mode 100644
index f072b65..0000000
--- a/boot_project/Objects/boot.lnp
+++ /dev/null
@@ -1,36 +0,0 @@
---cpu Cortex-M3
-".\objects\startup_stm32f10x_cl.o"
-".\objects\core_cm3.o"
-".\objects\misc.o"
-".\objects\stm32f10x_gpio.o"
-".\objects\stm32f10x_rcc.o"
-".\objects\stm32f10x_can.o"
-".\objects\stm32f10x_dma.o"
-".\objects\stm32f10x_flash.o"
-".\objects\stm32f10x_iwdg.o"
-".\objects\stm32f10x_pwr.o"
-".\objects\led.o"
-".\objects\24cxx.o"
-".\objects\bsp_i2c_gpio.o"
-".\objects\can2.o"
-".\objects\stm32f10x_it.o"
-".\objects\system_stm32f10x.o"
-".\objects\dev_flashapi.o"
-".\objects\dev_crc32.o"
-".\objects\dev_sys.o"
-".\objects\dev_eerom.o"
-".\objects\uds.o"
-".\objects\iso15765-2.o"
-".\objects\iso15765-2_entry.o"
-".\objects\can_transceiver.o"
-".\objects\diag_eeprom_c301.o"
-".\objects\canconfig_c301.o"
-".\objects\canctrl_c301.o"
-".\objects\diag_appl_c301.o"
-".\objects\uds_sa_c301.o"
-".\objects\main.o"
-".\objects\app_can.o"
---library_type=microlib --strict --scatter ".\link_sct\STM32F105Boot.sct"
---summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\boot.map" -o .\Objects\boot.axf
\ No newline at end of file
diff --git a/boot_project/Objects/diag_appl_hr.__i b/boot_project/Objects/diag_appl_hr.__i
deleted file mode 100644
index 3e0247a..0000000
--- a/boot_project/Objects/diag_appl_hr.__i
+++ /dev/null
@@ -1,6 +0,0 @@
---c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com\inc -I ..\boot_source\code_app\service\CanStack\canBus_hongri\inc -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
--I.\RTE\_hongri_boot
--IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
--IC:\Keil_v5\ARM\CMSIS\Include
--D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
--o .\objects\diag_appl_hr.o --omf_browse .\objects\diag_appl_hr.crf --depend .\objects\diag_appl_hr.d "..\boot_source\code_app\service\CanStack\canBus_hongri\src\Diag_Appl_hr.c"
\ No newline at end of file
diff --git a/boot_project/Objects/hongri_boot.axf b/boot_project/Objects/hongri_boot.axf
deleted file mode 100644
index 0565153..0000000
Binary files a/boot_project/Objects/hongri_boot.axf and /dev/null differ
diff --git a/boot_project/Objects/hongri_boot.build_log.htm b/boot_project/Objects/hongri_boot.build_log.htm
deleted file mode 100644
index 7a97e68..0000000
--- a/boot_project/Objects/hongri_boot.build_log.htm
+++ /dev/null
@@ -1,116 +0,0 @@
-
-
-
-µVision Build Log
-Tool Versions:
-IDE-Version: ¦ÌVision V5.25.2.0
-Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: Zachary Administrator, Zachary, LIC=TIVNB-2IHDY-01WP1-C2K2G-5HIE0-XG8NS
-
-Tool Versions:
-Toolchain: MDK-ARM Plus Version: 5.25.2.0
-Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
-C Compiler: Armcc.exe V5.06 update 6 (build 750)
-Assembler: Armasm.exe V5.06 update 6 (build 750)
-Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
-Library Manager: ArmAr.exe V5.06 update 6 (build 750)
-Hex Converter: FromElf.exe V5.06 update 6 (build 750)
-CPU DLL: SARMCM3.DLL V5.25.2.0
-Dialog DLL: DCM.DLL V1.17.1.0
-Target DLL: Segger\JL2CM3.dll V2.99.29.0
-Dialog DLL: TCM.DLL V1.35.1.0
-
-Project:
-E:\liudagui\project\HONGRI\code\boot_up\boot_project\hongri_boot.uvprojx
-Project File Date: 11/04/2024
-
-Output:
-*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
-Rebuild target 'hongri_boot'
-assembling startup_stm32f10x_cl.s...
-compiling stm32f10x_gpio.c...
-compiling misc.c...
-compiling stm32f10x_dma.c...
-compiling stm32f10x_iwdg.c...
-compiling stm32f10x_pwr.c...
-compiling stm32f10x_can.c...
-compiling stm32f10x_rcc.c...
-compiling led.c...
-compiling stm32f10x_flash.c...
-compiling 24cxx.c...
-compiling core_cm3.c...
-compiling bsp_i2c_gpio.c...
-compiling dev_eerom.c...
-compiling dev_crc32.c...
-compiling dev_flashApi.c...
-compiling stm32f10x_it.c...
-compiling system_stm32f10x.c...
-compiling dev_sys.c...
-compiling can2.c...
-compiling iso15765-2_entry.c...
-compiling Can_Transceiver.c...
-compiling iso15765-2.c...
-compiling Diag_Eeprom_C301.c...
-compiling UDS.c...
-compiling CanConfig_C301.c...
-compiling CanCtrl_C301.c...
-compiling UDS_SA_C301.c...
-..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c(48): warning: #177-D: function "BL_BE32_TO_MCU" was declared but never referenced
- static uint32_t BL_BE32_TO_MCU(uint8_t *pBuf)
-..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c: 1 warning, 0 errors
-compiling Diag_Appl_C301.c...
-..\boot_source\code_app\driver\inc\dev_eerom.h(32): warning: #1-D: last line of file ends without a newline
- /** EOF */
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(1329): warning: #177-D: variable "crc32" was declared but never referenced
- uint32_t crc32=0;
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2026): warning: #550-D: variable "CRC_16" was set but never used
- uint16_t CRC_16=0xFFFF;
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(2121): warning: #223-D: function "GetCrc32Chk" declared implicitly
- if(GetCrc32Chk() == transSequenceValue)
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c(289): warning: #177-D: function "Diag_ExtMemorySecFAAFlagSave" was declared but never referenced
- static void Diag_ExtMemorySecFAAFlagSave(uint8_t cnt)
-..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c: 5 warnings, 0 errors
-compiling main.c...
-..\boot_source\code_app\main\src\main.c(163): warning: #188-D: enumerated type mixed with another type
- RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP,ENABLE );//
-..\boot_source\code_app\main\src\main.c(164): warning: #188-D: enumerated type mixed with another type
- PWR_BackupAccessCmd(ENABLE);//
-..\boot_source\code_app\main\src\main.c(198): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_1MS = RESET;
-..\boot_source\code_app\main\src\main.c(207): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_5MS = RESET;
-..\boot_source\code_app\main\src\main.c(213): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_10MS = RESET;
-..\boot_source\code_app\main\src\main.c(222): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_20MS = RESET;
-..\boot_source\code_app\main\src\main.c(226): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_50MS = RESET;
-..\boot_source\code_app\main\src\main.c(230): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_100MS = RESET;
-..\boot_source\code_app\main\src\main.c(234): warning: #188-D: enumerated type mixed with another type
- TimeTaskData.F_Time_1000MS = RESET;
-..\boot_source\code_app\main\src\main.c(89): warning: #177-D: function "Task_RunToAppCheckValide" was declared but never referenced
- static uint8_t Task_RunToAppCheckValide(void)
-..\boot_source\code_app\main\src\main.c: 10 warnings, 0 errors
-compiling app_can.c...
-linking...
-Program Size: Code=22124 RO-data=980 RW-data=252 ZI-data=12716
-FromELF: creating hex file...
-".\Objects\hongri_boot.axf" - 0 Error(s), 16 Warning(s).
-
-Software Packages used:
-
-Package Vendor: Keil
- http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.1.0.pack
- Keil.STM32F1xx_DFP.2.1.0
- STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
-
-Collection of Component include folders:
- .\RTE\_hongri_boot
- C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-
-Collection of Component Files used:
-Build Time Elapsed: 00:00:06
-
-
-
diff --git a/boot_project/Objects/hongri_boot.hex b/boot_project/Objects/hongri_boot.hex
deleted file mode 100644
index 57be32b..0000000
--- a/boot_project/Objects/hongri_boot.hex
+++ /dev/null
@@ -1,1463 +0,0 @@
-:020000040800F2
-:10000000A832002085010008153E00088D2A00084E
-:10001000113E0008FD020008F9540008000000002D
-:10002000000000000000000000000000394200084D
-:100030006F10000800000000B53E00086143000892
-:100040009F0100089F0100089F0100089F01000810
-:100050009F0100089F0100089F0100089F01000800
-:100060009F0100089F0100089F0100089F010008F0
-:100070009F0100089F0100089F0100089F010008E0
-:100080009F0100089F0100089F0100089F010008D0
-:100090009F0100089F0100089F0100089F010008C0
-:1000A0009F0100089F0100089F0100089F010008B0
-:1000B0009F0100089F0100089F0100089F010008A0
-:1000C0009F0100089F0100089F0100089F01000890
-:1000D0009F0100089F0100089F0100089F01000880
-:1000E0009F0100089F0100089F0100080000000018
-:1000F0000000000000000000000000000000000000
-:1001000000000000000000009F0100089F0100089F
-:100110009F0100089F0100089F0100089F0100083F
-:100120009F0100089F0100089F0100089F0100082F
-:100130009F0100089F0100089F0100089F0100081F
-:100140009F010008B9040008E90400089F010008A5
-:10015000DFF80CD000F04CF800480047E9560008E2
-:10016000A8320020EFF30980704780F309887047B8
-:10017000EFF30880704780F30888704740BA7047F3
-:10018000C0BA70470648804706480047FEE7FEE7CA
-:10019000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE737
-:1001A000214400085101000840EA01039B0703D0E5
-:1001B00009E008C9121F08C0042AFAD203E011F8A6
-:1001C000013B00F8013B521EF9D27047D2B201E068
-:1001D00000F8012B491EFBD270470022F6E710B54C
-:1001E00013460A4604461946FFF7F0FF204610BDA5
-:1001F000064C074D06E0E06840F0010394E8070074
-:1002000098471034AC42F6D3FFF7A6FF205A0008F7
-:10021000405A00080FB470B5049D9DF81A000828D4
-:1002200002DD08208DF81A000C49049808609DF83A
-:100230001A008872002407E00DF11B00015D0748D9
-:100240000B300155601CC4B29DF81A00A042F3DCCB
-:10025000284600F005F870BC5DF814FB802A0020E9
-:1002600070B5044603254FF6D0702040B0F5806F7E
-:1002700004D1012500201149086010E040F2DF7030
-:10028000844203D040F20B70844204D10225002046
-:100290000A49086003E00325002008490860012D91
-:1002A00004D0022D03D0032D05D103E004E002F0B9
-:1002B000EBFE01E000E000BF00BF70BDF0000020D9
-:1002C00010B501214FF0C05003F0F6FD012003F0FE
-:1002D000EBFD10BD00BF0748006800F4E060064970
-:1002E0000843001D03490860BFF34F8F00BF00BFE4
-:1002F000FEE700000CED00E00000FA0500BFFEE79D
-:1003000002480068C043014908607047D8000020D7
-:1003100000B50648006838B901200549086005485D
-:100320000249086005F0EAF800BD0000E000002086
-:10033000DC0000202083B8ED4FF0FF300149086059
-:1003400070470000D800002030B503460C4609482D
-:100350000268002108E0605C5040C5B2064850F8D1
-:10036000250080EA1222491C9942F4D30148026018
-:10037000002030BDD80000208026002000B589B0C4
-:100380000121092003F0B8FD0121480603F094FD86
-:100390000121880603F090FD4FF40050ADF82000D5
-:1003A00003208DF8220018208DF8230008A940486A
-:1003B00002F08FFA4FF48050ADF8200048208DF8FD
-:1003C000230008A93A4802F084FA00208DF81A00A8
-:1003D00001208DF81B0000208DF81C008DF81D00F9
-:1003E0008DF81E008DF81F008DF8160001208DF885
-:1003F000170008208DF8180001208DF8190006203C
-:10040000ADF8140005A92B4800F0B9FA0E208DF8BC
-:100410000E0000208DF80F0001208DF81000002044
-:10042000ADF80400ADF80600ADF80800ADF80A001C
-:100430000120ADF80C008DF8110001A800F046F97C
-:10044000012210211B4800F091FA41208DF8000094
-:1004500001208DF8010000208DF8020001208DF8A8
-:100460000300684603F0DEFC012005F0A9F8012234
-:100470005102104800F07AFA012291020D4800F072
-:1004800075FA0122D1030B4800F070FA42208DF872
-:10049000000001208DF8010000208DF802000120ED
-:1004A0008DF80300684603F0BDFC002009B000BDD4
-:1004B000000C01400068004000B587B0012005F045
-:1004C0008BF802AA0121074800F0E3FA0698009091
-:1004D00002A80FC8FFF79EFE142102A8FFF77DFEB9
-:1004E00007B000BD0068004010B54FF400712D4802
-:1004F00000F0ACF9012820D12B492A4800F06AF914
-:10050000012815D100BF022808DA284911F8301057
-:1005100021B1264911F83010032900D104E002214D
-:10052000224A02F8301000BF1F491E4800F042F86E
-:100530004FF400711B4800F059F84FF480611948DE
-:1005400000F084F901282BD11749891C154800F0C7
-:1005500041F901281FD10124022C03DA134810F8B5
-:10056000340000B912E00320104901F8340001EB17
-:10057000C401081D002103F0A1FF1CB90C4800F0C4
-:1005800089F802E0074800F085F800BF0649891C99
-:10059000044800F00FF84FF48061024800F026F89C
-:1005A00010BD0000006800400200F010FC000020B8
-:1005B0000064004000220C4B994202D10023836169
-:1005C00011E0C1F3130201F000730BB1C2600AE045
-:1005D00001F080630BB1026105E001F000630BB133
-:1005E000826000E0426070477000F030B1F5007F3B
-:1005F0003AD00FDC202928D006DC01291CD00429A0
-:100600001DD0082940D11DE0402921D0B1F5807FBF
-:100610003AD126E0B1F5004F31D006DCB1F5806F5C
-:1006200025D0B1F5006F2FD124E0B1F5803F12D075
-:10063000B1F5003F28D111E0154A826025E008227B
-:10064000C26022E01022C2601FE0082202611CE0AA
-:100650001022026119E00822426016E01022426076
-:1006600013E00422426010E0042242600DE0042204
-:1006700042600AE0002282610422426005E000221A
-:1006800082610422426000E000BF00BF70470000AA
-:100690000101010010B504460B48844209D1012133
-:1006A000480603F019FC00214FF0007003F014FC21
-:1006B00008E00121880603F00FFC00214FF0806064
-:1006C00003F00AFC10BD00000064004010B50021DA
-:1006D000837A012202FA03F13D4A126842F00102D4
-:1006E0003B4B1A603A4A1C3212688A43384B1C331F
-:1006F0001A60027BCAB9364A0C3212688A43344BFC
-:100700000C331A604288C38842EA0343304A4032BD
-:10071000847A42F834300288838842EA03432C4AC0
-:100720004032847A02EBC4025360027B012A19D161
-:10073000274A0C3212680A43254B0C331A60428850
-:10074000038842EA0343224A4032847A42F8343032
-:10075000C288838842EA03431D4A4032847A02EB0E
-:10076000C4025360C27A3AB9194A121D12688A4308
-:10077000174B1B1D1A6006E0154A121D12680A432A
-:10078000134B1B1D1A60028932B9114A14321268C8
-:100790008A430F4B14331A600289012A06D10C4A8E
-:1007A000143212680A430A4B14331A60427B012A3E
-:1007B00006D1074A1C3212680A43054B1C331A60E3
-:1007C000034A126822F00102014B1A6010BD0000BA
-:1007D0000066004010B50246002001F4700343B1EA
-:1007E0009369C1F3130423400BB101202DE00020D5
-:1007F0002BE001F0807343B15368C1F3130423402D
-:100800000BB1012021E000201FE001F0006343B1A3
-:100810009368C1F3130423400BB1012015E00020BD
-:1008200013E001F0007343B1D368C1F31304234014
-:100830000BB1012009E0002007E01369C1F31304A4
-:1008400023400BB1012000E0002010BD70B504462C
-:100850000D46002660692840002871D0B5F5807FDC
-:100860005CD010DC082D35D006DC012D20D0022D07
-:1008700024D0042D72D127E0102D31D0202D35D079
-:10088000402D6BD138E0B5F5004F60D009DCB5F5EF
-:10089000007F49D0B5F5806F4CD0B5F5006F5DD1C4
-:1008A0004FE0B5F5803F2DD0B5F5003F56D12FE094
-:1008B000A0682D4900F0D2FB064651E0E068032114
-:1008C00000F0CCFB06464BE0E068082100F0C6FBD8
-:1008D000064645E0E068102100F0C0FB06463FE018
-:1008E0002069032100F0BAFB064639E0206908219F
-:1008F00000F0B4FB064633E02069102100F0AEFBA7
-:1009000006462DE06068082100F0A8FB064627E0B7
-:100910006068102100F0A2FB064621E0A0690121D9
-:1009200000F09CFB06461BE0A069022100F096FB4C
-:10093000064615E0A069042100F090FB06460FE092
-:100940000FE0A069702100F089FB064608E06068AE
-:10095000042100F083FB064602E0FFE7002600BF0B
-:1009600000E00026304670BD010101001AB1436964
-:100970000B43436102E043698B434361704730B5E9
-:10098000024600200023146824F002041460146856
-:1009900044F00104146000E05B1C546804F001049E
-:1009A0001CB94FF6FF74A342F6D1546804F0010459
-:1009B0000CB900206CE08C79012C04D1146844F04F
-:1009C0008004146003E0146824F080041460CC797F
-:1009D000012C04D1146844F04004146003E014684E
-:1009E00024F0400414600C7A012C04D1146844F003
-:1009F0002004146003E0146824F0200414604C7A8E
-:100A0000012C04D1146844F01004146003E014684D
-:100A100024F0100414608C7A012C04D1146844F082
-:100A20000804146003E0146824F008041460CC7A0D
-:100A3000012C04D1146844F00404146003E0146829
-:100A400024F0040414608C78A407CD7844EA05648B
-:100A50000D7944EA05444D7944EA05540D886D1E2C
-:100A60002C43D461146824F001041460002300E0D6
-:100A70005B1C546804F001041CB14FF6FF74A342E0
-:100A8000F6D1546804F001040CB1002000E001200C
-:100A900030BD10B500F5D87303EB01131B6803F0EC
-:100AA00004031372137A53B900F5D87303EB0113DF
-:100AB0001B6840F2FF7404EA5353136009E000F529
-:100AC000D87303EB01131B686FF0604404EAD3038F
-:100AD000536000F5D87303EB01131B6803F00203A6
-:100AE000537200F5D87303EB01135B6803F00F0337
-:100AF000937200F5D87303EB01135B681B0AD37480
-:100B000000F5D87303EB01139B68D37200F5D8731B
-:100B100003EB01139B681C0A147300F5D87303EBF5
-:100B200001139B681C0C547300F5D87303EB01137D
-:100B30009B681B0E937300F5D87303EB0113DB68FE
-:100B4000D37300F5D87303EB0113DB681C0A14742C
-:100B500000F5D87303EB0113DB681C0C547400F52B
-:100B6000D87303EB0113DB681B0E937421B9C368C0
-:100B700043F02003C36003E0036943F020030361F3
-:100B800010BD10B502460020936803F08063B3F1F6
-:100B9000806F00D110E0936803F00063B3F1006F41
-:100BA00001D1012008E0936803F08053B3F1805F26
-:100BB00001D1022000E00420042874D002F5C073A3
-:100BC00003EB00131B6803F0010402F5C07303EB91
-:100BD00000131C600B7A7BB94B7A0C8843EA4453B0
-:100BE00002F5C07404EB00142468234302F5C074BA
-:100BF00004EB0014236010E00B7A4C6843EAC40352
-:100C00004C7A234302F5C07404EB00142468234398
-:100C100002F5C07404EB001423608B7A03F00F0319
-:100C20008B7202F5C07303EB00135B6823F00F04B3
-:100C300002F5C07303EB00135C6002F5C07303EBB5
-:100C400000135B688C7A234302F5C07404EB001434
-:100C500063608B7B1C064B7B44EA03440B7B44EABA
-:100C60000323CC7A234302F5C07404EB0014A36081
-:100C70008B7C1C064B7C44EA03440B7C44EA032334
-:100C8000CC7B234302F5C07404EB0014E36002F54F
-:100C9000C07303EB00131B6843F0010402F5C0733B
-:100CA00003EB00131C6010BD10B50246002321B1F8
-:100CB000012907D002290FD109E090681D4C00EAF4
-:100CC00004030BE090681C4C00EA040306E0906803
-:100CD0001A4C00EA040301E0002300BF00BF184CD7
-:100CE000181BA34216D007DC83B16FF08060184454
-:100CF00070B1022818D111E0B0F5007F10D0114C6E
-:100D0000204448B1B0F5003F0ED10BE002230DE0C6
-:100D100000230BE0002309E0002307E0012305E0A6
-:100D2000012303E0012301E0002300BF00BFD8B28C
-:100D300010BD0000030000040003000800000310C1
-:100D4000000100080001FFF70FB430B585B00024A2
-:100D5000142208A96846FFF727FA012004F050FC86
-:100D600020B9012005B030BC5DF814FB69460E487F
-:100D7000FFF707FF0546002401E0601C84B2012054
-:100D800004F03EFC40B129460748FFF78DFF18B933
-:100D900040F6FF708442F0DB40F6FF70844201DBD6
-:100DA0000120DFE70020DDE70068004010B50020EB
-:100DB00000F00AF910BD70473048407820F040003C
-:100DC0002E4948700846407820F0200048700846B8
-:100DD000407820F0100048700846807820F00F001E
-:100DE00088700846807820F0F00088700846007807
-:100DF00020F0010008700846007820F00800087014
-:100E00000846007820F0040008700846007820F0BA
-:100E1000020008700846007820F02000087008469C
-:100E2000007820F0100008700846007820F080005C
-:100E300008700846007820F04000087008464078A6
-:100E400020F0010048700846407820F00200487009
-:100E50000846407820F00400487000204871C1F82E
-:100E6000F000C1F8F400C1F8F800C1F8FC00C1F8C6
-:100E7000EC004FF6FF70A1F8E600704770150020F7
-:100E80000148007870470000F600002010B50024EB
-:100E9000002012490870124908701249087012495E
-:100EA000087072B6FFF788FF00240DE000200F499C
-:100EB00008550F4908552146012001F041FE204602
-:100EC00001F030FE601CC4B2012CEFDB00F09AF898
-:100ED00001F0BEFF03F0A8FD62B610BDF7000020D0
-:100EE000F6000020F8000020F5000020F9000020A6
-:100EF000FA0000200949097842290DD107494978AB
-:100F00004F2909D105498978452905D10349C9786F
-:100F1000522901D1012000E0002070478E000020FE
-:100F200010B506480078002806DD04480078401E09
-:100F30000249087003F0D2FC10BD0000F800002048
-:100F400002480078401C014908707047F6000020F4
-:100F50000149087070470000F500002010B5FFF748
-:100F60002AFF02F0E5FC04F045F9FFF7E9FFFFF77F
-:100F7000D7FF10BD10B503480078012801D104F057
-:100F800029F910BDF700002000204FF4AC7000E0FC
-:100F9000401E0028FCD1704710B50446012C00DB30
-:100FA00010BD44B98021064801F068FD10210548B4
-:100FB00001F064FD00E000BF00BF00BFF0E70000EB
-:100FC00000100140000C014010B50446012C00DB6C
-:100FD00010BD74B91021094801F04EFD8021084868
-:100FE00001F04CFDFFF7D0FF8021054801F044FDE2
-:100FF00000E000BF00BF00BFEAE70000000C0140B6
-:101000000010014010B50020FFF7C6FF10BD000022
-:1010100010B500240F480078012817D1FFF79EFF74
-:101020000D480068B0F5FA6F0AD3FFF7BFFE06E07F
-:10103000601C84B2B4F5487F01DBFFF74BF9F7E79A
-:1010400005480068401C0449086002E0012001498D
-:10105000087010BDF7000020F000002002460020BC
-:1010600002EA01030BB1012000E000207047704745
-:101070000120014908707047C200002070B5044685
-:10108000012501F0FDFCA04200D10025284670BDDD
-:1010900038B502221021684604F0C8FA0546012D31
-:1010A00001D0002038BD002409E01DF8040006A18D
-:1010B000095D884201D00020F4E7601CC4B2022C14
-:1010C000F3DB0120EEE700004852000010B50548B0
-:1010D000807800F00F00012802D1FFF7D9FF10BD82
-:1010E0000120FCE77015002000200549897801F0F7
-:1010F0000F01012901D1012000E00120704700000B
-:101100007015002002460020A2F57143843B73B99C
-:101110000B78632B01DD012008E04B783C2B01DDCF
-:10112000012003E08B781F2B00DD012000E000BFD1
-:1011300000BF704770B5054604F0BCFA72B68B2D3F
-:1011400006D10E480068012182680D48904711E0E1
-:101150002E2D0FD1002404E0AA200A490855601C56
-:10116000C4B2082CF8DB054800680822054943682A
-:101170000348984704F0A6FA62B670BD2800002024
-:1011800000380208A8000020002004E0AA21034A39
-:101190001154411CC8B20828F8DB70478E000020AB
-:1011A000012802D0022800D000BF7047012802D0D9
-:1011B000022800D000BF70472DE9F0410446207995
-:1011C000401CC6B22068477820688578032E03DC6F
-:1011D000132003F0BBFF44E037B1032F1BD0802F57
-:1011E00003D0832F2ED117E000BF042E05D013208B
-:1011F00003F0ACFF03F0B6FC32E00220A081032D27
-:1012000001DC012D03DA312003F0A0FF02E02846C3
-:10121000FFF7CCFF24E000BF042E05D0132003F01D
-:1012200095FF03F09FFC1BE00220A081032D01DC51
-:10123000012D03DA312003F089FF02E02846FFF791
-:10124000AFFF0DE003F006FA18B1802003F0BCFFF9
-:1012500005E0002003F0B8FF122003F077FF00BF85
-:1012600000BF03F037FCBDE8F08170B5044620797B
-:10127000401CC6B22068457825F08005022E03D1B7
-:10128000132003F063FF1FE0012D02D0022D0CD1CB
-:1012900000E000BF032E05D0132003F057FF03F03A
-:1012A00061FC10E00220A0810DE003F0D3F918B139
-:1012B000802003F089FF05E0002003F085FF122065
-:1012C00003F044FF00BF00BF03F004FC70BD00004A
-:1012D00070B50246002028E00D5C2B02002421E0BE
-:1012E000134DB5F8E6505D4005F4004555B1104D7D
-:1012F000B5F8E65041F2210686EA45050C4EA6F8FF
-:10130000E65009E00A4DB5F8E6504FF6FF7606EADA
-:101310004505074EA6F8E6504FF6FF7505EA43036C
-:10132000651CECB2082CDBDB401C9042D4D370BDB2
-:10133000701500202DE9F04105460E4617464FF086
-:1013400000081448807800F00F00012805D01148EB
-:10135000807800F00F00022814D104F0ABF972B6C7
-:101360000D4800683A46314643682846984780460B
-:1013700004F0A8F962B6B8F1000F01D1002402E030
-:10138000012400E0012414B90120BDE8F08100200F
-:10139000FBE70000701500202800002070B504460F
-:1013A0002079401CC5B22068467826F08006022DC0
-:1013B00003DC132003F0CAFE2FE0012E02D0032E1F
-:1013C0001CD10DE0032D05D0132003F0BFFE03F068
-:1013D000C9FB04E00220A0810A20114908701BE02B
-:1013E000032D05D0132003F0B1FE03F0BBFB04E096
-:1013F0000220A0810A200B4908700DE003F02AF9B1
-:1014000018B1802003F0E0FE05E0002003F0DCFED0
-:10141000122003F09BFE00BF00BF03F05BFB70BD1A
-:1014200044000020450000202DE9F05F06460F46ED
-:1014300090461B48B0F8E84000252BE04FF44830B8
-:10144000B5FBF0F100FB115010B9404603F02EFA45
-:1014500017F805B04FEA0B294FF0000A16E084EAAE
-:10146000090000F4004028B141F2210080EA440064
-:1014700084B203E04FF6FF7000EA44044FF6FF70B9
-:1014800000EA49090AF1010000F0FF0ABAF1080F69
-:10149000E5DB6D1CB542D1D32046BDE8F09F0000CE
-:1014A00070150020704710B50346002003E01C5C57
-:1014B0000C54441CE0B29042F9DB10BD10B5034659
-:1014C000002002E00C5C1C54401C9042FAD310BD7A
-:1014D0001D48007820F0800080301B4908700020F3
-:1014E000C1F8EC00C1F8F400C1F8F00008464078FB
-:1014F00020F0010048700846007820F002000870D3
-:101500000846007820F0040008700846007820F0B3
-:10151000200008700846007820F001000870084696
-:10152000007820F0080008700846407820F010008D
-:1015300048700846807820F00F0088700846807850
-:1015400020F0F000887070477015002070B50646D6
-:101550000C461546224629463046FFF7AFFF70BDC0
-:101560002DE9F04F9BB007464FF00008C34600241A
-:101570003879401C00F0FF0801201A90B8F1040FE0
-:101580000FD0B8F1060F0CD0B8F1080F09D0B8F1A0
-:101590000A0F06D0B8F10C0F03D0132003F0D6FDCC
-:1015A00083E04FF0010BBBF1050F01DD4FF0050BA0
-:1015B000012400255BE0012101EB45013868405C16
-:1015C0000DF804001DF804004FEA002A601CC4B2A4
-:1015D000022101EB45013868405C0DF804001DF85C
-:1015E000040040EA0A0A601CC4B2002019900026D8
-:1015F0002DE0304800EB06100088504525D1012031
-:1016000019902C4800EB0610407A012803D12A4992
-:1016100051F8260080474FF000090DE0254800EB07
-:101620000610406810F809000DF80400601CC4B2F0
-:1016300009F1010000F0FF091E4800EB0610007AD6
-:101640004845EBDC00201A9003E0701CC6B2052E62
-:10165000CFDB00BF03F050F910B100201A9008E072
-:10166000199810B901201A9003E0681CC5B25D45B5
-:10167000A1DB00BFBC81012505E01DF80500B968AC
-:101680004855681CC5B2A542F7DB1A9801280CD151
-:1016900002F0E0FF18B1802003F096FD05E0002085
-:1016A00003F092FD312003F051FD03F013FA1BB05B
-:1016B000BDE8F08FB8590008085A0008002005E07E
-:1016C0000449095C044A1154411CC8B20528F7DBDF
-:1016D0007047000033580008B0000020002005E0EB
-:1016E0000449095C044A1154411CC8B20928F7DBBB
-:1016F000704700002A5800083D150020002004E033
-:10170000FF21034A1154411CC8B20628F8DB704778
-:10171000B500002070470000002005E00449095C86
-:10172000044A1154411CC8B20928F7DB7047000075
-:1017300021580008341500202DE9FC410446257984
-:1017400020684678206887780B2D03D0132003F09B
-:10175000FDFC46E10EB9442F03D0312003F0F6FC26
-:101760003FE1C5480078C0F3400018B1702003F095
-:10177000EDFC36E12068C0788DF80400206800791F
-:101780008DF80500206840798DF806002068807982
-:101790008DF807002068C0798DF800002068007A75
-:1017A0008DF801002068407A8DF802002068807A68
-:1017B0008DF803009DF8040000069DF8051000EB6D
-:1017C00001409DF8061000EB01209DF80710084429
-:1017D000A949C1F8F8009DF8000000069DF8011025
-:1017E00000EB01409DF8021000EB01209DF8031072
-:1017F0000844A149C1F8FC0008460078C0F3C000C5
-:10180000002857D10846D0F8FC00B0F5805F0AD810
-:101810000846D0F8F800401C28B10846D0F8F80077
-:101820009649884203D0312003F090FCD9E09248D9
-:10183000D0F8F8009149884207D18F48807820F08D
-:10184000F00010308C4988700CE08B48D0F8F8001C
-:101850008B49884206D18848807820F0F0002030FB
-:10186000854988708448007820F008000830824953
-:1018700008700846007820F00200801C08700020E4
-:10188000C1F8EC00C1F8F000C1F8F4004FF6FF70A9
-:10189000A1F8E6002020A16848700420A1688870A3
-:1018A0000020A168C8700420A081FEF731FDFEF77A
-:1018B00043FD96E07048D0F8F800724988420FD096
-:1018C0006D48D0F8F800B0F5601F09D06A48D0F82C
-:1018D000F800B0F1805F03D0312003F037FC7AE0EC
-:1018E0006548D0F8F8006749884205D16248D0F8C9
-:1018F000FC00B0F5CC3F17D85F48D0F8F800B0F541
-:10190000601F05D15C48D0F8FC00B0F5002F0BD863
-:101910005948D0F8F800B0F1805F09D15648D0F8A6
-:10192000FC00B0F1806F03D9312003F00FFC52E0CE
-:1019300051484078C0F3800018B9222003F006FC1B
-:1019400049E04D48D0F8F8004E49884207D14A484E
-:10195000807820F00F00401C474988701AE0464804
-:10196000D0F8F800B0F5601F07D14348807820F028
-:101970000F00801C404988700CE03F48D0F8F80008
-:10198000B0F1805F06D13C48807820F00F00801CC9
-:10199000394988703848007820F00200801C3649A8
-:1019A00008700020C1F8EC00C1F8F000C1F8F400A4
-:1019B0004FF6FF70A1F8E6002020A16848700420CF
-:1019C000A16888700020A168C8700420A081FEF77B
-:1019D0009FFCFEF7B1FC2848007820F0080026495B
-:1019E000087002F089FF98B32348007820F00200C5
-:1019F000214908700846007820F040000870084629
-:101A0000007820F0800008700846407820F001003F
-:101A100048700846807820F00F008870084680786B
-:101A200020F0F00088700020C1F8F800C1F8FC0038
-:101A3000C1F8F4004FF6FF70A1F8E6000020C1F8ED
-:101A4000EC00C1F8F000887500210B48C1750176E3
-:101A50000948007820F010000749087008464078CF
-:101A600020F0100048700846407820F020004870B0
-:101A700003F030F8BDE8FC817015002000F0002074
-:101A800000D8BFFE00A000082DE9F04105460E4633
-:101A900000270F48854214D1B6F5CC3F11D803F08A
-:101AA00009FE72B60B4800683321826808489047E7
-:101AB000074603F007FE62B60FB9002402E00124D6
-:101AC00000E0012414B90120BDE8F0810020FBE70B
-:101AD00000A000082800002070B504464FF6FF76ED
-:101AE0002579012D03D0132003F030FB86E0454813
-:101AF000007800F0010040B142484078C0F3800017
-:101B000018B9222003F022FB78E03E480078C0F3A9
-:101B1000400020B13B484078C0F3001018B92420A1
-:101B200003F014FB6AE03748007820F01000103012
-:101B3000344908700846407820F010004870084684
-:101B4000007820F0200008700846007820F002009D
-:101B500008700846407820F0040048700846407835
-:101B600020F02000487000204871C1F8EC00C1F856
-:101B7000FC00C1F8F8000846007800F0010010B938
-:101B80000020C1F8F4001F480078C0F3C00018B16D
-:101B90001C48B0F8E6602DE01A48807800F00F008D
-:101BA000012808D117493722D1F8F4001649FFF768
-:101BB0003BFC06461EE01348807800F00F00022828
-:101BC00009D110493722D1F8F4004FF46011FFF722
-:101BD0002BFC06460EE00B48807800F00F00022830
-:101BE00008D108493722D1F8F4004FF08051FFF7AF
-:101BF0001BFC0646FEF784FB0120A08102F06AFF71
-:101C000070BD00007015002000A000082DE9FC5FE9
-:101C100004464FF0000B2579206846782068C0788C
-:101C20002168897800EB01201FFA80FA042D06DA7A
-:101C3000132003F08BFA02F04DFFBDE8FC9F5046E5
-:101C4000BAF57F4F73D009DCA0F2022040B3A0F5B3
-:101C50005C40A0F5EF7000286AD107E06FF47F4187
-:101C60000844002877D00128F6D168E002F036FE5B
-:101C7000032803D07F2003F069FA10E0052D03D07C
-:101C8000132003F063FA0AE0012E03D0122003F0C0
-:101C90005DFA04E00020A16808710520A08169E1D7
-:101CA0002068007900062168497900EB014021682D
-:101CB000897900EB01202168C97900EB0109082D21
-:101CC00003D0132003F042FA38E0012E03D0122093
-:101CD00003F03CFA32E0AA480078C0F3001018B9CB
-:101CE000222003F033FA29E0312002F0DFFD4846DC
-:101CF000FFF7C4F9E8B9A248807800F00F00012886
-:101D000002D19F49C87002E001209D4908719C489A
-:101D1000007820F010009A4908700846007820F0FA
-:101D20000100401C08700020A168087104E025E053
-:101D300012E10120A16808710520A0811AE102F0DA
-:101D4000CDFD032808D002F0C9FD022804D07F2071
-:101D500003F0FCF911E0B7E0042D03D0132003F0E9
-:101D6000F5F90AE0012E03D0122003F0EFF904E0A8
-:101D70000020A16808710520A081FBE00D2D03D192
-:101D800020680079442803D0132003F0DFF99AE09B
-:101D9000012E03D0122003F0D9F994E02068407995
-:101DA0008DF80400206880798DF805002068C079DE
-:101DB0008DF806002068007A8DF807002068407AC8
-:101DC0008DF800002068807A8DF801002068C07AC4
-:101DD0008DF802002068007B8DF803009DF8040058
-:101DE00000069DF8051000EB01409DF8061000EB81
-:101DF00001209DF8071047189DF8000000069DF887
-:101E0000011000EB01409DF8021000EB01209DF84D
-:101E1000031000EB01085B48874251D1B8F5CC3F75
-:101E200005D8574880780121B1EB101F18D05448CD
-:101E3000007820F00200524908700846007820F02F
-:101E4000080008700846407820F0400048700846B6
-:101E5000807820F0F0008870312003F077F932E0CC
-:101E6000312002F023FD41463846FFF70DFE0128E0
-:101E700022D14348407820F00400001D40494870BA
-:101E80000846407820F0400048700846407820F02E
-:101E90000800487000F06AFA8B20FFF74BF9002029
-:101EA000A16808710520A0813548007820F0010064
-:101EB000401C3349087006E0722003F047F902E045
-:101EC000312003F043F955E0042D03D0132003F033
-:101ED0003DF940E0012E03D0122003F037F93AE03B
-:101EE00027484078C0F3801018B9222003F02EF95B
-:101EF00031E0FFF7EBF8012821D1FFF7F5F80128D1
-:101F00001DD11F480079012819D11D48C07801282A
-:101F100015D1FFF739F92E20FFF70CF91848407852
-:101F200020F008000830164948700020A1680871A8
-:101F30000520A081002012490871C87002E022200B
-:101F400003F004F900200E49C1F8F4000846807837
-:101F500020F00F0088700DE002F07CFB18B18020AB
-:101F600003F032F905E0002003F02EF9312003F0F0
-:101F7000EDF800BF00BF02F0ADFD00BF5DE6000060
-:101F80007015002000A000082DE9FE43054602F070
-:101F9000ABFC07462879401CC6B2286890F801803F
-:101FA000022E03DC132003F0D1F8CDE1B8F1010FCC
-:101FB00009D0B8F1020F6CD0B8F1050F6FD0B8F1AD
-:101FC000060F6DD13EE1012F03D17F2003F0BEF853
-:101FD0005EE0032E03D0132003F0B8F858E0DC488D
-:101FE000007801280ED1A9684870002405E000217E
-:101FF000A01CAA681154601CC4B2042CF7DB062094
-:10200000A88145E0D348007A012803D0D148807ADE
-:10201000012803D1372003F099F839E00120A9689D
-:102020004870CD480078012812D1CA48007B0328A7
-:102030000EDB362003F08AF80120C64988720020A2
-:102040008880C648007810B90120C44908707AE138
-:10205000C148007810B9C24802F0BEF8002406E07A
-:10206000BF48015DA01CAA681154601CC4B2042CB6
-:10207000F6DB02ABBB4A0421B94802F025F8002088
-:10208000B449087208800120B34908700620A8816D
-:1020900059E1012F05D17F2003F058F868E068E08E
-:1020A00043E1072E03D0132003F050F860E0AA4864
-:1020B0000078012859D10020A7490870A548807AE6
-:1020C000012803D1362003F041F849E0002406E05E
-:1020D000A01C2968085C0DF80400601CC4B2042C24
-:1020E000F6DB9DF800008DF804009DF801008DF8E6
-:1020F00005009DF802008DF806009DF803008DF89C
-:102100000700042201A9974801F0CCFF90B10220FA
-:10211000A9684870A881002003F01EF801208C49AE
-:10212000087000208D4908708A49087302208E4982
-:10213000087015E0352003F009F88648007B401C44
-:10214000844908730846007B032809DB0120887254
-:10215000002088808148007810B901207F490870EC
-:1021600000207C490880087202E0242002F0EEFF83
-:10217000E9E0012F03D17F2002F0E8FF61E0032EA8
-:1021800003D0132002F0E2FF5BE0714840780128A1
-:102190000FD10520A9684870002405E00021A01C8B
-:1021A000AA681154601CC4B2042CF7DB0620A88175
-:1021B00047E06848407A012803D06648C07A012881
-:1021C00003D1372002F0C2FF3BE00520A968487028
-:1021D00061484078012812D15E48407B03280EDB1D
-:1021E000362002F0B3FF01215A48C1720021C1809C
-:1021F0005A48407810B9012058494870A3E0564821
-:10220000407810B9564801F0E7FF002406E0544832
-:10221000015DA01CAA681154601CC4B2042CF6DB3A
-:1022200002AB504A04214E4801F092FF0021494878
-:1022300041720020474948800120474948700620E4
-:10224000A88180E0012F03D17F2002F07FFF6BE0A7
-:10225000072E03D0132002F079FF65E03E48407856
-:1022600001285ED100203C4948703A48C07A0128D4
-:1022700003D1362002F06AFF4CE0002406E0A01CE7
-:102280002968085C0DF80400601CC4B2042CF6DB5D
-:102290009DF800008DF804009DF801008DF8050000
-:1022A0009DF802008DF806009DF803008DF80700E8
-:1022B000042201A92B4801F0F5FEA0B10620A9686F
-:1022C00048700220A881002002F046FF012020492A
-:1022D000487000202149487000211E4841730420A5
-:1022E0002149087016E0352002F030FF1948407B84
-:1022F000401CC1B217484173407B03280ADB01210F
-:102300001448C1720021C1801448407810B90120DE
-:102310001249487000200F49488000210D48417241
-:1023200002E0242002F012FF0DE002F093F918B150
-:10233000802002F049FF05E0002002F045FF122056
-:1023400002F004FF00BF00BF02F0C4FBBDE8FE8343
-:10235000C000002070260020BD0000208C0000205E
-:10236000C7000020C3000020C20000204220044912
-:1023700008704F204870452088705220C870704700
-:102380008E0000202DE9F04705460024A246A14614
-:10239000A888801E86B228684778FD4890F8058096
-:1023A00008F1010000F0FF08012E02DA132002F00C
-:1023B000CDFEB6F5806F03DD712002F0C7FEFCE1B3
-:1023C000F3480078C0F3800050B9F148D0F8F0002D
-:1023D000B0F5406F04D8EE484078C0F3001070B1FB
-:1023E000EB48407820F01000E949487008464078F2
-:1023F00020F040004870702002F0A8FEDDE1E448C3
-:102400000078C0F3801028B9E14800780121B1EBD1
-:10241000D01F03D1722002F099FECEE1DC48007893
-:10242000C0F3400018B9242002F090FEC5E1D8485E
-:102430004078C0F3401028B9012F03D0732002F078
-:1024400085FEBAE1781C804502D10220A881B4E162
-:10245000B84503D0732002F079FEAEE1CC48007895
-:1024600000F0010040B1CA484078C0F3800018B9BC
-:10247000222002F06BFEA0E1C548007820F0200089
-:102480002030C34908700846407820F020002030F2
-:10249000487008464771007800F0010000287CD0A1
-:1024A000002415E0A01C2968085CB949D1F8F01097
-:1024B000B84A5054B648D0F8F000401CB449C1F8AE
-:1024C000F0000846D0F8F400401CC1F8F400641C89
-:1024D000B442E7D32868811C3046FDF735FFAC488D
-:1024E000D0F8F400AA49D1F8FC10884277D3A84864
-:1024F000D0F8F000B0F5006F2DD3A5494FF400627D
-:10250000D1F8F800A349FEF715FF40B9FEF7E0FF48
-:10251000722002F01BFE02F0DDFABDE8F0879C4855
-:10252000D0F8F80000F500609949C1F8F8000846B5
-:10253000D0F8F000A0F50060C1F8F000002405E03C
-:1025400004F500609349085C0855641C9048D0F875
-:10255000F000A042F4D88E48D0F8F000F0B18C48DA
-:10256000D0F8F09005E0FF208A4901F8090009F150
-:102570000109B9F5006FF6D385494FF40062D1F82F
-:10258000F8008449FEF7D6FE40B9FEF7A1FF72209D
-:1025900002F0DCFD02F09EFABFE7A5E000207C49D6
-:1025A000C1F8F0000846407820F001004870084665
-:1025B000007820F0040008700846007820F0200021
-:1025C00008700846407820F04000403048700846C7
-:1025D000407820F01000103048707EE0FFE76C4833
-:1025E000D0F8F000B0F5006F77D36948407820F05C
-:1025F0000100401C664948700846007820F004003D
-:10260000001D08704FF40062D1F8F8006149FEF730
-:1026100091FE38B9FEF75CFF722002F097FD02F0E0
-:1026200059FA7AE75A48007820F080005849087033
-:102630000846D0F8F80000F50060C1F8F800084638
-:10264000D0F8F000A0F50060C1F8F000002405E02B
-:1026500004F500604F49085C0855641C4C48D0F8EC
-:10266000F000A042F4D84A48D0F8EC00401C484999
-:10267000C1F8EC000846807800F00F00012805D171
-:102680000846D0F8EC00B0F5607F17D84048807855
-:1026900000F00F00022805D13D48D0F8EC00B0F55D
-:1026A000607F0BD83A48807800F00F0002280ED1E6
-:1026B0003748D0F8EC00B0F5802F08D9FEF708FFB6
-:1026C000722002F043FD02F005FA26E705E03048EB
-:1026D000007820F040002E4908702D48007820F046
-:1026E00004002B49087066E0B6F5805F58DA0024D4
-:1026F0000FE0A01C2968085C2549D1F8F010254A94
-:1027000050542348D0F8F000401C2149C1F8F00093
-:10271000641CB442EDD31E49D1F8F0001D49FEF708
-:10272000D7FD2868811C3046FDF70EFE1848D0F80A
-:10273000F400194900EB010A154880780121B1EB3A
-:10274000101F0BD10AEB06001449884206D210482C
-:10275000104AD0F8F0105046FEF7F8FE0C48D0F8BA
-:10276000F4000B49D1F8F01008440949C1F8F4000D
-:102770000846D0F8F400D1F8FC10884217D304487A
-:10278000407820F010001030014948700FE0000040
-:10279000701500207016002000F00020FFFF0020C0
-:1027A00000200B49C1F8F400312002F0CFFC0020DA
-:1027B0000749C1F8F0000220A8810548007820F000
-:1027C00010000349087002F085F900BFA5E600007B
-:1027D000701500202DE9F047054695F8048028681B
-:1027E000407806022868807806432868C71C4FF0A6
-:1027F0000109B8F1030F03DC132002F0A7FC5CE031
-:10280000002447E02F4800EB04100088B0423FD17D
-:102810002C4800EB0410407A072839D1294800EBF6
-:102820000410007AC01C404505D0132002F08EFC35
-:102830004FF0000930E039463046FEF763FC0128CE
-:1028400005D1312002F082FC4FF0000924E0032082
-:10285000A8811C4800EB0410027A1A4800EB04100F
-:1028600041683846FEF71FFE164800EB041000884A
-:102870004FF28411884208D100F028F812484078BD
-:1028800020F00200801C104948704FF0000903E05E
-:10289000601CC4B2052CB5DB00BFB9F1010F0CD12F
-:1028A00001F0D8FE18B1802002F08EFC05E0002077
-:1028B00002F08AFC312002F049FC02F00BF9BDE87D
-:1028C000F0870000B8590008701500200146FF206D
-:1028D00070472DE9F0410246002500260020002324
-:1028E0000024002791F803C00CF00F0591F803C0F5
-:1028F0000CF0100CBCF1000F03D091F802C04CEAB0
-:10290000050591F800C0BCF1000F31D0146800201B
-:102910002BE04FF0010C0CFA00F3B1F800C00CEA08
-:1029200003069E4220D183004FF00F0C0CFA03F7F0
-:10293000BC4305FA03FC4CEA040491F803C0BCF163
-:10294000280F06D14FF0010C0CFA00FCC2F814C09D
-:102950000AE091F803C0BCF1480F05D14FF0010C1B
-:102960000CFA00FCC2F810C0401C0828D1D3146037
-:10297000B1F800C0BCF1FF0F34DD546800202EE038
-:1029800000F1080C4FF0010808FA0CF3B1F800C090
-:102990000CEA03069E4221D183004FF00F0C0CFA83
-:1029A00003F7BC4305FA03FC4CEA040491F803C0A6
-:1029B000BCF1280F05D100F1080C08FA0CF8C2F898
-:1029C000148091F803C0BCF1480F07D100F1080C46
-:1029D0004FF0010808FA0CF8C2F81080401C0828D3
-:1029E000CED35460BDE8F081F0B50A460023002440
-:1029F0000021002500F00046B6F1004F02D11D4E27
-:102A0000F16901E01B4E7168C0F3034583B200F425
-:102A10004016B6F5401F08D121F07061154E76685A
-:102A200026F07066134F7E6012E000F48016B6F553
-:102A3000801F06D1032606FA05F4A14341F0706118
-:102A400006E0460D360103FA06F6B14341F0706127
-:102A500022B1460D360103FA06F6314300F0004676
-:102A6000B6F1004F02D1034EF16101E0014E7160F9
-:102A7000F0BD0000000001404161704701617047F6
-:102A80000148006870470000D800002000BFFEE742
-:102A9000704700002DE9F04F95B004468A469046F5
-:102AA0001E460025402105A8FDF797FB0020049055
-:102AB0000027012003904FF0000B194800EB441051
-:102AC00000680490164800EB44104779FF2E00D0B0
-:102AD0003746402F00D94027114800EB4410D0F86A
-:102AE0001C90002505E019F8050005A94855681C4B
-:102AF000C5B2BD42F7D305ABCDE90074514640469F
-:102B0000049A00F029F88346BBF1000F02D101209E
-:102B1000039001E000200390039815B0BDE8F08F0A
-:102B20003858000810B50446012C06DA0020034985
-:102B300008552146012000F003F810BDFB000020DD
-:102B4000012803D10122034B5A5402E00022014B19
-:102B50005A547047F40000202DE9F04F87B0064624
-:102B60008B4617469846DDE910954FF0000A012E76
-:102B700003DB012007B0BDE8F08F1F48C0F80490C8
-:102B800000201D4948721D4800EB4510007908706F
-:102B90001A4800EB4510407C08B1012000E00020FD
-:102BA00015498872154800EB4510807C08B101205A
-:102BB00000E000201049087200208DF810000297F4
-:102BC000084600798DF8120000208DF811000024CD
-:102BD00006E018F804100DF113000155601CC4B292
-:102BE0009DF81200A042F4DC0698009002A80FC8DD
-:102BF000FEF7AAF85046BDE7982A0020385800088A
-:102C00002DE9F04106460C46154600270848005DB0
-:102C100008B1012C02DB0020BDE8F0812B462246E2
-:102C200039463046FFF736FF80464046F4E700005D
-:102C3000F400002010B54FF400600B49086002F06A
-:102C40004BFD4FF480600849091F086002F044FD05
-:102C50004FF480600449086002F03EFD4FF40060CC
-:102C60000149091F086010BD140C014010B54FF454
-:102C700000600949086002F02FFD4FF480600649AA
-:102C8000086002F029FD4FF480600349091D0860C7
-:102C900002F022FD10BD0000100C014070B5054689
-:102CA0000024002618E06006040E4FF480600F49EF
-:102CB000086002F011FD0D480838006800F400605B
-:102CC00008B1601CC4B24FF480600849091D086057
-:102CD00002F002FD701CC6B2082EE4DB15B9FFF746
-:102CE000C5FF01E0FFF7A6FF204670BD100C0140B4
-:102CF00070B50446002524E004F0800020B14FF4B4
-:102D000000601149086004E04FF400600E49091D9D
-:102D1000086002F0E1FC4FF480600B49086002F0AB
-:102D2000DBFC4FF480600849091D0860072D02D1C3
-:102D30004000091F08606006040E02F0CDFC681C0C
-:102D4000C5B2082DD8DB70BD100C014010B54FF492
-:102D500000600A4908604010086002F0BDFC4FF4B2
-:102D600000600649091D086002F0B6FC4FF480605F
-:102D70000249091D086002F0AFFC10BD100C0140B3
-:102D800010B54FF40060074908604010091F086043
-:102D900002F0A2FC4FF400600249091F086002F033
-:102DA0009BFC10BD140C014010B54FF400600E499F
-:102DB000086002F091FC4FF480600B49086002F05B
-:102DC0008BFC09480838006800F4006008B1012451
-:102DD00000E000244FF480600349091D086002F000
-:102DE0007BFC204610BD0000100C014010B50446CD
-:102DF0000548827A00212046FFF702FF012800D112
-:102E000010BD0020FCE700001C15002070B5054631
-:102E10000C46224600212846FFF7F2FE012800D189
-:102E200070BD0020FCE7000010B50446044800789F
-:102E300010B900F0E1FD01E000F034FC10BD00002D
-:102E40006600002010B500F04DFC00F01DFE10BD26
-:102E500010B50020044908710449C870FF200449D6
-:102E60000870FFF7EFFF10BD600000205A0000203F
-:102E7000660000203EB57948006878498988084492
-:102E800001907748C078052806D0062834D0072856
-:102E900076D0082875D1A1E07048C088082817DBD3
-:102EA00000207049096808706C4880796D4909688C
-:102EB00048706C480068801C00906848C088ADF875
-:102EC00008006649C988891C88B200F00DFD12E02F
-:102ED0006248807963490968087062480068401C4C
-:102EE00000905E48C088ADF808005C49C988491C5C
-:102EF00088B200F0F9FCA8E05849C88800F0F4FC5A
-:102F00005648C088B0F5805F3CDB10205549096801
-:102F10000870544800680078524909680870002019
-:102F20005049096848704D48C08800164D490968E5
-:102F3000887000204B490968C8704848C088000A5A
-:102F400048490968087145488079464909684871C7
-:102F500044480068801D00904048807A801F80B2FD
-:102F6000ADF808003D48807A801F3C4988800846BB
-:102F7000408920F4706048810020394988702CE035
-:102F80002DE060E010203749096808703548006876
-:102F900000783249C988C1F30321084331490968DF
-:102FA00008702E4880792F49096848702D480068BC
-:102FB000801C00902948807A801E80B2ADF80800FD
-:102FC0002648807A801E254988800846408920F45A
-:102FD0007060488100202249887036E000BF2020C0
-:102FE0002049096808701F48006800781B49498912
-:102FF000C1F3032108431B49096808701948006898
-:10300000401C00901648C078082808D11348C08892
-:1030100012498988401A80B2ADF8080005E00F48CF
-:10302000807A401E80B2ADF808000C488188807A12
-:10303000401E084409498880BDF80810491C88B220
-:1030400000F052FC01E001203EBD00BF06480168CF
-:103050006846884704462046F6E700001C15002015
-:103060005A0000206C00002084000020002005E0B1
-:10307000AA21044A12681154411CC8B20828F7DB7F
-:10308000704700006C00002070B5FE48867A082E5C
-:1030900001D0002070BDFB48C07A00F0F00038B1CC
-:1030A000102804D020287DD030287CD154E200BFE5
-:1030B000F548007998B1F4480079012801D1002041
-:1030C000E8E7F048C07A022826D1EE48007B3E2887
-:1030D00022D1EC48407B80281ED10020DAE7E94865
-:1030E000C07A022818D1E748007B3E2814D1E54871
-:1030F000407B802810D1E548008828B9E448008842
-:1031000010B9E448007938B10020E0490880012076
-:10311000E14908700020BDE700F0E4FA0220DA4936
-:1031200008710020DD498880D648C07A00F0F000A0
-:1031300000287DD010287CD1D2480088C0F30A0036
-:1031400040F2DF71884206D10120CF49087100F0BA
-:1031500005FB00209EE7D248C078022807D0D0485F
-:10316000C078032803D0CE48C078082806D10120B3
-:10317000C549087100F0F2FA00208BE7082E7AD1D9
-:10318000C048C07A00F00F004FF6FF7101EA00203E
-:10319000C249C8800846C088BA49097B0843BF496C
-:1031A000C88001E0DEE06AE20846C088072869DDE1
-:1031B00000204881B3480D3008600B46D988B14BD8
-:1031C0001B88C3F30A00B74B1A689047B3490860DD
-:1031D0000846807A00F0030088B102280ED103204F
-:1031E000A9490880072008710846808820F480706B
-:1031F00000F58070888000F0BBFA42E000BFA7486D
-:103200000068C8B39F48407BA449096808709D487E
-:10321000807BA249096848709A48C07B9F49096829
-:1032200088709848007C9D490968C870954801E0FD
-:1032300035E08FE0407C9949096808719148807CAD
-:103240009649096848710620944988800846008993
-:1032500020F00F00401C088103208B4908800520C6
-:1032600008710846808820F4807000F5807088809E
-:1032700000F07EFA04E00BE0FFE7002082490871CD
-:1032800000BF0AE001208049087100F067FA04E0FD
-:1032900001207D49087100F061FA0020FAE67948C2
-:1032A0000088C0F30A00804908807648C07A7B49CC
-:1032B000C8800846C088401CB04244DC0846C0882C
-:1032C00007283ADC0846C08880B3002048816D4852
-:1032D0000C3008600B46D9886A4B1B88C3F30A0080
-:1032E000704B1A6890476D49086008460068F0B155
-:1032F0000846807A00F00300C8B9002407E061485E
-:103300000C30005D654909680855601CC4B263480B
-:103310008079401EC0B2A042F1DA01205A490871FA
-:103320005E4AD088614A1168884711E005E00120B3
-:103330005549087100F012FA0AE00120524908715B
-:1033400000F00CFA04E001204F49087100F006FA81
-:1033500000209FE601204C49087100F0FFF900BFF2
-:1033600000BF8DE147480088C0F30A0040F2DF71DA
-:10337000884206D101204449087100F0EFF900208D
-:1033800088E641480079032803D03F4800790528A2
-:1033900076D13D48007905280FD13B488088C0F39D
-:1033A000002040B942490878FFF772FB404908788D
-:1033B000FFF73AFD01E000206CE638488088C01D28
-:1033C0003649C988884237DB3448C0883349898800
-:1033D000401A401CB0420EDC2A48C07A00F00F00B0
-:1033E0002E49097A01F00F01884205D001202649B3
-:1033F000087100F0B3F9ACE000240AE021480C3079
-:10340000005D26490968254A928811440855601CC8
-:10341000C4B2224881790079401C081AC0B2A04287
-:10342000ECDA012018490871002008801B4AD08876
-:103430001E4A116888478CE0082E0BD11148C07ACB
-:1034400000F00F001549097A01F00F01884202D0FF
-:1034500000F048F97DE00B48017B104800680F4AF6
-:10346000928881540748407B0C4909680B4A92882E
-:10347000114448700348807B08490968074A19E0ED
-:1034800069E00000802A0020600000205200002037
-:10349000540000204800002056000020281500207D
-:1034A0005A0000207C0000205800002070000020FE
-:1034B000680000209288114488707348C07B73496B
-:1034C0000968724A92881144C8706F48017C6F483D
-:1034D00000686E4A9288104401716B48407C6B49C9
-:1034E00009686A4A9288114448716748817C674834
-:1034F0000068664A92881044817164488088C01DC3
-:10350000624988800846007A401C098960F30301FB
-:103510005E4801815E488078B0B15D488078401E89
-:103520005B4988700846807870B9052008710320CF
-:1035300008800846808820F4807000F580708880BC
-:1035400000F016F90020A5E50F205149088003205E
-:10355000087100209EE593E04B480088C0F30A0004
-:103560004C49098888420ED047480088C0F30A00B9
-:1035700040F2DF71884206D101204549087100F010
-:10358000EDF8002086E54448C078022807D042487C
-:10359000C078062803D04048C07807286ED13E483E
-:1035A000007900F00100A0B93B48C078062807D098
-:1035B0003948C07807280ED13748807801280AD1C9
-:1035C00036490878FFF764FA34490878FFF72CFC8D
-:1035D00001E000205EE53048C07802284CD1032E7F
-:1035E0004ADB2948C07A302804D0312839D0322823
-:1035F0003ED13AE028480079C0F38000F8B9264867
-:10360000808820F00400001D234988801E48007B2C
-:10361000234908721C48457B0A2D02DA01204872B2
-:1036200016E005F0800058B1F02D05DDF92D03DC22
-:1036300001201B4948720BE00E201949487207E02F
-:1036400005F109000A2190FBF1F0401C1449487271
-:103650001348007A10498870012008800320C87040
-:1036600009E00F200C49088005E000F00DFA02E0A7
-:1036700000F00AFA00BF00BF00200BE500E000BF29
-:1036800000BF002006E50000802A00202815002049
-:1036900060000020580000205A0000206800002030
-:1036A0001C1500200D480079052802D007280DD1EF
-:1036B00007E00F200949088003200871FF20C87027
-:1036C00005E0002005490880087100E0704700BF50
-:1036D000FF200349087000BFF8E7000060000020E9
-:1036E0006600002010B518480079012809DD164849
-:1036F0000079082805D00820134908711349086883
-:10370000804700201049088008710846808820F40E
-:10371000807088800846808820F4007088800C487B
-:10372000008920F00F000A490881002048810948DB
-:103730000078802806D108490878FFF7A9F9FF200A
-:103740000449087010BD00006000002074000020D3
-:1037500028150020660000206800002010B5FFF743
-:10376000C1FF10BD014A508170470000281500209C
-:1037700070B538488088C0F34020D8B1354DA8884E
-:10378000C0F34020002863D02846808820F40070D1
-:103790002946888030490878FFF728FB0446002C2A
-:1037A00056D12846808820F4007000F50070294624
-:1037B00088804DE027488088C0F30020002847D04B
-:1037C000244DA888C0F30020002841D02348007869
-:1037D000FF283DD18020214908702846808820F4A8
-:1037E00080702946888008201D498872002605E0DF
-:1037F000AA201C4909688855701CC6B21848807AEE
-:10380000B042F5DC13480079072804D1322015496D
-:103810000968087003E03020124909680870002028
-:1038200010490968487001200E4909688870002015
-:103830000849887008490878FFF7D8FA04463CB967
-:103840000448808820F4007000F5007001498880E9
-:1038500070BD0000600000206800002066000020AD
-:103860001C1500206C00002010B51E4800880028A0
-:1038700036D01C4C2088002832D020460088401EBC
-:10388000214608800846008840BB08460079032886
-:1038900006D0052807D0062809D007281CD103E048
-:1038A000FFF720FF19E000BFFFF71CFF15E00D48F0
-:1038B000C07810B9FFF716FF0DE003200949088012
-:1038C000052008710846808820F4807000F580701B
-:1038D0008880FFF74DFF00E000BF01E0FFF748FFE1
-:1038E00010BD0000600000200C4A12780C4B03EB66
-:1038F00042125179884202DB0A4A91720CE0C2B24C
-:10390000094B9A5C094B9A5C064B9A721A46927A5A
-:10391000082A01DA08229A72704700006800002025
-:10392000385800081C150020CC570008BC57000868
-:1039300010B5FFF799FF00F067F910BD10B5034609
-:1039400009B9012010BD1648C07808B10320F9E775
-:103950001448807A082801DD022200E00122114883
-:10396000807A801A80B2884203DB05200C4CE0701C
-:1039700002E006200A4CE0700320094C2080094830
-:1039800003600020074CA0802046C1800448808846
-:1039900020F00100401C024CA0800020D2E7000073
-:1039A0005A0000201C15002011484089000A401CC4
-:1039B0000F49498960F30B210D4841818188807A44
-:1039C000401E80B208440A49C988884203DB0820A7
-:1039D0000849C87002E007200649C870032005495D
-:1039E00008800846808820F00100401C88807047CD
-:1039F0001C1500205A00002010B51F48C07805286B
-:103A000006D006280ED0072817D008282CD100E0B1
-:103A100000BF1A4801680020884700201649088026
-:103A2000C87022E00F20144908800220C8700846A0
-:103A3000808820F00400888017E00F48807860B10B
-:103A40000D488078401E0C4988700846807820B95F
-:103A50000F2008800220C87007E00948407A064914
-:103A600008800320C87000E010BD00BFFF2005499A
-:103A7000087000BFF8E700005A000020780000201E
-:103A80001C1500206600002010B501241B48C078DA
-:103A900001280EDD1948C07809280AD009201749E5
-:103AA000C870174908688047044614B900201349B4
-:103AB000C8700020114908800846808820F0010065
-:103AC00088800846808820F00200888054B1002059
-:103AD000C8700C4908720846408920F4706048811B
-:103AE000082088720848007830B908490878FEF73D
-:103AF000CFFFFF200449087010BD00005A000020CD
-:103B0000800000201C1500206600002068000020B6
-:103B100070B539480079C0F34000D0B1364DA8885F
-:103B2000C0F34000002866D02846808820F00200BC
-:103B30002946888031490878FFF758F90446002C57
-:103B400059D12846808820F00200801C29468880B0
-:103B500051E02948007900F0010000284BD0264DA3
-:103B6000A88800F00100002845D025480078FF28EB
-:103B700041D10020224908702846808820F00100A9
-:103B800029468880FFF772FAFFF774F906466EB986
-:103B90001A490878FFF72AF9044664BB284680884A
-:103BA00020F00200801C2946888024E01248C0785A
-:103BB000072807D01048C078082803D00E48C078DE
-:103BC00006280ED10C48C078062803D100200D49E4
-:103BD000888006E00B488188807A401E081A0949CF
-:103BE0008880FF20064908700348808820F0010083
-:103BF000401C0149888070BD5A00002068000020E8
-:103C0000660000201C15002010B51648008820B35F
-:103C1000144C208808B320460088401E21460880A6
-:103C200008460088D0B90846C078801E072813D2FD
-:103C3000DFE800F00407120C0D0E0F00FFF724FF61
-:103C40000BE0FFF7B1FEFFF763FF06E000BF00BF28
-:103C500000BFFFF719FF00E000BF01E0FFF758FFCA
-:103C600010BD00005A00002008B5074840680090C9
-:103C700006490098086004490868FCF77CFA034884
-:103C80000068804708BD000000A00008E800002090
-:103C900008B501211C2000F02FF94FF40070ADF899
-:103CA000000010208DF8030003208DF80200694603
-:103CB0005348FEF70EFE4FF400715148FEF7DEFE4A
-:103CC0000120ADF8000010208DF8030003208DF8CE
-:103CD000020069464A48FEF7FCFD01214848FEF70C
-:103CE000CDFE40F20240ADF8000010208DF8030038
-:103CF00003208DF8020069464148FEF7EAFD0221E3
-:103D00003F48FEF7BBFE4FF480613D48FEF7B4FE2E
-:103D1000A020ADF8000010208DF8030003208DF8DE
-:103D2000020069463748FEF7D4FD20213548FEF7EA
-:103D3000A3FE80213348FEF7A1FE44F22720ADF810
-:103D4000000010208DF8030003208DF80200694662
-:103D50002D48FEF7BEFD4FF400712B48FEF78EFE96
-:103D600001212948FEF788FE02212748FEF784FE3C
-:103D700004212548FEF780FE4FF480412248FEF7DB
-:103D80007BFE20212048FEF777FE4FF48070ADF8CF
-:103D9000000048208DF8030069461948FEF799FD98
-:103DA0004FF40070ADF8000048208DF8030069461C
-:103DB0001448FEF78EFD0121084600F09DF8012110
-:103DC0001248FEF711FE1020ADF8000001208DF81A
-:103DD000020010208DF8030069460B48FEF779FDBC
-:103DE00010210948FEF74AFE4FF40050ADF80000DC
-:103DF00004208DF8030069460248FEF76AFD08BDFD
-:103E00000008014000100140000C0140000130009A
-:103E100000BFFEE7704710B54FF4A06000F03AF81D
-:103E200010BD000070B5002100230F22C47804B338
-:103E3000154C246804F4E064C4F5E064210AC1F17F
-:103E40000403CA40447804FA03F1847814402143FF
-:103E500009010E4C0678A155047804F01F050124D1
-:103E6000AC4005786D11AD0005F1E025C5F80041C5
-:103E700009E0047804F01F050124AC40044D0678E5
-:103E8000761145F8264070BD0CED00E000E400E03E
-:103E900080E100E002490143024A116070470000DE
-:103EA0000000FA050CED00E00149086270470000CF
-:103EB00000000E427047000029B1064AD269024351
-:103EC000044BDA6104E0034AD2698243014BDA61B0
-:103ED000704700000010024029B1064A12690243EF
-:103EE000044B1A6104E0034A12698243014B1A61D0
-:103EF000704700000010024029B1064A926902434F
-:103F0000044B9A6104E0034A92698243014B9A612F
-:103F100070470000001002402DE9F041002100220E
-:103F2000002500230026002400278C46DFF860814E
-:103F3000D8F8048008F00C0121B1042907D0082921
-:103F400059D109E0DFF84C81C0F8008058E0DFF873
-:103F50004481C0F8008053E0DFF83481D8F8048051
-:103F600008F47012DFF82881D8F8048008F480354E
-:103F7000920C0D2A01D0921C00E0062235B9DFF820
-:103F8000188102FB08F8C0F8008033E0DFF80081F8
-:103F9000D8F82C8008F48036DFF8F480D8F82C802C
-:103FA00008F00F0808F1010446B9DFF8E880B8FB13
-:103FB000F4F808FB02F8C0F800801BE0DFF8D080BE
-:103FC000D8F82C80C8F3031808F10107DFF8C08087
-:103FD000D8F82C80C8F3032808F1020CDFF8B4806D
-:103FE000B8FBF7F808FB0CF8B8FBF4F808FB02F88C
-:103FF000C0F8008004E0DFF89C80C0F8008000BFBB
-:1040000000BFDFF88C80D8F8048008F0F0010909BF
-:10401000DFF8888018F80130D0F8008028FA03F81B
-:10402000C0F80480DFF86880D8F8048008F4E06104
-:10403000090ADFF8688018F80130D0F8048028FAFF
-:1040400003F8C0F80880DFF84880D8F8048008F446
-:104050006051C90ADFF8448018F80130D0F80480B4
-:1040600028FA03F8C0F80C80DFF82480D8F8048020
-:1040700008F44041890BDFF8288018F80130D0F8A7
-:104080000C80B8FBF3F8C0F81080BDE8F0810000A8
-:104090000010024000127A0000093D0000000020DC
-:1040A0001000002070B503460C460120002107E0F7
-:1040B000655C5E5CB54201D0002003E04D1CE9B2B6
-:1040C0009142F5DB00BF70BD78B50C46057845B967
-:1040D000457835B9857825B9C57815B900251D709D
-:1040E00078BD002107E0455C184E765C75400DF800
-:1040F00001504D1CE9B20429F5DB9DF8015005F093
-:10410000F0059DF8006006F00F0645EA06151570EB
-:104110009DF801502D072D0E9DF8026045EA1615F9
-:1041200055709DF8025005F0F0059DF8036045EAD2
-:10413000161595709DF8035005F00F069DF8005078
-:1041400066F31F15D5701C7000BFC9E71C5A000824
-:1041500078B50C46057845B9457835B9857825B9DF
-:10416000C57815B900251D7078BD002107E0455CB4
-:10417000184E765C75400DF801504D1CE9B20429CB
-:10418000F5DB9DF8005005F00F069DF8015066F331
-:104190001F1515709DF801502D099DF8026006F05D
-:1041A0000F0645EA061555709DF8035005F0F00519
-:1041B0009DF8026045EA161595709DF8035005F0CC
-:1041C0000F059DF8006045EA1615D5701C7000BFFC
-:1041D000CAE700001C5A00082DE9F0410446FCF72C
-:1041E0004FFE0546134800782844C5B2002612E069
-:1041F000691C42F2BB02514343F2390202EB410017
-:10420000C11700EB11610912A0EB0127FDB204F800
-:10421000015B701CC6B2042EEADB06480078401C25
-:104220000449087008460078642801D1002008700D
-:10423000BDE8F081E4000020704710B500F002F8FE
-:1042400010BD00000CB500200190009040480068AF
-:1042500040F480303E49086000BF3D48006800F4EB
-:10426000003000900198401C0190009820B94FF652
-:10427000FF7101988842F0D13548006800F40030A1
-:1042800010B10120009001E000200090009801286A
-:104290005CD13048006840F010002E4908600846A4
-:1042A000006820F0030008600846006840F0020043
-:1042B00008602748406826494860084640684860CA
-:1042C0000846406840F4806048600846C06A224959
-:1042D00008401F49C8620846C06A204908431C4973
-:1042E000C8620846006840F08060086000BF184857
-:1042F000006800F000600028F9D01548406820F4FC
-:104300007C10134948600846406840F4E810486053
-:104310000846006840F08070086000BF0C480068E4
-:1043200000F000700028F9D00948406820F0030030
-:10433000074948600846406840F00200486000BFF6
-:104340000348406800F00C000828F9D10CBD0000BB
-:10435000001002400020024000F0FEFF140801009F
-:104360000F480068401C0E4908600E480068401C59
-:104370000C4908600A4800684FF47A71B0FBF1F20A
-:1043800001FB1200012804D107480068401C0649BF
-:1043900008600648007810B9012004490870704789
-:1043A000340000202C0000203800002030000020C5
-:1043B00030B5164800684FF47A72B0FBF2F1B1F1F3
-:1043C000807F01D301201DE021F07F40401E4FF08F
-:1043D000E022506150170F22002807DA13071D0E44
-:1043E0000B4B00F00F04241F1D5503E013071C0E98
-:1043F000084B1C5400BF00204FF0E02290610720C2
-:104400001061002008B100BFFEE730BD140000209D
-:1044100018ED00E000E400E010B5FFF725FC10BD4A
-:1044200010B51648006840F00100144908600846BD
-:10443000406813490840114948600846006811491E
-:1044400008400E4908600846006820F48020086093
-:104450000846406820F4FE0048600846006820F0E6
-:10446000A05008604FF47F0088600020C862FFF70A
-:10447000E4FE4FF000600449086010BD00100240E7
-:104480000000FFF0FFFFF6FE08ED00E010B50A485F
-:104490000078401C084908700846007803280ADBA9
-:1044A00000200870002401E0601CC4B2012CFBDB7A
-:1044B00072B6FFF7B1FF10BDEC00002002460023EA
-:1044C00021B90D4800681060012070470A48036850
-:1044D0001068984205D81068181A884209D301203C
-:1044E000F3E71068C0F1FF301844884201D301207F
-:1044F000EBE70020E9E70000340000204F48007897
-:1045000001280AD14E484089401C4D49488101206C
-:10451000087000204949087000E070474848408909
-:10452000052190FBF1F201FB120030B944484089AB
-:1045300018B101204249487000E0EEE74048408948
-:104540000A2190FBF1F201FB120028B93C48408996
-:1045500010B101203A49887039484089142190FBF4
-:10456000F1F201FB120028B93548408910B1012051
-:104570003349C87032484089322190FBF1F201FB87
-:10458000120028B92E48408910B101202C49087129
-:104590002B484089642190FBF1F201FB120028B9FD
-:1045A0002748408910B10120254948712448408995
-:1045B0004FF4FA7190FBF1F201FB120028B9204888
-:1045C000408910B101201E4988711D4840894FF46F
-:1045D0007A7190FBF1F201FB120028B9184840896A
-:1045E00010B101201649C8711548408940F2DC51CC
-:1045F00090FBF1F201FB120028B91148408910B17B
-:1046000001200F4908720E4840894FF4FA6190FB6F
-:10461000F1F201FB120028B90948408910B10120CC
-:10462000074948720648408941F27071884202DBAE
-:1046300000200349488100BF6FE7000030000020E0
-:104640000C01002000200249087048804860704733
-:104650003C00002003484078022801D10120704727
-:104660000020FCE75801002010B504462046FCF766
-:10467000A3FD10BD70B53848007900F04000B8B116
-:104680003548007920F0400033490871012408467C
-:10469000407900B104243148007818B124F00104B5
-:1046A00044F0020404F0010010B1002000F05AFDB3
-:1046B0002948007902281AD104202749087128487E
-:1046C00080680078274948700020244908702448F1
-:1046D0008089C82802DA2248858900E0C825EAB224
-:1046E0001F4B19699868FCF7DEFE00F049FA1A487A
-:1046F000007900F0100068B300201B4908801748BB
-:10470000007878280AD11948007838B11348007821
-:10471000782814D115484088012810D120200E494E
-:1047200008710E48007808B9012000E002200C4909
-:1047300088700F490A480161083000F0ADFE074853
-:104740000078782806D109480078012802D1022093
-:104750000149087170BD0000480000205000002091
-:104760005801002070010020520000203C00002071
-:104770003D0B002010B504462046FCF776FD10BD29
-:1047800070B5044601252289D4E9000100F003F840
-:104790000025284670BD03E0531E9AB28B5C8354FB
-:1047A000002AF9D1704700002DE9F041044638484D
-:1047B000007800F07F072068457825F0800594F8A0
-:1047C0000480B8F1010F03D1132000F0BFFC5BE0BF
-:1047D000012D04D0022D04D0032D44D100E000BFF0
-:1047E00000BFB8F1020F05D0132000F0AFFC00F0BD
-:1047F000B9F948E0012F01D1022D03D0022F07D1D2
-:10480000032D05D17E2000F0A1FC00F0ABF93AE0C9
-:10481000032F04D1022D02D101201D49087100206F
-:1048200000F0A0FC002606E000201A4988551A492D
-:104830008855701CC6B2022EF6DBFCF719FC062068
-:10484000A0810020A16888703220A168C870012072
-:10485000A1680871F420A1684871032D02D10120DC
-:10486000FCF776FB0FE0FFF7F5FE20B180200B4947
-:104870000968C87006E0002008490968C87012205D
-:1048800000F064FC00BF00BF00F024F9BDE8F08137
-:1048900058010020BD000020C0000020480000207A
-:1048A00010B504462046FCF779FD10BD10B504464E
-:1048B0000320094908707F204870084684707820DA
-:1048C000C870AA20087148718871C8710821002039
-:1048D000FEF79CFA10BD0000180100200148007886
-:1048E00070470000580100200248007800F07F0067
-:1048F0007047000058010020014800787047000010
-:10490000500000200A4A127902F0FE02084B1A7188
-:1049100049B91A461268824205D11A46127942F004
-:1049200002021A7170470122024B1A7000BFF9E7A8
-:10493000480000205600002070B504460D46A078BF
-:10494000012804D0022803D0032806D104E000BFC8
-:10495000284600F057F801E000E000BF00BF00204B
-:10496000A07070BD01460120044A127942F0010294
-:10497000024B1A711A46116000207047480000204F
-:104980002DE9F04104460D46002740F6C41085424B
-:1049900003DD0220FEF7E6FE16E040F2DF708442FF
-:1049A00003D102200A49487006E040F20B708442AD
-:1049B00002D101200649487005488581FFF7D2FFE2
-:1049C00006460EB9024887683846BDE8F081000007
-:1049D0005801002010B5044600210448FFF792FF5B
-:1049E000FEF7BCFE05200249088010BD58010020DA
-:1049F0005200002010B503210148FFF783FF10BDCE
-:104A0000580100200021054A1180054948714021C4
-:104A1000034A11710121034A1170704752000020AE
-:104A2000480000205600002010B500201E49887064
-:104A300001200870087148710020C8701B48886008
-:104A40001B491948016100201A49487108717F20EB
-:104A50001949087078208870002018490870184992
-:104A60000870FFF7EFFD1748007820F02000154987
-:104A7000087000240EE0002113480155801E0155E6
-:104A8000001F20F8141000200F490A3921F81400E3
-:104A9000601CC4B2022CEEDBFCF7EAFA00200B49E2
-:104AA00008800B49088010BD5801002079010020C2
-:104AB0003D0B002048000020700100205000002025
-:104AC00056000020BB0000207A2600205400002061
-:104AD0005200002010B517480079042822D116484A
-:104AE0000269846823781548007848B17F201070E7
-:104AF000537012480078907003210F48818208E0BB
-:104B00000C480068C078802803D003F14000107082
-:104B1000521C0A480078782801D0FFF793FD08203E
-:104B2000044908710348007940F0100001490871F8
-:104B300010BD000048000020580100205000002057
-:104B400010B504462046FCF70BFD10BD10B5044619
-:104B50002046FCF7F1FD10BD10B504462046FCF7D9
-:104B6000BBFF10BD002002490968C87070470000F3
-:104B70004800002010B504462046FDF747F810BD58
-:104B80002DE9F05F4FF00008F8488468067B207834
-:104B9000F749085C00EB4000F64901EB80004578DE
-:104BA0002078F349085C00EB4000F24901EB8000FB
-:104BB00090F804902078EE49085C00EB4000ED4945
-:104BC00001EB800090F805A0FFF78EFE074694F8F1
-:104BD00000B02078862800DBC346E7480078C0F3A1
-:104BE000401058B1E1484078022807D18020E349BD
-:104BF0000968C870FFF76EFFBDE8F09FDC4810F849
-:104C00000B00FF2874D0012F04D0022F71D0032F86
-:104C100070D14DE0D5484078022848D12078272827
-:104C20000ED020782E280BD020782F2808D020787E
-:104C3000312805D02078342802D02078372809D1AF
-:104C40007F20CF4908708020CC490968C870FFF7E1
-:104C500041FFD1E7607800F0800040B32078C4497C
-:104C6000085C00EB4000C34901EB8000C078F0B164
-:104C70002078192802D02078282804D18020BF4924
-:104C80000968C87013E02078B949085C00EB40005F
-:104C9000B84911F82000B04205D01320B849087077
-:104CA000FFF718FFA8E78020B4490968C8709FE0A3
-:104CB000AE48407802284BD1207827280ED02078A3
-:104CC0002E280BD020782F2808D02078312805D026
-:104CD0002078342802D0207837280CD17F20A849AA
-:104CE00008708020A5490968C870FFF7F3FE83E7C4
-:104CF000C8E12EE07BE0607800F0800040B32078CF
-:104D00009B49085C00EB40009A4901EB8000C078A9
-:104D1000F0B12078192802D02078282804D18020EA
-:104D200096490968C87013E020789149085C00EB47
-:104D30004000904911F82000B04205D0132090495E
-:104D40000870FFF7C7FE57E780208C490968C870D4
-:104D50004EE086484078022848D1207827280ED097
-:104D600020782E280BD020782F2808D020783128C2
-:104D700005D02078342802D02078372809D17F2028
-:104D80007F49087080207D490968C870FFF7A2FE3E
-:104D900032E7607800F0800040B320787449085C06
-:104DA00000EB4000734901EB8000C078F0B120783F
-:104DB000192802D02078282804D180206F4909685A
-:104DC000C87013E020786A49085C00EB400069492C
-:104DD00011F82000B04205D0132069490870FFF790
-:104DE00079FE09E7802065490968C87000E000BFC6
-:104DF00000BF20785E49085C00EB40005D4901EB94
-:104E00008000C078002875D0607800F0800000280D
-:104E100071D0012E6FDD207828285AD004DC1028AC
-:104E200007D0112868D105E03E287CD08528F9D12B
-:104E3000D4E000BF607881280ED0607883280BD042
-:104E40006078822802D12078112805D060788228E5
-:104E50002DD1207810282AD1022E03D013204849C2
-:104E6000087035E0FFF740FD012816D1062D01D06E
-:104E7000042D09D1002042490870607800F08000BC
-:104E80003E490968C87023E0B8F1000F20D14FF007
-:104E900001087E203A4908701AE00020384908705D
-:104EA000607800F0800035490968C87010E02F482C
-:104EB0004078022806D1802030490968C870FFF781
-:104EC00009FE99E6607800F080002C490968C870F6
-:104ED000CDE0032E11D02548407802280DD123487B
-:104EE0004078022841D1802024490968C870FFF722
-:104EF000F1FD81E6C1E0BBE0B2E06078802802D03D
-:104F00006078832823D1FFF7EFFC012815D1052D08
-:104F10000AD100201A490870607800F08000174913
-:104F20000968C87021E02DE0B8F1000F1DD14FF0E5
-:104F300001087E201249087017E00020104908700F
-:104F4000607800F080000D490968C8700DE00748DE
-:104F50004078022806D1802008490968C870FFF708
-:104F6000B9FD49E612200649087080E0580100208A
-:104F7000305900089458000870150020480000209F
-:104F8000500000206078802819D1FFF7ADFC01287F
-:104F90000BD1042D21D1002060490870607800F009
-:104FA00080005F490968C87017E000205B490870FD
-:104FB000607800F080005A490968C8700DE05948CF
-:104FC0004078022806D1802055490968C870FFF74B
-:104FD00081FD11E612205149087048E0022E07D0E9
-:104FE00050484078022803D113204C49087036E01D
-:104FF0006078812802D06078822822D1FFF774FC83
-:10500000012814D1032D09D100204449087060788B
-:1050100000F0800042490968C87020E0B8F1000F34
-:105020001DD14FF001087E203C49087017E0002098
-:105030003A490870607800F0800039490968C87002
-:105040000DE038484078022806D1802034490968AC
-:10505000C870FFF73FFDCFE512203049087006E029
-:10506000607800F080002E490968C87000BF17E022
-:1050700000202B490968C87012E0002028490968FF
-:10508000C8700DE011202549087026484078022894
-:1050900006D1802022490968C870FFF71BFDABE5E7
-:1050A0001E48007888BB022D01D1022F07D1032DA5
-:1050B00001D1032F03D1052D07D1012F05D17F2069
-:1050C00016490870FFF706FD26E01648007900EA49
-:1050D000090020B91348407900EA0A0028B13320BA
-:1050E0000E490870FFF7F6FC16E005200E4908800F
-:1050F00020780E4A105C00EB40000D4A02EB800065
-:10510000816808480830884706E0FFE70020044926
-:105110000968C870FFF7DEFC00BF6DE55000002095
-:10512000480000205801002052000020305900089B
-:105130009458000810B504462046FCF725FF10BD22
-:10514000014948717047000058010020014908706A
-:1051500070470000500000200149087170470000AE
-:105160005801002070B5044612488068057811483F
-:105170008068407800F07F06012C03D1012000F008
-:1051800047F904E0102D02D1304600F041F9FFF755
-:10519000ABFB01280CD10020FBF7DAFEFBF778FF10
-:1051A000012805D1FBF7A6FE10B90A2002490870B4
-:1051B00070BD000058010020440000200149087122
-:1051C000704700005801002001490968C870704705
-:1051D0004800002010B50348007908B1FFF74AFAEB
-:1051E00010BD00004800002010B5FBF711FFFFF7CD
-:1051F0004DF910BD10B500F02BF810BD70B5044688
-:105200002068457825F080052679012E03D11320EA
-:10521000FFF79CFF19E06DB9022E05D01320FFF7B0
-:1052200095FFFFF79FFC10E00020A1684870022066
-:10523000A0810AE01220FFF789FFFFF793FCFFF738
-:1052400009FA10B18020FFF7BFFFFFF743FC70BDE4
-:1052500010B56548008818B364480078012806D165
-:105260000020624908704FF4FA705F490880604876
-:105270000079A8B95C480088401E5B490880084650
-:10528000008868B9002008800120FFF76BFF002428
-:1052900004E0002057490855601CC4B2022CF8DB1A
-:1052A0005348007900F00C00C0B153480088A8B101
-:1052B00051480088401E504908800846008868B957
-:1052C0004B480068807830B90320494909688870E4
-:1052D00000F0CEF802E0012047490880002455E0A4
-:1052E000464830F81400B0F57A7F06DB4348001DCD
-:1052F00030F81400B0F57A7F46DA4048001D30F8E7
-:105300001400401C81B23D48001D20F81410001FFD
-:1053100030F81400401C394921F8140001F108004C
-:10532000005D012810D1084630F81400B0F57A7FEE
-:105330002ADB002021F814000021304808300155F4
-:1053400000202F4908551FE02C480A30005D012835
-:105350001AD12A48001D30F81400B0F57A7F13DB0B
-:105360000020274908550021244808300155001F16
-:1053700020F81410801D0155801C005D032803DBFC
-:1053800002211E480C300155601CC4B2022CA7DB60
-:105390001C480078002809DD1A480078401E194989
-:1053A00008700846007808B9FAF794FF16480078A4
-:1053B000002809DD14480078401E1349087008468B
-:1053C000007808B9FAF786FF10480078002809DD50
-:1053D0000E480078401E0D4908700846007808B94C
-:1053E000FAF778FF10BD000054000020560000209E
-:1053F00048000020C000002052000020702600203D
-:10540000BD00002044000020450000204600002090
-:1054100010B50446FFF768FA01280AD1FFF7CEFE5F
-:1054200004F07F00012810D04FF4FA700B49088077
-:105430000BE004F07F00012807D1FFF7BFFE012039
-:10544000FFF77EFE0020054908800548047004F03F
-:105450007F00012801D1FBF7AFFC10BD54000020F4
-:105460005801002010B504462046FCF78BFF10BD04
-:1054700010B506490648016103218182083000F019
-:105480000BF84FF4FA700349088010BD700100203A
-:10549000580100205200002070B5044608480068FA
-:1054A000C078802805D0A189A068FEF747FA054694
-:1054B00002E00025FFF756FB284600F003F870BD18
-:1054C0004800002070B504460CB1032000E0002025
-:1054D000054629460148FFF72FFA70BD5801002004
-:1054E00010B50320FFF7EEFF002010BD10B50446F5
-:1054F0002046FDF76FF910BD00BFFEE7002114E064
-:10550000084608220BE00B4B1B68034023B10A4BF3
-:105510001B6883EA500000E04008531EDAB2002AFC
-:10552000F1DC064B43F82100491C054B1B689942EE
-:10553000E6D37047DC000020E00000208026002039
-:10554000D000002002E008C8121F08C1002AFAD1CA
-:1055500070477047002001E001C1121F002AFBD1F3
-:105560007047000008B501210820FEF7C5FC0320A4
-:105570008DF8020014208DF803004FF48060ADF820
-:10558000000069460D48FDF7A4F903208DF80200DC
-:105590004FF40060ADF8000014208DF80300694658
-:1055A0000648FDF796F94FF480610448FDF766FA66
-:1055B0004FF400610148FDF761FA08BD000C01409D
-:1055C000022800DB70470121024A02F8301000BFB8
-:1055D000F8E70000FC000020022803DA074911F870
-:1055E000301001B970470121044A02F8301000213F
-:1055F00002EBC002517000BFF4E70000FC00002085
-:105600000146022908DA064810F8310020B10448A2
-:1056100010F83100032801D1002070470120FCE779
-:10562000FC00002010B5FFF79DFF10BD2DE9F041F3
-:1056300007460C461646FDF789FBA020FDF758FBF0
-:10564000FDF7B2FB00B130E0A046E11704EB1161B9
-:10565000C1F30720FDF74CFBFDF7A6FB00B124E0EA
-:10566000E0B2FDF745FBFDF79FFB00B11DE0FDF744
-:105670006DFBA120FDF73CFBFDF796FB00B114E0AC
-:1056800000250BE0711EA94201D0012100E000219C
-:105690000846FDF703FB7855681C85B2B542F1DB7F
-:1056A000FDF76EFB0120BDE8F081FDF769FB0020EE
-:1056B000F9E70000014802490860704700F0002047
-:1056C0002800002003480068006810B1002001494C
-:1056D0000860704728000020002001E0411C88B2CB
-:1056E0003C28FBDB7047000086B0FEF799FEFAF716
-:1056F000E7FDFEF75DFE01A8FEF70EFCFEF78BFB53
-:10570000FEF7C6FAFFF78EFFFBF7C0FBFAF736FE8F
-:105710004FF400712548FDF7AFF9FBF7B7FBFBF736
-:10572000C1FE41E0FEF7EAFE21480078012805D1DC
-:1057300000201F49087000F03DF835E01C48407813
-:10574000012803D100201A4948702DE018488078BC
-:10575000012805D1002016498870FFF745FD23E098
-:105760001348C078012803D100201149C8701BE0FC
-:105770000F480079012803D100200D49087113E07A
-:105780000B484079012803D10020094948710BE0FA
-:105790000748C079012807D100200549C8714FF496
-:1057A00000710248FDF768F9BCE70000000C0140F9
-:1057B0000C01002010B5FBF7DDFB10BD000102035A
-:1057C00004050607080C10141820304000010203DD
-:1057D0000405060708090909090A0A0A0A0B0B0B3E
-:1057E0000B0C0C0C0C0D0D0D0D0D0D0D0D0E0E0EEC
-:1057F0000E0E0E0E0E0E0E0E0E0E0E0E0E0F0F0FC6
-:105800000F0F0F0F0F0F0F0F0F0F0F0F0F39323139
-:10581000343830312D4446303200000000000000A2
-:105820000056480012566E00000056480012566E90
-:1058300000000001170B10001B0700000008040007
-:105840000000020000000000000000000000000056
-:10585000292E0008180100200B070000FF07000098
-:1058600000000800DF070000FF070000000008003C
-:105870002D010000FF0700000000080000000000EC
-:105880000000000000000000000000000000000018
-:10589000000000000206031000000000A9470008F5
-:1058A0000206031000000000A148000803060300E0
-:1058B00000000000414B0008060501000000000048
-:1058C000355100080303031000000000694600087A
-:1058D0001402010001000000ED540008060501005B
-:1058E00000000000754B00080B02010001000000E1
-:1058F0004D4B0008FF020100010000006554000844
-:105900000102010001000000594B000802060310CB
-:1059100000000000FD510008020303100000000019
-:1059200075470008000000000000000000000000B3
-:10593000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77
-:105940000001FFFFFFFFFFFFFFFFFFFFFFFFFFFF64
-:10595000FFFF02FFFFFFFF0304FFFFFFFFFF05FF45
-:10596000FF06FFFF07FF0809FFFFFFFFFFFF0AFF1A
-:10597000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF37
-:10598000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF27
-:10599000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF17
-:1059A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF07
-:1059B000FFFFFFFFFF0B000094F100003D150020EA
-:1059C00009010000FFFF000095F10000B500002074
-:1059D00006010000FFFF000093F10000B00000206E
-:1059E00005010000FFFF00008CF1000046150020BB
-:1059F00013010000FFFF000080F1000034150020BB
-:105A000009010000FFFF0000DD160008FD16000878
-:105A1000BD16000815170008191700083E53E17B52
-:105A2000405A000800000020FC0000004455000817
-:105A30003C5B0008FC000020AC310000545500081D
-:105A40000000000001020304010203040607080924
-:105A50000204060800A24A04000000000000000042
-:105A6000010203040607080900000000000000000E
-:105A70000000000000000000000000000000000026
-:105A80000000000000000000000000000000000016
-:105A90000000000000000000000000000000000006
-:105AA00000000000000000000000000018010020BD
-:105AB000D5490008F5490008C55400088149000887
-:105AC000E1540008814700080000000000000000C9
-:105AD00000000000000000000000000000000000C6
-:105AE00000000000000000000000000000000000B6
-:105AF00000000000000000000000000000000000A6
-:105B00000000000000000000000000000000000095
-:105B1000000100000800000000000000000000007C
-:105B20000000000000000000000000000000000075
-:0C5B300000000000000000000000000069
-:04000005080001519D
-:00000001FF
diff --git a/boot_project/Objects/hongri_boot.htm b/boot_project/Objects/hongri_boot.htm
deleted file mode 100644
index 18707ae..0000000
--- a/boot_project/Objects/hongri_boot.htm
+++ /dev/null
@@ -1,1916 +0,0 @@
-
-
-Static Call Graph - [.\Objects\hongri_boot.axf]
-
-Static Call Graph for image .\Objects\hongri_boot.axf
-
#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Mon Nov 04 19:26:00 2024
-
-
Maximum Stack Usage = 384 bytes + Unknown(Cycles, Untraceable Function Pointers)
-Call chain for Maximum Stack Depth:
-CAN2_RX1_IRQHandler ⇒ APP_CAN_FifoMessageReceive ⇒ APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
-Mutually Recursive functions
-
ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
-
-
-
-Function Pointers
-
- - ADC1_2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_RX0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_RX1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_SCE_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN1_TX_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_RX0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_RX1_IRQHandler from can2.o(i.CAN2_RX1_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_SCE_IRQHandler from can2.o(i.CAN2_SCE_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
-
- CAN2_TX_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel6_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA1_Channel7_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DMA2_Channel5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- Diag_Read_ECUSoftwareCode_F193 from diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F193) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_ECUSoftwareCode_F194 from diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F194) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_ECUSoftwareCode_F195 from diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F195) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_F18C from diag_eeprom_c301.o(i.Diag_Read_F18C) referenced from diag_appl_c301.o(.constdata)
-
- Diag_Read_FBLVersionInformation from diag_eeprom_c301.o(i.Diag_Read_FBLVersionInformation) referenced from diag_appl_c301.o(.constdata)
-
- ETH_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- ETH_WKUP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI15_10_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- EXTI9_5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- FLASH_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C1_ER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C1_EV_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C2_ER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- I2C2_EV_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- ISO15765_DrvConfirmation from iso15765-2.o(i.ISO15765_DrvConfirmation) referenced from canconfig_c301.o(.constdata)
-
- MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- OTG_FS_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- OTG_FS_WKUP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- PVD_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- RCC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- RTCAlarm_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- RTC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- Reset_Handler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SPI1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SPI2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SPI3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- SysTick_Handler from dev_sys.o(i.SysTick_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_cl.o(.text)
-
- TAMPER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_BRK_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_CC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM1_UP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM6_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- TIM7_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- UART4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- UART5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- USART1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- USART2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- USART3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- Uds_CommunicationControl from uds.o(i.Uds_CommunicationControl) referenced from canconfig_c301.o(.constdata)
-
- Uds_ControlDTCSetting from uds.o(i.Uds_ControlDTCSetting) referenced from canconfig_c301.o(.constdata)
-
- Uds_CopyToCAN from uds.o(i.Uds_CopyToCAN) referenced from iso15765-2_entry.o(.data)
-
- Uds_DiagControlSession from uds.o(i.Uds_DiagControlSession) referenced from canconfig_c301.o(.constdata)
-
- Uds_ECUReset from uds.o(i.Uds_ECUReset) referenced from canconfig_c301.o(.constdata)
-
- Uds_PhysFuncGetBuffer from uds.o(i.Uds_PhysFuncGetBuffer) referenced from iso15765-2_entry.o(.data)
-
- Uds_PhysReqInd from uds.o(i.Uds_PhysReqInd) referenced from iso15765-2_entry.o(.data)
-
- Uds_PhysRxErrorIndication from uds.o(i.Uds_PhysRxErrorIndication) referenced from iso15765-2_entry.o(.data)
-
- Uds_ReadDataByIdentifier from uds.o(i.Uds_ReadDataByIdentifier) referenced from canconfig_c301.o(.constdata)
-
- Uds_RequestDownload from uds.o(i.Uds_RequestDownload) referenced from canconfig_c301.o(.constdata)
-
- Uds_RequestTransferExit from uds.o(i.Uds_RequestTransferExit) referenced from canconfig_c301.o(.constdata)
-
- Uds_RoutineControl from uds.o(i.Uds_RoutineControl) referenced from canconfig_c301.o(.constdata)
-
- Uds_SecurityAccess from uds.o(i.Uds_SecurityAccess) referenced from canconfig_c301.o(.constdata)
-
- Uds_TesterPresent from uds.o(i.Uds_TesterPresent) referenced from canconfig_c301.o(.constdata)
-
- Uds_TransferData from uds.o(i.Uds_TransferData) referenced from canconfig_c301.o(.constdata)
-
- Uds_TxConfirmation from uds.o(i.Uds_TxConfirmation) referenced from iso15765-2_entry.o(.data)
-
- Uds_TxErrorIndication from uds.o(i.Uds_TxErrorIndication) referenced from iso15765-2_entry.o(.data)
-
- Uds_WriteDataByIdentifier from uds.o(i.Uds_WriteDataByIdentifier) referenced from canconfig_c301.o(.constdata)
-
- UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
-
- WWDG_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
-
- __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_stm32f10x_cl.o(.text)
-
- main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-
-Global Symbols
-
-__main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(.text)
-
-_main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
-
-
_main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Calls]
-
-__main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
-
[Called By]
-
-_main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
-
-
_main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
-
-
_main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
-
-
__rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
-
-
__rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
-
-
__get_PSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__set_PSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__get_MSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__set_MSP (Thumb, 6 bytes, Stack size 0 bytes, core_cm3.o(.emb_text))
-
[Called By]
-
-__REV16 (Thumb, 4 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
__REVSH (Thumb, 4 bytes, Stack size 0 bytes, core_cm3.o(.emb_text), UNUSED)
-
-
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
-
-CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-DMA2_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-__aeabi_memcpy (Thumb, 36 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED)
-
-
__aeabi_memcpy4 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text))
-
[Called By]
-
-__aeabi_memcpy8 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED)
-
-
__aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
[Called By]
- >> _memset$wrapper
-
- >> __aeabi_memclr
-
-
-__aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
__aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
__aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
[Calls]
-
-__aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
-
[Called By]
- >> CAN2_RX1_IRQHandler
-
- >> IF_CAN_CopyDataAndStartTx
-
-
-__aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
-
-
_memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
-
[Calls]
-
-__scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
-
[Calls]
- >> __main_after_scatterload
-
-
[Called By]
-
-__scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
-
-
APP_CAN_FifoMessageReceive (Thumb, 72 bytes, Stack size 32 bytes, app_can.o(i.APP_CAN_FifoMessageReceive))
-
[Stack]
- Max Depth = 352
- Call Chain = APP_CAN_FifoMessageReceive ⇒ APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> APP_CAN_MessageTypeHandle
-
-
[Called By]
-
-BSP_BKP_Init (Thumb, 20 bytes, Stack size 8 bytes, main.o(i.BSP_BKP_Init))
-
[Stack]
- Max Depth = 8
- Call Chain = BSP_BKP_Init
-
-
[Calls]- >> RCC_APB1PeriphClockCmd
-
- >> PWR_BackupAccessCmd
-
-
[Called By]
-
-BSP_vSystemReset (Thumb, 30 bytes, Stack size 0 bytes, app_can.o(i.BSP_vSystemReset))
-
[Called By]
- >> Uds_TimerTask
-
- >> Can_Task
-
-
-BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-Bzip2_Finish (Thumb, 12 bytes, Stack size 0 bytes, uds_sa_c301.o(i.Bzip2_Finish))
-
[Called By]
- >> Diag_RequestTransferExit
-
-
-Bzip2_Init (Thumb, 26 bytes, Stack size 4 bytes, uds_sa_c301.o(i.Bzip2_Init))
-
[Stack]
- Max Depth = 4
- Call Chain = Bzip2_Init
-
-
[Calls]
-
[Called By]- >> Diag_RequestDownload
-
-
-Bzip2_Start (Thumb, 10 bytes, Stack size 0 bytes, uds_sa_c301.o(i.Bzip2_Start))
-
[Called By]
- >> Diag_RequestDownload
-
-
-Bzip2_Update (Thumb, 44 bytes, Stack size 12 bytes, uds_sa_c301.o(i.Bzip2_Update))
-
[Stack]
- Max Depth = 12
- Call Chain = Bzip2_Update
-
-
[Called By]
-
-CAN2_Mode_Init (Thumb, 308 bytes, Stack size 40 bytes, can2.o(i.CAN2_Mode_Init))
-
[Stack]
- Max Depth = 64
- Call Chain = CAN2_Mode_Init ⇒ GPIO_Init
-
-
[Calls]- >> CAN_Init
-
- >> CAN_ITConfig
-
- >> CAN_FilterInit
-
- >> RCC_APB2PeriphClockCmd
-
- >> RCC_APB1PeriphClockCmd
-
- >> GPIO_Init
-
- >> NVIC_Init
-
- >> can_bus_open_hook
-
-
[Called By]
-
-CAN2_RX1_IRQHandler (Thumb, 44 bytes, Stack size 32 bytes, can2.o(i.CAN2_RX1_IRQHandler))
-
[Stack]
- Max Depth = 384
- Call Chain = CAN2_RX1_IRQHandler ⇒ APP_CAN_FifoMessageReceive ⇒ APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_Receive
-
- >> APP_CAN_FifoMessageReceive
-
- >> can_bus_ready_hook
-
- >> __aeabi_memclr4
-
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
-
-CAN2_SCE_IRQHandler (Thumb, 186 bytes, Stack size 8 bytes, can2.o(i.CAN2_SCE_IRQHandler))
-
[Stack]
- Max Depth = 24
- Call Chain = CAN2_SCE_IRQHandler ⇒ CAN_GetITStatus
-
-
[Calls]- >> CAN_GetITStatus
-
- >> CAN_GetFlagStatus
-
- >> CAN_DeInit
-
- >> CAN_ClearITPendingBit
-
- >> CAN_ClearFlag
-
- >> TickOut
-
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
-
-CAN_ClearFlag (Thumb, 52 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ClearFlag))
-
[Called By]
-
-CAN_ClearITPendingBit (Thumb, 162 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ClearITPendingBit))
-
[Called By]
-
-CAN_DeInit (Thumb, 50 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_DeInit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_DeInit
-
-
[Calls]- >> RCC_APB1PeriphResetCmd
-
-
[Called By]
-
-CAN_FilterInit (Thumb, 258 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_FilterInit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_FilterInit
-
-
[Called By]
-
-CAN_GetFlagStatus (Thumb, 120 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_GetFlagStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_GetFlagStatus
-
-
[Called By]
-
-CAN_GetITStatus (Thumb, 284 bytes, Stack size 16 bytes, stm32f10x_can.o(i.CAN_GetITStatus))
-
[Stack]
- Max Depth = 16
- Call Chain = CAN_GetITStatus
-
-
[Calls]
-
[Called By]
-
-CAN_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ITConfig))
-
[Called By]
-
-CAN_Init (Thumb, 276 bytes, Stack size 12 bytes, stm32f10x_can.o(i.CAN_Init))
-
[Stack]
- Max Depth = 12
- Call Chain = CAN_Init
-
-
[Called By]
-
-CAN_Receive (Thumb, 240 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_Receive))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Receive
-
-
[Called By]
-
-CAN_Transmit (Thumb, 294 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_Transmit))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_Transmit
-
-
[Called By]
-
-CAN_TransmitStatus (Thumb, 138 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_TransmitStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = CAN_TransmitStatus
-
-
[Called By]
-
-Can2_Send_Message (Thumb, 96 bytes, Stack size 48 bytes, can2.o(i.Can2_Send_Message))
-
[Stack]
- Max Depth = 56
- Call Chain = Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> CAN_TransmitStatus
-
- >> CAN_Transmit
-
- >> can_bus_send_ready
-
- >> __aeabi_memcpy4
-
-
[Called By]
-
-CanExt_CanTransShutdown (Thumb, 10 bytes, Stack size 8 bytes, app_can.o(i.CanExt_CanTransShutdown))
-
[Stack]
- Max Depth = 16
- Call Chain = CanExt_CanTransShutdown ⇒ CanTrans_GoToSleep
-
-
[Calls]
-
[Called By]
-
-CanTask_BusErrorDetection (Thumb, 2 bytes, Stack size 0 bytes, app_can.o(i.CanTask_BusErrorDetection))
-
[Called By]
- >> CanTask_TimerProcess
-
-
-CanTask_FBLInit (Thumb, 196 bytes, Stack size 0 bytes, app_can.o(i.CanTask_FBLInit))
-
[Called By]
- >> Uds_TransSessionType
-
- >> CanTask_InitProcess
-
-
-CanTask_GetSaRandom (Thumb, 6 bytes, Stack size 0 bytes, app_can.o(i.CanTask_GetSaRandom))
-
[Called By]
-
-CanTask_InitProcess (Thumb, 80 bytes, Stack size 8 bytes, app_can.o(i.CanTask_InitProcess))
-
[Stack]
- Max Depth = 32
- Call Chain = CanTask_InitProcess ⇒ ISO15765_InitPowerOn ⇒ ISO15765_Init ⇒ ISO15765_TxInit
-
-
[Calls]- >> IF_CAN_IsOnLine
-
- >> CanTrans_Init
-
- >> ISO15765_InitPowerOn
-
- >> CanTask_FBLInit
-
- >> Uds_PowerOnInit
-
- >> IF_CAN_InitLoaclStatus
-
-
[Called By]
-
-CanTask_IsAppBeenErased (Thumb, 40 bytes, Stack size 0 bytes, app_can.o(i.CanTask_IsAppBeenErased))
-
[Called By]
-
-CanTask_SetStayInBootFlagValue (Thumb, 6 bytes, Stack size 0 bytes, app_can.o(i.CanTask_SetStayInBootFlagValue))
-
[Called By]
- >> Uds_DiagControlSession
-
- >> Uds_SetState
-
-
-CanTask_UdsStateProcess (Thumb, 16 bytes, Stack size 8 bytes, app_can.o(i.CanTask_UdsStateProcess))
-
[Stack]
- Max Depth = 112
- Call Chain = CanTask_UdsStateProcess ⇒ Uds_StateTask ⇒ Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> uds_SysTick_Process_1ms
-
-
-CanTrans_GoToNormal (Thumb, 38 bytes, Stack size 8 bytes, can_transceiver.o(i.CanTrans_GoToNormal))
-
[Stack]
- Max Depth = 8
- Call Chain = CanTrans_GoToNormal
-
-
[Calls]
-
[Called By]
-
-CanTrans_GoToSleep (Thumb, 50 bytes, Stack size 8 bytes, can_transceiver.o(i.CanTrans_GoToSleep))
-
[Stack]
- Max Depth = 8
- Call Chain = CanTrans_GoToSleep
-
-
[Calls]- >> GPIO_SetBits
-
- >> GPIO_ResetBits
-
- >> CanTrans_Delay
-
-
[Called By]- >> CanExt_CanTransShutdown
-
-
-CanTrans_Init (Thumb, 10 bytes, Stack size 8 bytes, can_transceiver.o(i.CanTrans_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = CanTrans_Init ⇒ CanTrans_GoToNormal
-
-
[Calls]
-
[Called By]
-
-Can_Task (Thumb, 68 bytes, Stack size 8 bytes, app_can.o(i.Can_Task))
-
[Stack]
- Max Depth = 320
- Call Chain = Can_Task ⇒ CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> BSP_vSystemReset
-
- >> CanExt_CanTransShutdown
-
- >> CanTask_TimerProcess
-
-
[Called By]- >> Uds_SysTick_Process_10ms
-
-
-DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-Diag_AppDataInit (Thumb, 8 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_AppDataInit))
-
[Called By]
- >> Uds_PowerOnInit
-
- >> Uds_DiagControlSession
-
-
-Diag_CheckTransmitSequence (Thumb, 20 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_CheckTransmitSequence))
-
[Stack]
- Max Depth = 16
- Call Chain = Diag_CheckTransmitSequence
-
-
[Calls]
-
[Called By]
-
-Diag_CheckValidApp1 (Thumb, 54 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_CheckValidApp1))
-
[Stack]
- Max Depth = 64
- Call Chain = Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> Diag_CheckValidApplication
-
- >> Uds_SetState
-
-
-Diag_CheckValidApplication (Thumb, 24 bytes, Stack size 8 bytes, diag_appl_c301.o(i.Diag_CheckValidApplication))
-
[Stack]
- Max Depth = 72
- Call Chain = Diag_CheckValidApplication ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]
-
-Diag_CheckVerifyUpgradePacket (Thumb, 22 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CheckVerifyUpgradePacket))
-
[Called By]
-
-Diag_CheckWriteDIDRange (Thumb, 48 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CheckWriteDIDRange))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
-
-Diag_ClrAPP1UpdateMark (Thumb, 72 bytes, Stack size 16 bytes, diag_eeprom_c301.o(i.Diag_ClrAPP1UpdateMark))
-
[Stack]
- Max Depth = 16
- Call Chain = Diag_ClrAPP1UpdateMark
-
-
[Calls]- >> flashdnit
-
- >> flashInit
-
-
[Called By]
-
-Diag_ClrEepromUpdateMark (Thumb, 20 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_ClrEepromUpdateMark))
-
[Called By]
-
-Diag_CommunicationControl (Thumb, 178 bytes, Stack size 24 bytes, diag_appl_c301.o(i.Diag_CommunicationControl))
-
[Stack]
- Max Depth = 32
- Call Chain = Diag_CommunicationControl ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_CommEnable
-
- >> Diag_CommDisable
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_CommunicationControl
-
-
-Diag_ControlDTCSetting (Thumb, 100 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_ControlDTCSetting))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_ControlDTCSetting ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_ControlDTCSetting
-
-
-Diag_DataCalcCRC (Thumb, 96 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_DataCalcCRC))
-
[Stack]
- Max Depth = 16
- Call Chain = Diag_DataCalcCRC
-
-
[Called By]
-
-Diag_DataProgram (Thumb, 94 bytes, Stack size 24 bytes, diag_appl_c301.o(i.Diag_DataProgram))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_DataProgram
-
-
[Calls]- >> flashdnit
-
- >> flashInit
-
-
[Called By]
-
-Diag_EcuReset (Thumb, 132 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_EcuReset))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_EcuReset ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]
-
-Diag_FlashCalcCRC (Thumb, 118 bytes, Stack size 40 bytes, diag_appl_c301.o(i.Diag_FlashCalcCRC))
-
[Stack]
- Max Depth = 328
- Call Chain = Diag_FlashCalcCRC ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Uds_ForceTransmitResPending
-
-
[Called By]- >> Diag_RequestTransferExit
-
-
-Diag_HndUpdataEV (Thumb, 2 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_HndUpdataEV))
-
[Called By]
-
-Diag_MemCopy (Thumb, 22 bytes, Stack size 8 bytes, diag_eeprom_c301.o(i.Diag_MemCopy))
-
[Stack]
- Max Depth = 8
- Call Chain = Diag_MemCopy
-
-
[Called By]- >> Diag_WriteDataByIdentifier
-
- >> Uds_ContextTask
-
-
-Diag_MemCpy (Thumb, 20 bytes, Stack size 8 bytes, diag_appl_c301.o(i.Diag_MemCpy))
-
[Stack]
- Max Depth = 8
- Call Chain = Diag_MemCpy
-
-
[Called By]
-
-Diag_ProgramFailedDataInit (Thumb, 120 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_ProgramFailedDataInit))
-
[Called By]
-
-Diag_RamWrite (Thumb, 20 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_RamWrite))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_RamWrite ⇒ Diag_MemCpy
-
-
[Calls]
-
[Called By]
-
-Diag_ReadDataByIdentifier (Thumb, 340 bytes, Stack size 144 bytes, diag_appl_c301.o(i.Diag_ReadDataByIdentifier))
-
[Stack]
- Max Depth = 152
- Call Chain = Diag_ReadDataByIdentifier ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetNRC
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_ReadDataByIdentifier
-
-
-Diag_Read_ECUSoftwareCode_F193 (Thumb, 22 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F193))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_ECUSoftwareCode_F194 (Thumb, 22 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F194))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_ECUSoftwareCode_F195 (Thumb, 20 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_ECUSoftwareCode_F195))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_F18C (Thumb, 2 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_F18C))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_Read_FBLVersionInformation (Thumb, 22 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_Read_FBLVersionInformation))
-
[Address Reference Count : 1]
- diag_appl_c301.o(.constdata)
-
-Diag_RequestDownload (Thumb, 832 bytes, Stack size 32 bytes, diag_appl_c301.o(i.Diag_RequestDownload))
-
[Stack]
- Max Depth = 40
- Call Chain = Diag_RequestDownload ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Bzip2_Start
-
- >> Bzip2_Init
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetNRC
-
-
[Called By]
-
-Diag_RequestEraseFlash (Thumb, 72 bytes, Stack size 24 bytes, diag_appl_c301.o(i.Diag_RequestEraseFlash))
-
[Stack]
- Max Depth = 24
- Call Chain = Diag_RequestEraseFlash
-
-
[Calls]- >> flashdnit
-
- >> flashInit
-
-
[Called By]
-
-Diag_RequestTransferExit (Thumb, 298 bytes, Stack size 16 bytes, diag_appl_c301.o(i.Diag_RequestTransferExit))
-
[Stack]
- Max Depth = 344
- Call Chain = Diag_RequestTransferExit ⇒ Diag_FlashCalcCRC ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Bzip2_Finish
-
- >> Diag_FlashCalcCRC
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
-
[Called By]- >> Uds_RequestTransferExit
-
-
-Diag_RoutineControl (Thumb, 882 bytes, Stack size 48 bytes, diag_appl_c301.o(i.Diag_RoutineControl))
-
[Stack]
- Max Depth = 336
- Call Chain = Diag_RoutineControl ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Diag_RequestEraseFlash
-
- >> Diag_CheckVerifyUpgradePacket
-
- >> Diag_CheckValidApplication
-
- >> Diag_CheckTransmitSequence
-
- >> Diag_SetEepromAppErasureMark
-
- >> Diag_ClrEepromUpdateMark
-
- >> Diag_ClrAPP1UpdateMark
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetCurSessionAccessStatus
-
- >> Uds_ForceTransmitResPending
-
- >> Uds_CheckAdrrType
-
-
[Called By]
-
-Diag_SecurityAccess (Thumb, 968 bytes, Stack size 40 bytes, diag_appl_c301.o(i.Diag_SecurityAccess))
-
[Stack]
- Max Depth = 64
- Call Chain = Diag_SecurityAccess ⇒ SA_Random
-
-
[Calls]- >> SA_GenerateKeyFBL
-
- >> SA_GenerateKey
-
- >> SA_Compare
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetProtect
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_GetCurSessionState
-
- >> Uds_CheckAdrrType
-
- >> SA_Random
-
-
[Called By]
-
-Diag_SetEepromAppErasureMark (Thumb, 20 bytes, Stack size 0 bytes, diag_eeprom_c301.o(i.Diag_SetEepromAppErasureMark))
-
[Called By]
-
-Diag_TransferData (Thumb, 1098 bytes, Stack size 32 bytes, diag_appl_c301.o(i.Diag_TransferData))
-
[Stack]
- Max Depth = 56
- Call Chain = Diag_TransferData ⇒ Diag_RamWrite ⇒ Diag_MemCpy
-
-
[Calls]- >> Bzip2_Update
-
- >> Diag_RamWrite
-
- >> Diag_ProgramFailedDataInit
-
- >> Diag_DataProgram
-
- >> Diag_DataCalcCRC
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
-
[Called By]
-
-Diag_WriteDataByIdentifier (Thumb, 238 bytes, Stack size 32 bytes, diag_appl_c301.o(i.Diag_WriteDataByIdentifier))
-
[Stack]
- Max Depth = 40
- Call Chain = Diag_WriteDataByIdentifier ⇒ Diag_MemCopy
-
-
[Calls]- >> EED_WriteDID
-
- >> Diag_CheckWriteDIDRange
-
- >> Diag_MemCopy
-
- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Called By]- >> Uds_WriteDataByIdentifier
-
-
-EED_WriteDID (Thumb, 6 bytes, Stack size 0 bytes, app_can.o(i.EED_WriteDID))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
-
-GPIO_Init (Thumb, 278 bytes, Stack size 24 bytes, stm32f10x_gpio.o(i.GPIO_Init))
-
[Stack]
- Max Depth = 24
- Call Chain = GPIO_Init
-
-
[Called By]- >> CAN2_Mode_Init
-
- >> bsp_InitI2C
-
- >> LED_Init
-
-
-GPIO_PinRemapConfig (Thumb, 138 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_PinRemapConfig))
-
[Stack]
- Max Depth = 20
- Call Chain = GPIO_PinRemapConfig
-
-
[Called By]
-
-GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits))
-
[Called By]
- >> LED_Init
-
- >> CanTrans_GoToSleep
-
- >> main
-
-
-GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits))
-
[Called By]
- >> bsp_InitI2C
-
- >> LED_Init
-
- >> CanTrans_GoToSleep
-
- >> CanTrans_GoToNormal
-
-
-GetCrc32Chk (Thumb, 6 bytes, Stack size 0 bytes, uds_sa_c301.o(i.GetCrc32Chk))
-
[Called By]
- >> Diag_CheckTransmitSequence
-
-
-HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-IF_CAN_CancelTransmitMsg (Thumb, 2 bytes, Stack size 0 bytes, app_can.o(i.IF_CAN_CancelTransmitMsg))
-
[Called By]
- >> ISO15765_Precopy
-
- >> ISO15765_TxInit
-
- >> ISO15765_RxInit
-
-
-IF_CAN_InitLoaclStatus (Thumb, 24 bytes, Stack size 8 bytes, app_can.o(i.IF_CAN_InitLoaclStatus))
-
[Stack]
- Max Depth = 8
- Call Chain = IF_CAN_InitLoaclStatus
-
-
[Calls]
-
[Called By]
-
-IF_CAN_IsOnLine (Thumb, 20 bytes, Stack size 0 bytes, app_can.o(i.IF_CAN_IsOnLine))
-
[Called By]
- >> IF_CAN_InitLoaclStatus
-
- >> CanTask_InitProcess
-
-
-IF_CAN_SendCanData (Thumb, 160 bytes, Stack size 64 bytes, app_can.o(i.IF_CAN_SendCanData))
-
[Stack]
- Max Depth = 120
- Call Chain = IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> IF_CAN_CopyDataAndStartTx
-
-
-IF_CAN_TransmitMsg (Thumb, 46 bytes, Stack size 24 bytes, app_can.o(i.IF_CAN_TransmitMsg))
-
[Stack]
- Max Depth = 264
- Call Chain = IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> IF_CAN_CopyDataAndStartTx
-
-
[Called By]- >> ISO15765_CanTransmitMsg
-
- >> ISO15765_CanTransmitMsgWithDlc
-
-
-IIC_Ack (Thumb, 52 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Ack))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Ack
-
-
[Calls]
-
[Called By]
-
-IIC_NAck (Thumb, 42 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_NAck))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_NAck
-
-
[Calls]
-
[Called By]
-
-IIC_Read_Byte (Thumb, 80 bytes, Stack size 16 bytes, bsp_i2c_gpio.o(i.IIC_Read_Byte))
-
[Stack]
- Max Depth = 24
- Call Chain = IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> IIC_NAck
-
- >> IIC_Ack
-
- >> i2c_Delay
-
-
[Called By]
-
-IIC_Send_Byte (Thumb, 88 bytes, Stack size 16 bytes, bsp_i2c_gpio.o(i.IIC_Send_Byte))
-
[Stack]
- Max Depth = 16
- Call Chain = IIC_Send_Byte
-
-
[Calls]
-
[Called By]
-
-IIC_Start (Thumb, 48 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Start))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Start
-
-
[Calls]
-
[Called By]
-
-IIC_Stop (Thumb, 36 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Stop))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Stop
-
-
[Calls]
-
[Called By]
-
-IIC_Wait_Ack (Thumb, 62 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.IIC_Wait_Ack))
-
[Stack]
- Max Depth = 8
- Call Chain = IIC_Wait_Ack
-
-
[Calls]
-
[Called By]
-
-ISO15765_CanTransmitMsg (Thumb, 26 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_CanTransmitMsg))
-
[Stack]
- Max Depth = 272
- Call Chain = ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> ISO15765_TxStateTask
-
- >> ISO15765_RxStateTask
-
-
-ISO15765_CanTransmitMsgWithDlc (Thumb, 26 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_CanTransmitMsgWithDlc))
-
[Stack]
- Max Depth = 280
- Call Chain = ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> Uds_ForceTransmitResPending
-
-
-ISO15765_DrvConfirmation (Thumb, 22 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_DrvConfirmation))
-
[Stack]
- Max Depth = 16
- Call Chain = ISO15765_DrvConfirmation ⇒ ISO15765_TxFinishProcess
-
-
[Calls]- >> ISO15765_TxFinishProcess
-
- >> ISO15765_RxFinishProcess
-
-
[Called By]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-ISO15765_InitPowerOn (Thumb, 24 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_InitPowerOn))
-
[Stack]
- Max Depth = 24
- Call Chain = ISO15765_InitPowerOn ⇒ ISO15765_Init ⇒ ISO15765_TxInit
-
-
[Calls]
-
[Called By]
-
-ISO15765_Precopy (Thumb, 1534 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_Precopy))
-
[Stack]
- Max Depth = 304
- Call Chain = ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> IF_CAN_CancelTransmitMsg
-
- >> ISO15765_DrvConfirmation
-
- >> ISO15765_TxInit
-
- >> ISO15765_RxStateTask
-
- >> ISO15765_RxInit
-
- >> ISO15765_RxResetBus
-
-
[Called By]- >> APP_CAN_MessageTypeHandle
-
-
-ISO15765_RxResetBus (Thumb, 8 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_RxResetBus))
-
[Stack]
- Max Depth = 16
- Call Chain = ISO15765_RxResetBus ⇒ ISO15765_RxInit
-
-
[Calls]
-
[Called By]- >> ISO15765_Precopy
-
- >> Uds_PhysReqInd
-
-
-ISO15765_RxSetFCStatus (Thumb, 6 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_RxSetFCStatus))
-
[Called By]
- >> Uds_PhysFuncGetBuffer
-
-
-ISO15765_Task (Thumb, 12 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_Task))
-
[Stack]
- Max Depth = 304
- Call Chain = ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_TxTask
-
- >> ISO15765_RxTask
-
-
[Called By]- >> CanTask_TimerProcess
-
-
-ISO15765_Transmit (Thumb, 98 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_Transmit))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_Transmit
-
-
[Called By]- >> Uds_TransmitResponse
-
-
-LED_Init (Thumb, 368 bytes, Stack size 8 bytes, led.o(i.LED_Init))
-
[Stack]
- Max Depth = 32
- Call Chain = LED_Init ⇒ GPIO_Init
-
-
[Calls]- >> RCC_APB2PeriphClockCmd
-
- >> GPIO_SetBits
-
- >> GPIO_ResetBits
-
- >> GPIO_PinRemapConfig
-
- >> GPIO_Init
-
-
[Called By]
-
-MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-NVIC_Configuration (Thumb, 12 bytes, Stack size 8 bytes, dev_sys.o(i.NVIC_Configuration))
-
[Stack]
- Max Depth = 8
- Call Chain = NVIC_Configuration
-
-
[Calls]- >> NVIC_PriorityGroupConfig
-
-
[Called By]
-
-NVIC_Init (Thumb, 100 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = NVIC_Init
-
-
[Called By]
-
-NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
-
[Called By]
-
-PWR_BackupAccessCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_pwr.o(i.PWR_BackupAccessCmd))
-
[Called By]
-
-PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd))
-
[Called By]
- >> CAN2_Mode_Init
-
- >> BSP_BKP_Init
-
-
-RCC_APB1PeriphResetCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd))
-
[Called By]
-
-RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd))
-
[Called By]
- >> CAN2_Mode_Init
-
- >> bsp_InitI2C
-
- >> LED_Init
-
-
-RCC_GetClocksFreq (Thumb, 374 bytes, Stack size 24 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq))
-
[Stack]
- Max Depth = 24
- Call Chain = RCC_GetClocksFreq
-
-
[Called By]
-
-SA_Compare (Thumb, 36 bytes, Stack size 16 bytes, uds_sa_c301.o(i.SA_Compare))
-
[Stack]
- Max Depth = 16
- Call Chain = SA_Compare
-
-
[Called By]
-
-SA_GenerateKey (Thumb, 132 bytes, Stack size 20 bytes, uds_sa_c301.o(i.SA_GenerateKey))
-
[Stack]
- Max Depth = 20
- Call Chain = SA_GenerateKey
-
-
[Called By]
-
-SA_GenerateKeyFBL (Thumb, 130 bytes, Stack size 20 bytes, uds_sa_c301.o(i.SA_GenerateKeyFBL))
-
[Stack]
- Max Depth = 20
- Call Chain = SA_GenerateKeyFBL
-
-
[Called By]
-
-SA_Random (Thumb, 92 bytes, Stack size 24 bytes, uds_sa_c301.o(i.SA_Random))
-
[Stack]
- Max Depth = 24
- Call Chain = SA_Random
-
-
[Calls]
-
[Called By]
-
-SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SysTick_Handler (Thumb, 64 bytes, Stack size 0 bytes, dev_sys.o(i.SysTick_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-SysTick_Init (Thumb, 92 bytes, Stack size 12 bytes, dev_sys.o(i.SysTick_Init))
-
[Stack]
- Max Depth = 12
- Call Chain = SysTick_Init
-
-
[Called By]
-
-SystemInit (Thumb, 92 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
-
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
[Address Reference Count : 1]- startup_stm32f10x_cl.o(.text)
-
-TickOut (Thumb, 58 bytes, Stack size 0 bytes, dev_sys.o(i.TickOut))
-
[Called By]
-
-TimeTaskDispatch_Flag (Thumb, 318 bytes, Stack size 0 bytes, dev_sys.o(i.TimeTaskDispatch_Flag))
-
[Called By]
-
-UDS_ForcPendingReset (Thumb, 12 bytes, Stack size 0 bytes, uds.o(i.UDS_ForcPendingReset))
-
[Called By]
- >> Uds_ProcessFinished
-
- >> Uds_PowerOnInit
-
-
-Uds_CheckAdrrType (Thumb, 16 bytes, Stack size 0 bytes, uds.o(i.Uds_CheckAdrrType))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
-
-Uds_CommunicationControl (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_CommunicationControl))
-
[Stack]
- Max Depth = 40
- Call Chain = Uds_CommunicationControl ⇒ Diag_CommunicationControl ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_CommunicationControl
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ControlDTCSetting (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_ControlDTCSetting))
-
[Stack]
- Max Depth = 32
- Call Chain = Uds_ControlDTCSetting ⇒ Diag_ControlDTCSetting ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_ControlDTCSetting
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_CopyToCAN (Thumb, 22 bytes, Stack size 16 bytes, uds.o(i.Uds_CopyToCAN))
-
[Stack]
- Max Depth = 16
- Call Chain = Uds_CopyToCAN
-
-
[Calls]
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_DiagControlSession (Thumb, 232 bytes, Stack size 24 bytes, uds.o(i.Uds_DiagControlSession))
-
[Stack]
- Max Depth = 104
- Call Chain = Uds_DiagControlSession ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> Diag_AppDataInit
-
- >> CanTask_SetStayInBootFlagValue
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
- >> Uds_SetState
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ECUReset (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_ECUReset))
-
[Stack]
- Max Depth = 32
- Call Chain = Uds_ECUReset ⇒ Diag_EcuReset ⇒ Uds_ProcessFinished
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ForceTransmitResPending (Thumb, 42 bytes, Stack size 8 bytes, uds.o(i.Uds_ForceTransmitResPending))
-
[Stack]
- Max Depth = 288
- Call Chain = Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_CanTransmitMsgWithDlc
-
-
[Called By]- >> Diag_FlashCalcCRC
-
- >> Diag_RoutineControl
-
-
-Uds_GetCurSessionAccessStatus (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_GetCurSessionAccessStatus))
-
[Called By]
- >> Diag_RoutineControl
-
- >> CanTask_ReprogrammingCheck
-
-
-Uds_GetCurSessionState (Thumb, 10 bytes, Stack size 0 bytes, uds.o(i.Uds_GetCurSessionState))
-
[Called By]
- >> Diag_SecurityAccess
-
- >> Uds_TransSessionType
-
- >> Uds_SetState
-
- >> Uds_Scheduler
-
-
-Uds_GetNRC (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_GetNRC))
-
[Called By]
- >> Diag_RequestDownload
-
- >> Diag_ReadDataByIdentifier
-
-
-Uds_PhysFuncGetBuffer (Thumb, 78 bytes, Stack size 24 bytes, uds.o(i.Uds_PhysFuncGetBuffer))
-
[Stack]
- Max Depth = 24
- Call Chain = Uds_PhysFuncGetBuffer
-
-
[Calls]- >> ISO15765_RxSetFCStatus
-
- >> Uds_NetLayerStartRec
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_PhysReqInd (Thumb, 24 bytes, Stack size 8 bytes, uds.o(i.Uds_PhysReqInd))
-
[Stack]
- Max Depth = 24
- Call Chain = Uds_PhysReqInd ⇒ ISO15765_RxResetBus ⇒ ISO15765_RxInit
-
-
[Calls]- >> ISO15765_RxResetBus
-
- >> Uds_NetLayerEndOfRec
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_PhysRxErrorIndication (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_PhysRxErrorIndication))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_PhysRxErrorIndication
-
-
[Calls]- >> Uds_NetLayerEndOfRec
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_PowerOnInit (Thumb, 128 bytes, Stack size 8 bytes, uds.o(i.Uds_PowerOnInit))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_PowerOnInit
-
-
[Calls]- >> Diag_AppDataInit
-
- >> UDS_ForcPendingReset
-
-
[Called By]
-
-Uds_ProcessFinished (Thumb, 94 bytes, Stack size 8 bytes, uds.o(i.Uds_ProcessFinished))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_ProcessFinished
-
-
[Calls]- >> UDS_ForcPendingReset
-
-
[Called By]- >> Diag_WriteDataByIdentifier
-
- >> Diag_TransferData
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_RequestTransferExit
-
- >> Diag_RequestDownload
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
- >> Uds_Scheduler
-
-
-Uds_ReadDataByIdentifier (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_ReadDataByIdentifier))
-
[Stack]
- Max Depth = 160
- Call Chain = Uds_ReadDataByIdentifier ⇒ Diag_ReadDataByIdentifier ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_ReadDataByIdentifier
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_RequestDownload (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_RequestDownload))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_RequestDownload ⇒ Diag_RequestDownload ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Diag_RequestDownload
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_RequestTransferExit (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_RequestTransferExit))
-
[Stack]
- Max Depth = 352
- Call Chain = Uds_RequestTransferExit ⇒ Diag_RequestTransferExit ⇒ Diag_FlashCalcCRC ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Diag_RequestTransferExit
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_ResponseEnable (Thumb, 10 bytes, Stack size 0 bytes, uds.o(i.Uds_ResponseEnable))
-
[Called By]
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
- >> Uds_TransmitResponse
-
-
-Uds_RoutineControl (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_RoutineControl))
-
[Stack]
- Max Depth = 344
- Call Chain = Uds_RoutineControl ⇒ Diag_RoutineControl ⇒ Uds_ForceTransmitResPending ⇒ ISO15765_CanTransmitMsgWithDlc ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_SecurityAccess (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_SecurityAccess))
-
[Stack]
- Max Depth = 72
- Call Chain = Uds_SecurityAccess ⇒ Diag_SecurityAccess ⇒ SA_Random
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_SetNRC (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetNRC))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
- >> Diag_TransferData
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_RequestTransferExit
-
- >> Diag_RequestDownload
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
- >> Uds_DiagControlSession
-
-
-Uds_SetProtect (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetProtect))
-
[Called By]
-
-Uds_SetSupFuncEnableFlag (Thumb, 8 bytes, Stack size 0 bytes, uds.o(i.Uds_SetSupFuncEnableFlag))
-
[Called By]
- >> Diag_WriteDataByIdentifier
-
- >> Diag_SecurityAccess
-
- >> Diag_RoutineControl
-
- >> Diag_ReadDataByIdentifier
-
- >> Diag_EcuReset
-
- >> Diag_ControlDTCSetting
-
- >> Diag_CommunicationControl
-
- >> Uds_TesterPresent
-
-
-Uds_StateTask (Thumb, 14 bytes, Stack size 8 bytes, uds.o(i.Uds_StateTask))
-
[Stack]
- Max Depth = 104
- Call Chain = Uds_StateTask ⇒ Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> CanTask_UdsStateProcess
-
-
-Uds_Task (Thumb, 8 bytes, Stack size 8 bytes, uds.o(i.Uds_Task))
-
[Stack]
- Max Depth = 96
- Call Chain = Uds_Task ⇒ Uds_TimerTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]
-
[Called By]- >> CanTask_TimerProcess
-
-
-Uds_TesterPresent (Thumb, 84 bytes, Stack size 16 bytes, uds.o(i.Uds_TesterPresent))
-
[Stack]
- Max Depth = 24
- Call Chain = Uds_TesterPresent ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_SetSupFuncEnableFlag
-
- >> Uds_SetNRC
-
- >> Uds_ResponseEnable
-
- >> Uds_ProcessFinished
-
- >> Uds_CheckAdrrType
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_TransSessionType (Thumb, 76 bytes, Stack size 8 bytes, uds.o(i.Uds_TransSessionType))
-
[Stack]
- Max Depth = 8
- Call Chain = Uds_TransSessionType
-
-
[Calls]- >> CanTask_FBLInit
-
- >> Uds_GetCurSessionState
-
- >> Uds_SetStateSessionAccess
-
- >> Uds_SetFlashProtect
-
-
[Called By]
-
-Uds_TransferData (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_TransferData))
-
[Stack]
- Max Depth = 64
- Call Chain = Uds_TransferData ⇒ Diag_TransferData ⇒ Diag_RamWrite ⇒ Diag_MemCpy
-
-
[Calls]
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-Uds_TxConfirmation (Thumb, 24 bytes, Stack size 16 bytes, uds.o(i.Uds_TxConfirmation))
-
[Stack]
- Max Depth = 32
- Call Chain = Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]- >> Uds_NetLayerEndOfTrans
-
-
[Called By]- >> Uds_TxErrorIndication
-
- >> Uds_TransmitResponse
-
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_TxErrorIndication (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_TxErrorIndication))
-
[Stack]
- Max Depth = 40
- Call Chain = Uds_TxErrorIndication ⇒ Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]
-
[Address Reference Count : 1]- iso15765-2_entry.o(.data)
-
-Uds_WriteDataByIdentifier (Thumb, 12 bytes, Stack size 8 bytes, uds.o(i.Uds_WriteDataByIdentifier))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_WriteDataByIdentifier ⇒ Diag_WriteDataByIdentifier ⇒ Diag_MemCopy
-
-
[Calls]- >> Diag_WriteDataByIdentifier
-
-
[Address Reference Count : 1]- canconfig_c301.o(.constdata)
-
-UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler))
-
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
-
-_Bzip2_InitTable (Thumb, 56 bytes, Stack size 0 bytes, uds_sa_c301.o(i._Bzip2_InitTable))
-
[Called By]
-
-__scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
-
-
__scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
-
-
__scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
-
-
bsp_InitI2C (Thumb, 88 bytes, Stack size 8 bytes, bsp_i2c_gpio.o(i.bsp_InitI2C))
-
[Stack]
- Max Depth = 32
- Call Chain = bsp_InitI2C ⇒ GPIO_Init
-
-
[Calls]- >> RCC_APB2PeriphClockCmd
-
- >> GPIO_SetBits
-
- >> GPIO_Init
-
-
[Called By]
-
-ee_Init (Thumb, 8 bytes, Stack size 8 bytes, 24cxx.o(i.ee_Init))
-
[Stack]
- Max Depth = 40
- Call Chain = ee_Init ⇒ bsp_InitI2C ⇒ GPIO_Init
-
-
[Calls]
-
[Called By]
-
-ee_ReadBytes (Thumb, 134 bytes, Stack size 24 bytes, 24cxx.o(i.ee_ReadBytes))
-
[Stack]
- Max Depth = 48
- Call Chain = ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> IIC_Wait_Ack
-
- >> IIC_Stop
-
- >> IIC_Start
-
- >> IIC_Send_Byte
-
- >> IIC_Read_Byte
-
-
[Called By]
-
-flashInit (Thumb, 8 bytes, Stack size 0 bytes, dev_flashapi.o(i.flashInit))
-
[Called By]
- >> Diag_RequestEraseFlash
-
- >> Diag_DataProgram
-
- >> Diag_ClrAPP1UpdateMark
-
-
-flashdnit (Thumb, 16 bytes, Stack size 0 bytes, dev_flashapi.o(i.flashdnit))
-
[Called By]
- >> Diag_RequestEraseFlash
-
- >> Diag_DataProgram
-
- >> Diag_ClrAPP1UpdateMark
-
-
-main (Thumb, 194 bytes, Stack size 24 bytes, main.o(i.main))
-
[Stack]
- Max Depth = 352
- Call Chain = main ⇒ Uds_SysTick_Process_10ms ⇒ Can_Task ⇒ CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> RCC_GetClocksFreq
-
- >> GPIO_ResetBits
-
- >> SystemInit
-
- >> TimeTaskDispatch_Flag
-
- >> SysTick_Init
-
- >> NVIC_Configuration
-
- >> CAN2_Mode_Init
-
- >> ee_Init
-
- >> LED_Init
-
- >> Diag_HndUpdataEV
-
- >> CanTask_InitProcess
-
- >> BSP_BKP_Init
-
- >> uds_SysTick_Process_1ms
-
- >> Uds_SysTick_Process_10ms
-
-
[Address Reference Count : 1]- entry9a.o(.ARM.Collect$$$$0000000B)
-
-
-Local Symbols
-
-CheckITStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CheckITStatus))
-
[Called By]
-
-i2c_Delay (Thumb, 14 bytes, Stack size 0 bytes, bsp_i2c_gpio.o(i.i2c_Delay))
-
[Called By]
- >> IIC_NAck
-
- >> IIC_Ack
-
- >> IIC_Wait_Ack
-
- >> IIC_Stop
-
- >> IIC_Start
-
- >> IIC_Send_Byte
-
- >> IIC_Read_Byte
-
-
-can_bus_open_hook (Thumb, 18 bytes, Stack size 0 bytes, can2.o(i.can_bus_open_hook))
-
[Called By]
-
-can_bus_ready_hook (Thumb, 34 bytes, Stack size 0 bytes, can2.o(i.can_bus_ready_hook))
-
[Called By]
-
-can_bus_send_ready (Thumb, 32 bytes, Stack size 0 bytes, can2.o(i.can_bus_send_ready))
-
[Called By]
-
-SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
-
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
-
-
[Calls]
-
[Called By]
-
-SetSysClockTo72 (Thumb, 266 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
-
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
-
-
[Called By]
-
-Uds_ContextTask (Thumb, 226 bytes, Stack size 16 bytes, uds.o(i.Uds_ContextTask))
-
[Stack]
- Max Depth = 96
- Call Chain = Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> Diag_MemCopy
-
- >> Uds_TransmitResponse
-
- >> Uds_SetState
-
- >> Uds_Scheduler
-
-
[Called By]
-
-Uds_CopyToCanMemCpy (Thumb, 16 bytes, Stack size 0 bytes, uds.o(i.Uds_CopyToCanMemCpy))
-
[Called By]
-
-Uds_NetLayerEndOfRec (Thumb, 44 bytes, Stack size 0 bytes, uds.o(i.Uds_NetLayerEndOfRec))
-
[Called By]
- >> Uds_PhysRxErrorIndication
-
- >> Uds_PhysReqInd
-
-
-Uds_NetLayerEndOfTrans (Thumb, 44 bytes, Stack size 16 bytes, uds.o(i.Uds_NetLayerEndOfTrans))
-
[Stack]
- Max Depth = 16
- Call Chain = Uds_NetLayerEndOfTrans
-
-
[Calls]
-
[Called By]
-
-Uds_NetLayerStartRec (Thumb, 24 bytes, Stack size 0 bytes, uds.o(i.Uds_NetLayerStartRec))
-
[Called By]
- >> Uds_PhysFuncGetBuffer
-
-
-Uds_PostProcessing (Thumb, 24 bytes, Stack size 0 bytes, uds.o(i.Uds_PostProcessing))
-
[Called By]
- >> Uds_NetLayerEndOfTrans
-
-
-Uds_Scheduler (Thumb, 1436 bytes, Stack size 40 bytes, uds.o(i.Uds_Scheduler))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_Scheduler ⇒ Uds_ProcessFinished
-
-
[Calls]- >> Uds_ProcessFinished
-
- >> Uds_GetCurSessionState
-
-
[Called By]
-
-Uds_SetFlashProtect (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetFlashProtect))
-
[Called By]
- >> Uds_TransSessionType
-
-
-Uds_SetState (Thumb, 78 bytes, Stack size 16 bytes, uds.o(i.Uds_SetState))
-
[Stack]
- Max Depth = 80
- Call Chain = Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> Diag_CheckValidApp1
-
- >> CanTask_SetStayInBootFlagValue
-
- >> CanTask_IsAppBeenErased
-
- >> Uds_TransSessionType
-
- >> Uds_GetCurSessionState
-
-
[Called By]- >> Uds_DiagControlSession
-
- >> Uds_TimerTask
-
- >> Uds_ContextTask
-
-
-Uds_SetStateSessionAccess (Thumb, 6 bytes, Stack size 0 bytes, uds.o(i.Uds_SetStateSessionAccess))
-
[Called By]
- >> Uds_TransSessionType
-
-
-Uds_TimerTask (Thumb, 406 bytes, Stack size 8 bytes, uds.o(i.Uds_TimerTask))
-
[Stack]
- Max Depth = 88
- Call Chain = Uds_TimerTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> BSP_vSystemReset
-
- >> Uds_TransmitResPending
-
- >> Uds_SetState
-
-
[Called By]
-
-Uds_TransmitResPending (Thumb, 28 bytes, Stack size 8 bytes, uds.o(i.Uds_TransmitResPending))
-
[Stack]
- Max Depth = 56
- Call Chain = Uds_TransmitResPending ⇒ Uds_TransmitResponse ⇒ Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]- >> Uds_TransmitResponse
-
-
[Called By]
-
-Uds_TransmitResponse (Thumb, 40 bytes, Stack size 16 bytes, uds.o(i.Uds_TransmitResponse))
-
[Stack]
- Max Depth = 48
- Call Chain = Uds_TransmitResponse ⇒ Uds_TxConfirmation ⇒ Uds_NetLayerEndOfTrans
-
-
[Calls]- >> ISO15765_Transmit
-
- >> Uds_TxConfirmation
-
- >> Uds_ResponseEnable
-
-
[Called By]- >> Uds_TransmitResPending
-
- >> Uds_ContextTask
-
-
-ISO15765_Init (Thumb, 12 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_Init))
-
[Stack]
- Max Depth = 16
- Call Chain = ISO15765_Init ⇒ ISO15765_TxInit
-
-
[Calls]- >> ISO15765_TxInit
-
- >> ISO15765_RxInit
-
-
[Called By]- >> ISO15765_InitPowerOn
-
-
-ISO15765_PreCanTransmit (Thumb, 486 bytes, Stack size 24 bytes, iso15765-2.o(i.ISO15765_PreCanTransmit))
-
[Stack]
- Max Depth = 24
- Call Chain = ISO15765_PreCanTransmit
-
-
[Calls]- >> ISO15765_SetOptimalDlc
-
-
[Called By]- >> ISO15765_TxStateTask
-
-
-ISO15765_PreTransmitClearCanDataPtr (Thumb, 22 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_PreTransmitClearCanDataPtr))
-
[Called By]
- >> ISO15765_TxStateTask
-
-
-ISO15765_RxFinishProcess (Thumb, 54 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_RxFinishProcess))
-
[Called By]
- >> ISO15765_DrvConfirmation
-
-
-ISO15765_RxInit (Thumb, 98 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_RxInit))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_RxInit
-
-
[Calls]- >> IF_CAN_CancelTransmitMsg
-
-
[Called By]- >> ISO15765_Precopy
-
- >> ISO15765_RxTask
-
- >> ISO15765_Init
-
- >> ISO15765_RxResetBus
-
-
-ISO15765_RxStateTask (Thumb, 226 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_RxStateTask))
-
[Stack]
- Max Depth = 288
- Call Chain = ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_CanTransmitMsg
-
-
[Called By]- >> ISO15765_Precopy
-
- >> ISO15765_RxTask
-
-
-ISO15765_RxTask (Thumb, 122 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_RxTask))
-
[Stack]
- Max Depth = 296
- Call Chain = ISO15765_RxTask ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_RxStateTask
-
- >> ISO15765_RxInit
-
-
[Called By]
-
-ISO15765_SetOptimalDlc (Thumb, 50 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_SetOptimalDlc))
-
[Called By]
- >> ISO15765_PreCanTransmit
-
-
-ISO15765_TransmitOfCF (Thumb, 72 bytes, Stack size 0 bytes, iso15765-2.o(i.ISO15765_TransmitOfCF))
-
[Called By]
-
-ISO15765_TxFinishProcess (Thumb, 126 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_TxFinishProcess))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_TxFinishProcess
-
-
[Called By]- >> ISO15765_DrvConfirmation
-
-
-ISO15765_TxInit (Thumb, 114 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_TxInit))
-
[Stack]
- Max Depth = 8
- Call Chain = ISO15765_TxInit
-
-
[Calls]- >> IF_CAN_CancelTransmitMsg
-
-
[Called By]- >> ISO15765_Precopy
-
- >> ISO15765_TxTask
-
- >> ISO15765_Init
-
-
-ISO15765_TxStateTask (Thumb, 232 bytes, Stack size 16 bytes, iso15765-2.o(i.ISO15765_TxStateTask))
-
[Stack]
- Max Depth = 288
- Call Chain = ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_CanTransmitMsg
-
- >> ISO15765_PreTransmitClearCanDataPtr
-
- >> ISO15765_PreCanTransmit
-
-
[Called By]
-
-ISO15765_TxTask (Thumb, 90 bytes, Stack size 8 bytes, iso15765-2.o(i.ISO15765_TxTask))
-
[Stack]
- Max Depth = 296
- Call Chain = ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_TxStateTask
-
- >> ISO15765_TxInit
-
- >> ISO15765_TransmitOfCF
-
-
[Called By]
-
-CanTrans_Delay (Thumb, 16 bytes, Stack size 0 bytes, can_transceiver.o(i.CanTrans_Delay))
-
[Called By]
-
-Diag_CommDisable (Thumb, 12 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CommDisable))
-
[Called By]
- >> Diag_CommunicationControl
-
-
-Diag_CommEnable (Thumb, 12 bytes, Stack size 0 bytes, diag_appl_c301.o(i.Diag_CommEnable))
-
[Called By]
- >> Diag_CommunicationControl
-
-
-JumpToExecute (Thumb, 30 bytes, Stack size 8 bytes, main.o(i.JumpToExecute))
-
[Stack]
- Max Depth = 8
- Call Chain = JumpToExecute
-
-
[Calls]
-
[Called By]
-
-Sys_GotoApp (Thumb, 8 bytes, Stack size 8 bytes, main.o(i.Sys_GotoApp))
-
[Stack]
- Max Depth = 16
- Call Chain = Sys_GotoApp ⇒ JumpToExecute
-
-
[Calls]
-
[Called By]
-
-Task_RunToApp (Thumb, 44 bytes, Stack size 8 bytes, main.o(i.Task_RunToApp))
-
[Stack]
- Max Depth = 24
- Call Chain = Task_RunToApp ⇒ Sys_GotoApp ⇒ JumpToExecute
-
-
[Calls]
-
[Called By]- >> Uds_SysTick_Process_10ms
-
-
-Uds_SysTick_Process_10ms (Thumb, 12 bytes, Stack size 8 bytes, main.o(i.Uds_SysTick_Process_10ms))
-
[Stack]
- Max Depth = 328
- Call Chain = Uds_SysTick_Process_10ms ⇒ Can_Task ⇒ CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> Can_Task
-
- >> Task_RunToApp
-
-
[Called By]
-
-uds_SysTick_Process_1ms (Thumb, 8 bytes, Stack size 8 bytes, main.o(i.uds_SysTick_Process_1ms))
-
[Stack]
- Max Depth = 120
- Call Chain = uds_SysTick_Process_1ms ⇒ CanTask_UdsStateProcess ⇒ Uds_StateTask ⇒ Uds_ContextTask ⇒ Uds_SetState ⇒ Diag_CheckValidApp1 ⇒ ee_ReadBytes ⇒ IIC_Read_Byte ⇒ IIC_NAck
-
-
[Calls]- >> CanTask_UdsStateProcess
-
-
[Called By]
-
-APP_CAN_MessageTypeHandle (Thumb, 92 bytes, Stack size 16 bytes, app_can.o(i.APP_CAN_MessageTypeHandle))
-
[Stack]
- Max Depth = 320
- Call Chain = APP_CAN_MessageTypeHandle ⇒ ISO15765_Precopy ⇒ ISO15765_RxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]
-
[Called By]- >> APP_CAN_FifoMessageReceive
-
-
-CanTask_ReprogrammingCheck (Thumb, 26 bytes, Stack size 8 bytes, app_can.o(i.CanTask_ReprogrammingCheck))
-
[Stack]
- Max Depth = 8
- Call Chain = CanTask_ReprogrammingCheck
-
-
[Calls]- >> Uds_GetCurSessionAccessStatus
-
-
[Called By]- >> CanTask_TimerProcess
-
-
-CanTask_SaRandomCounter (Thumb, 12 bytes, Stack size 0 bytes, app_can.o(i.CanTask_SaRandomCounter))
-
[Called By]
- >> CanTask_TimerProcess
-
-
-CanTask_TimerProcess (Thumb, 24 bytes, Stack size 8 bytes, app_can.o(i.CanTask_TimerProcess))
-
[Stack]
- Max Depth = 312
- Call Chain = CanTask_TimerProcess ⇒ ISO15765_Task ⇒ ISO15765_TxTask ⇒ ISO15765_TxStateTask ⇒ ISO15765_CanTransmitMsg ⇒ IF_CAN_TransmitMsg ⇒ IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> ISO15765_Task
-
- >> Uds_Task
-
- >> CanTask_BusErrorDetection
-
- >> CanTask_SaRandomCounter
-
- >> CanTask_ReprogrammingCheck
-
-
[Called By]
-
-IF_CAN_CopyDataAndStartTx (Thumb, 140 bytes, Stack size 120 bytes, app_can.o(i.IF_CAN_CopyDataAndStartTx))
-
[Stack]
- Max Depth = 240
- Call Chain = IF_CAN_CopyDataAndStartTx ⇒ IF_CAN_SendCanData ⇒ Can2_Send_Message ⇒ CAN_TransmitStatus
-
-
[Calls]- >> __aeabi_memclr4
-
- >> IF_CAN_SendCanData
-
-
[Called By]
-
-
-Undefined Global Symbols
-
diff --git a/boot_project/Objects/hongri_boot.lnp b/boot_project/Objects/hongri_boot.lnp
deleted file mode 100644
index 0a0fb6c..0000000
--- a/boot_project/Objects/hongri_boot.lnp
+++ /dev/null
@@ -1,36 +0,0 @@
---cpu Cortex-M3
-".\objects\startup_stm32f10x_cl.o"
-".\objects\core_cm3.o"
-".\objects\misc.o"
-".\objects\stm32f10x_gpio.o"
-".\objects\stm32f10x_rcc.o"
-".\objects\stm32f10x_can.o"
-".\objects\stm32f10x_dma.o"
-".\objects\stm32f10x_flash.o"
-".\objects\stm32f10x_iwdg.o"
-".\objects\stm32f10x_pwr.o"
-".\objects\led.o"
-".\objects\24cxx.o"
-".\objects\bsp_i2c_gpio.o"
-".\objects\can2.o"
-".\objects\stm32f10x_it.o"
-".\objects\system_stm32f10x.o"
-".\objects\dev_flashapi.o"
-".\objects\dev_crc32.o"
-".\objects\dev_sys.o"
-".\objects\dev_eerom.o"
-".\objects\uds.o"
-".\objects\iso15765-2.o"
-".\objects\iso15765-2_entry.o"
-".\objects\can_transceiver.o"
-".\objects\diag_eeprom_c301.o"
-".\objects\canconfig_c301.o"
-".\objects\canctrl_c301.o"
-".\objects\diag_appl_c301.o"
-".\objects\uds_sa_c301.o"
-".\objects\main.o"
-".\objects\app_can.o"
---library_type=microlib --strict --scatter ".\link_sct\STM32F105Boot.sct"
---summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
---info sizes --info totals --info unused --info veneers
---list ".\Listings\hongri_boot.map" -o .\Objects\hongri_boot.axf
\ No newline at end of file
diff --git a/boot_project/Objects/hongri_boot.sct b/boot_project/Objects/hongri_boot.sct
deleted file mode 100644
index 2cc9188..0000000
Binary files a/boot_project/Objects/hongri_boot.sct and /dev/null differ
diff --git a/boot_project/Objects/hongri_boot_hongri_boot.dep b/boot_project/Objects/hongri_boot_hongri_boot.dep
deleted file mode 100644
index e7c5c03..0000000
--- a/boot_project/Objects/hongri_boot_hongri_boot.dep
+++ /dev/null
@@ -1,482 +0,0 @@
-Dependencies for Project 'hongri_boot', Target 'hongri_boot': (DO NOT MODIFY !)
-F (..\boot_source\platform\CMSIS\ST\STM32F10x\Source\arm\startup_stm32f10x_cl.s)(0x67188B3E)(--cpu Cortex-M3 -g --apcs=interwork --pd "__MICROLIB SETA 1"
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
--pd "__UVISION_VERSION SETA 525" --pd "STM32F10X_CL SETA 1"
--list .\listings\startup_stm32f10x_cl.lst --xref -o .\objects\startup_stm32f10x_cl.o --depend .\objects\startup_stm32f10x_cl.d)
-F (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.c)(0x61605444)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\core_cm3.o --omf_browse .\objects\core_cm3.crf --depend .\objects\core_cm3.d)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\misc.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\misc.o --omf_browse .\objects\misc.crf --depend .\objects\misc.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_gpio.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_gpio.o --omf_browse .\objects\stm32f10x_gpio.crf --depend .\objects\stm32f10x_gpio.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_rcc.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_rcc.o --omf_browse .\objects\stm32f10x_rcc.crf --depend .\objects\stm32f10x_rcc.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_can.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_can.o --omf_browse .\objects\stm32f10x_can.crf --depend .\objects\stm32f10x_can.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_dma.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_dma.o --omf_browse .\objects\stm32f10x_dma.crf --depend .\objects\stm32f10x_dma.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_dma.h)(0x521ED710)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_flash.c)(0x6118F57E)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_flash.o --omf_browse .\objects\stm32f10x_flash.crf --depend .\objects\stm32f10x_flash.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_flash.h)(0x521ED710)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_iwdg.c)(0x521ED710)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_iwdg.o --omf_browse .\objects\stm32f10x_iwdg.crf --depend .\objects\stm32f10x_iwdg.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\src\stm32f10x_pwr.c)(0x65F32F30)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_pwr.o --omf_browse .\objects\stm32f10x_pwr.crf --depend .\objects\stm32f10x_pwr.d)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\drivers\src\LED\led.c)(0x671A1AEB)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\led.o --omf_browse .\objects\led.crf --depend .\objects\led.d)
-I (..\boot_source\platform\drivers\inc\led.h)(0x67175BF6)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\platform\drivers\src\EEROM\24cxx.c)(0x67284208)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\24cxx.o --omf_browse .\objects\24cxx.crf --depend .\objects\24cxx.d)
-I (..\boot_source\platform\drivers\inc\24cxx.h)(0x67285B2C)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\platform\drivers\inc\bsp_i2c_gpio.h)(0x5EDA6162)
-I (..\boot_source\code_app\driver\inc\dev_config_all.h)(0x671755F9)
-I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
-F (..\boot_source\platform\drivers\src\EEROM\bsp_i2c_gpio.c)(0x67283D3C)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\bsp_i2c_gpio.o --omf_browse .\objects\bsp_i2c_gpio.crf --depend .\objects\bsp_i2c_gpio.d)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\platform\drivers\inc\bsp_i2c_gpio.h)(0x5EDA6162)
-F (..\boot_source\platform\drivers\src\CAN2\can2.c)(0x67231E54)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\can2.o --omf_browse .\objects\can2.crf --depend .\objects\can2.d)
-I (..\boot_source\platform\drivers\inc\can2.h)(0x67205017)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-F (..\boot_source\platform\drivers\src\flash\ecual_flash.c)(0x67232464)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\ecual_flash.o --omf_browse .\objects\ecual_flash.crf --depend .\objects\ecual_flash.d)
-I (..\boot_source\code_app\main\inc\config.h)(0x671A0813)
-I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x6720A9AA)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-F (..\boot_source\code_app\startup\src\stm32f10x_it.c)(0x6718B1A0)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\stm32f10x_it.o --omf_browse .\objects\stm32f10x_it.crf --depend .\objects\stm32f10x_it.d)
-I (..\boot_source\code_app\startup\inc\stm32f10x_it.h)(0x61605442)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\code_app\startup\src\system_stm32f10x.c)(0x6718B1B1)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\code_app\driver\src\dev_flashApi.c)(0x67171677)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_flashapi.o --omf_browse .\objects\dev_flashapi.crf --depend .\objects\dev_flashapi.d)
-I (..\boot_source\code_app\driver\inc\dev_flashApi.h)(0x67282DED)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-F (..\boot_source\code_app\driver\src\dev_crc32.c)(0x67173C51)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_crc32.o --omf_browse .\objects\dev_crc32.crf --depend .\objects\dev_crc32.d)
-I (..\boot_source\code_app\driver\inc\dev_crc32.h)(0x67184946)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-F (..\boot_source\code_app\driver\src\dev_sys.c)(0x67208F33)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_sys.o --omf_browse .\objects\dev_sys.crf --depend .\objects\dev_sys.d)
-I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-F (..\boot_source\code_app\driver\src\dev_eerom.c)(0x67286104)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\dev_eerom.o --omf_browse .\objects\dev_eerom.crf --depend .\objects\dev_eerom.d)
-F (..\boot_source\code_app\service\CanStack\canBus_Com\UDS.c)(0x6729762E)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\uds.o --omf_browse .\objects\uds.crf --depend .\objects\uds.d)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
-I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.h)(0x672977E5)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
-F (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2.c)(0x67242B88)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\iso15765-2.o --omf_browse .\objects\iso15765-2.crf --depend .\objects\iso15765-2.d)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
-F (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_entry.c)(0x6721ABCB)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\iso15765-2_entry.o --omf_browse .\objects\iso15765-2_entry.crf --depend .\objects\iso15765-2_entry.d)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\code_app\service\CanStack\canBus_Com\Can_Transceiver.c)(0x67297613)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\can_transceiver.o --omf_browse .\objects\can_transceiver.crf --depend .\objects\can_transceiver.d)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\Can_Transceiver.h)(0x67297611)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-F (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.c)(0x672974A7)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\diag_eeprom_c301.o --omf_browse .\objects\diag_eeprom_c301.crf --depend .\objects\diag_eeprom_c301.d)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\driver\inc\dev_flashApi.h)(0x67282DED)
-I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x67288F56)
-I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
-F (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.c)(0x6724308B)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\canconfig_c301.o --omf_browse .\objects\canconfig_c301.crf --depend .\objects\canconfig_c301.d)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
-F (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.c)(0x672974D8)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\canctrl_c301.o --omf_browse .\objects\canctrl_c301.crf --depend .\objects\canctrl_c301.d)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-F (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.c)(0x672975E0)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\diag_appl_c301.o --omf_browse .\objects\diag_appl_c301.crf --depend .\objects\diag_appl_c301.d)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Appl_C301.h)(0x672977E5)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
-I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
-I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x67288F56)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.h)(0x672444AF)
-I (..\boot_source\code_app\driver\inc\dev_flashApi.h)(0x67282DED)
-I (..\boot_source\code_app\driver\inc\dev_eerom.h)(0x672860FC)
-I (..\boot_source\platform\drivers\inc\24cxx.h)(0x67285B2C)
-F (..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.c)(0x6725BFB7)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\uds_sa_c301.o --omf_browse .\objects\uds_sa_c301.crf --depend .\objects\uds_sa_c301.d)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\UDS_SA_C301.h)(0x672444AF)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-F (..\boot_source\code_app\main\src\main.c)(0x6728AF31)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d)
-I (..\boot_source\code_app\main\inc\main.h)(0x6718CD0E)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\driver\inc\dev_config_all.h)(0x671755F9)
-I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
-I (..\boot_source\platform\drivers\inc\platform_driver_inc_all.h)(0x67177546)
-I (..\boot_source\platform\drivers\inc\led.h)(0x67175BF6)
-I (..\boot_source\platform\drivers\inc\24cxx.h)(0x67285B2C)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\platform\drivers\inc\can2.h)(0x67205017)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Service_Canstack_CanBus_hongri_All.h)(0x671F598C)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
-I (..\boot_source\code_app\main\inc\config.h)(0x6721CC37)
-I (..\boot_source\platform\drivers\inc\ecual_flash.h)(0x67288F56)
-F (..\boot_source\code_app\app_boot\src\app_can.c)(0x672975E0)(--c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O0 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
-I.\RTE\_hongri_boot
-IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
-IC:\Keil_v5\ARM\CMSIS\Include
-D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\objects\app_can.o --omf_browse .\objects\app_can.crf --depend .\objects\app_can.d)
-I (..\boot_source\code_app\app_boot\inc\app_can.h)(0x67285BFE)
-I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x67208686)
-I (..\boot_source\code_app\startup\inc\stm32f10x.h)(0x671A25F3)
-I (..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport\core_cm3.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\system_stm32f10x.h)(0x61605444)
-I (..\boot_source\code_app\startup\inc\stm32f10x_libopt.h)(0x67177362)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x62D28C12)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x65F3EF70)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x521ED710)
-I (..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc\misc.h)(0x521ED710)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanConfig_C301.h)(0x67243FD1)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\can_def.h)(0x67219607)
-I (..\boot_source\platform\drivers\inc\platform_type_def.h)(0x672193E6)
-I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x599ECD2E)
-I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
-I (..\boot_source\code_app\app_boot\inc\app_cfg.h)(0x6720B2FA)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\iso15765-2_def.h)(0x67235D8A)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\CanCtrl_C301.h)(0x67219591)
-I (..\boot_source\code_app\service\CanStack\canBus_hongri\Diag_Eeprom_C301.h)(0x6728607A)
-I (..\boot_source\code_app\driver\inc\dev_sys.h)(0x6721C8E4)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\uds.h)(0x67218E85)
-I (..\boot_source\code_app\service\CanStack\canBus_Com\Can_Transceiver.h)(0x67297611)
-I (..\boot_source\platform\drivers\inc\can2.h)(0x67205017)
diff --git a/boot_project/Objects/if_can.__i b/boot_project/Objects/if_can.__i
deleted file mode 100644
index 6f859f6..0000000
--- a/boot_project/Objects/if_can.__i
+++ /dev/null
@@ -1,6 +0,0 @@
---c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
--I.\RTE\_hongri_boot
--IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
--IC:\Keil_v5\ARM\CMSIS\Include
--D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
--o .\objects\if_can.o --omf_browse .\objects\if_can.crf --depend .\objects\if_can.d "..\boot_source\code_app\interface\src\if_can.c"
\ No newline at end of file
diff --git a/boot_project/Objects/if_gpio.__i b/boot_project/Objects/if_gpio.__i
deleted file mode 100644
index a0829ca..0000000
--- a/boot_project/Objects/if_gpio.__i
+++ /dev/null
@@ -1,6 +0,0 @@
---c99 -c --cpu Cortex-M3 -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\boot_source\platform\CMSIS\ST\STM32F10x\CoreSupport -I ..\boot_source\platform\Chip_peripheral_dev\STM32F10x_FWLib\inc -I ..\boot_source\platform\drivers\inc -I ..\boot_source\code_app\startup\inc -I ..\boot_source\code_app\driver\inc -I ..\boot_source\code_app\interface\inc -I ..\boot_source\code_app\service\CanStack\canBus_Com -I ..\boot_source\code_app\service\CanStack\canBus_hongri -I ..\boot_source\code_app\service\Eeprom\inc -I ..\boot_source\code_app\main\inc -I ..\boot_source\code_app\app_boot\inc --diag_suppress 236
--I.\RTE\_hongri_boot
--IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.1.0\Device\Include
--IC:\Keil_v5\ARM\CMSIS\Include
--D__UVISION_VERSION="525" -DSTM32F10X_CL -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
--o .\objects\if_gpio.o --omf_browse .\objects\if_gpio.crf --depend .\objects\if_gpio.d "..\boot_source\code_app\interface\src\if_gpio.c"
\ No newline at end of file
diff --git a/boot_project/hongri_boot-GD32F105.uvguix.Administrator b/boot_project/hongri_boot-GD32F105.uvguix.Administrator
new file mode 100644
index 0000000..c6b193d
Binary files /dev/null and b/boot_project/hongri_boot-GD32F105.uvguix.Administrator differ
diff --git a/boot_project/hongri_boot-GD32F105.uvprojx b/boot_project/hongri_boot-GD32F105.uvprojx
new file mode 100644
index 0000000..dc15e81
Binary files /dev/null and b/boot_project/hongri_boot-GD32F105.uvprojx differ
diff --git a/boot_project/hongri_boot-STM32F105.uvguix.Administrator b/boot_project/hongri_boot-STM32F105.uvguix.Administrator
new file mode 100644
index 0000000..716fe9c
Binary files /dev/null and b/boot_project/hongri_boot-STM32F105.uvguix.Administrator differ
diff --git a/boot_project/hongri_boot-STM32F105.uvprojx b/boot_project/hongri_boot-STM32F105.uvprojx
new file mode 100644
index 0000000..7902873
Binary files /dev/null and b/boot_project/hongri_boot-STM32F105.uvprojx differ
diff --git a/boot_project/hongri_boot.uvguix.Administrator b/boot_project/hongri_boot.uvguix.Administrator
deleted file mode 100644
index f6b794f..0000000
Binary files a/boot_project/hongri_boot.uvguix.Administrator and /dev/null differ
diff --git a/boot_project/hongri_boot.uvmpw b/boot_project/hongri_boot.uvmpw
new file mode 100644
index 0000000..2202f9c
Binary files /dev/null and b/boot_project/hongri_boot.uvmpw differ
diff --git a/boot_project/hongri_boot.uvmpw.uvgui.Administrator b/boot_project/hongri_boot.uvmpw.uvgui.Administrator
new file mode 100644
index 0000000..2b13efe
Binary files /dev/null and b/boot_project/hongri_boot.uvmpw.uvgui.Administrator differ
diff --git a/boot_project/hongri_boot.uvprojx b/boot_project/hongri_boot.uvprojx
deleted file mode 100644
index dc67a95..0000000
Binary files a/boot_project/hongri_boot.uvprojx and /dev/null differ
diff --git a/boot_project/link_sct/GD32F105Flashdriver.sct b/boot_project/link_sct/GD32F105Flashdriver.sct
new file mode 100644
index 0000000..8f74173
Binary files /dev/null and b/boot_project/link_sct/GD32F105Flashdriver.sct differ
diff --git a/boot_source/code_app/app_boot/inc/app_can.h b/boot_source/code_app/app_boot/inc/app_can.h
index 9f06257..aee69a1 100644
Binary files a/boot_source/code_app/app_boot/inc/app_can.h and b/boot_source/code_app/app_boot/inc/app_can.h differ
diff --git a/boot_source/code_app/app_boot/src/app_can.c b/boot_source/code_app/app_boot/src/app_can.c
index 14c1337..2cce597 100644
Binary files a/boot_source/code_app/app_boot/src/app_can.c and b/boot_source/code_app/app_boot/src/app_can.c differ
diff --git a/boot_source/code_app/driver/inc/dev_log_usart.h b/boot_source/code_app/driver/inc/dev_log_usart.h
index 0f2bf7d..84dfe4a 100644
Binary files a/boot_source/code_app/driver/inc/dev_log_usart.h and b/boot_source/code_app/driver/inc/dev_log_usart.h differ
diff --git a/boot_source/code_app/driver/inc/dev_sys.h b/boot_source/code_app/driver/inc/dev_sys.h
index 8cd3c75..229fe06 100644
Binary files a/boot_source/code_app/driver/inc/dev_sys.h and b/boot_source/code_app/driver/inc/dev_sys.h differ
diff --git a/boot_source/code_app/driver/src/dev_sys.c b/boot_source/code_app/driver/src/dev_sys.c
index 7705d6f..7b45014 100644
Binary files a/boot_source/code_app/driver/src/dev_sys.c and b/boot_source/code_app/driver/src/dev_sys.c differ
diff --git a/boot_source/code_app/main/inc/main.h b/boot_source/code_app/main/inc/main.h
index 25fe7f3..15475e0 100644
Binary files a/boot_source/code_app/main/inc/main.h and b/boot_source/code_app/main/inc/main.h differ
diff --git a/boot_source/code_app/main/src/main.c b/boot_source/code_app/main/src/main.c
index ae22750..1ec54ee 100644
Binary files a/boot_source/code_app/main/src/main.c and b/boot_source/code_app/main/src/main.c differ
diff --git a/boot_source/code_app/service/CanStack/canBus_Com/Can_Transceiver.c b/boot_source/code_app/service/CanStack/canBus_Com/Can_Transceiver.c
index 4fd10a0..d550506 100644
Binary files a/boot_source/code_app/service/CanStack/canBus_Com/Can_Transceiver.c and b/boot_source/code_app/service/CanStack/canBus_Com/Can_Transceiver.c differ
diff --git a/boot_source/code_app/service/CanStack/canBus_Com/iso15765-2.c b/boot_source/code_app/service/CanStack/canBus_Com/iso15765-2.c
index 0832986..e815982 100644
Binary files a/boot_source/code_app/service/CanStack/canBus_Com/iso15765-2.c and b/boot_source/code_app/service/CanStack/canBus_Com/iso15765-2.c differ
diff --git a/boot_source/code_app/service/CanStack/canBus_hongri/Diag_Eeprom_C301.c b/boot_source/code_app/service/CanStack/canBus_hongri/Diag_Eeprom_C301.c
index 1f42c1e..c8769af 100644
Binary files a/boot_source/code_app/service/CanStack/canBus_hongri/Diag_Eeprom_C301.c and b/boot_source/code_app/service/CanStack/canBus_hongri/Diag_Eeprom_C301.c differ
diff --git a/boot_source/code_app/startup/GD32F105/inc/gd32f10x.h b/boot_source/code_app/startup/GD32F105/inc/gd32f10x.h
new file mode 100644
index 0000000..30df3a5
Binary files /dev/null and b/boot_source/code_app/startup/GD32F105/inc/gd32f10x.h differ
diff --git a/boot_source/code_app/startup/GD32F105/inc/gd32f10x_it.h b/boot_source/code_app/startup/GD32F105/inc/gd32f10x_it.h
new file mode 100644
index 0000000..6eaa66a
--- /dev/null
+++ b/boot_source/code_app/startup/GD32F105/inc/gd32f10x_it.h
@@ -0,0 +1,60 @@
+/*!
+ \file gd32f10x_it.h
+ \brief the header file of the ISR
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_IT_H
+#define GD32F10X_IT_H
+
+#include "gd32f10x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32F10X_IT_H */
diff --git a/boot_source/code_app/startup/GD32F105/inc/gd32f10x_libopt.h b/boot_source/code_app/startup/GD32F105/inc/gd32f10x_libopt.h
new file mode 100644
index 0000000..a90b814
Binary files /dev/null and b/boot_source/code_app/startup/GD32F105/inc/gd32f10x_libopt.h differ
diff --git a/boot_source/code_app/startup/GD32F105/inc/system_gd32f10x.h b/boot_source/code_app/startup/GD32F105/inc/system_gd32f10x.h
new file mode 100644
index 0000000..71fc2af
Binary files /dev/null and b/boot_source/code_app/startup/GD32F105/inc/system_gd32f10x.h differ
diff --git a/boot_source/code_app/startup/GD32F105/src/gd32f10x_it.c b/boot_source/code_app/startup/GD32F105/src/gd32f10x_it.c
new file mode 100644
index 0000000..24da9d2
Binary files /dev/null and b/boot_source/code_app/startup/GD32F105/src/gd32f10x_it.c differ
diff --git a/boot_source/code_app/startup/GD32F105/src/system_gd32f10x.c b/boot_source/code_app/startup/GD32F105/src/system_gd32f10x.c
new file mode 100644
index 0000000..a1c63b1
Binary files /dev/null and b/boot_source/code_app/startup/GD32F105/src/system_gd32f10x.c differ
diff --git a/boot_source/code_app/startup/inc/stm32f10x.h b/boot_source/code_app/startup/STM32F105/inc/stm32f10x.h
similarity index 100%
rename from boot_source/code_app/startup/inc/stm32f10x.h
rename to boot_source/code_app/startup/STM32F105/inc/stm32f10x.h
diff --git a/boot_source/code_app/startup/inc/stm32f10x_it.h b/boot_source/code_app/startup/STM32F105/inc/stm32f10x_it.h
similarity index 100%
rename from boot_source/code_app/startup/inc/stm32f10x_it.h
rename to boot_source/code_app/startup/STM32F105/inc/stm32f10x_it.h
diff --git a/boot_source/code_app/startup/inc/stm32f10x_libopt.h b/boot_source/code_app/startup/STM32F105/inc/stm32f10x_libopt.h
similarity index 100%
rename from boot_source/code_app/startup/inc/stm32f10x_libopt.h
rename to boot_source/code_app/startup/STM32F105/inc/stm32f10x_libopt.h
diff --git a/boot_source/code_app/startup/inc/system_stm32f10x.h b/boot_source/code_app/startup/STM32F105/inc/system_stm32f10x.h
similarity index 100%
rename from boot_source/code_app/startup/inc/system_stm32f10x.h
rename to boot_source/code_app/startup/STM32F105/inc/system_stm32f10x.h
diff --git a/boot_source/code_app/startup/src/stm32f10x_it.c b/boot_source/code_app/startup/STM32F105/src/stm32f10x_it.c
similarity index 100%
rename from boot_source/code_app/startup/src/stm32f10x_it.c
rename to boot_source/code_app/startup/STM32F105/src/stm32f10x_it.c
diff --git a/boot_source/code_app/startup/src/system_stm32f10x.c b/boot_source/code_app/startup/STM32F105/src/system_stm32f10x.c
similarity index 100%
rename from boot_source/code_app/startup/src/system_stm32f10x.c
rename to boot_source/code_app/startup/STM32F105/src/system_stm32f10x.c
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cm3.h b/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cm3.h
new file mode 100644
index 0000000..1b661b4
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cm3.h
@@ -0,0 +1,1638 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.30
+ * @date 17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmFunc.h b/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmFunc.h
new file mode 100644
index 0000000..2c2af69
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmFunc.h
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.30
+ * @date 17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmInstr.h b/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmInstr.h
new file mode 100644
index 0000000..d2ec262
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/CoreSupport/core_cmInstr.h
@@ -0,0 +1,687 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.30
+ * @date 17. February 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x.h b/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x.h
new file mode 100644
index 0000000..30df3a5
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x.h differ
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_it.h b/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_it.h
new file mode 100644
index 0000000..6eaa66a
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_it.h
@@ -0,0 +1,60 @@
+/*!
+ \file gd32f10x_it.h
+ \brief the header file of the ISR
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_IT_H
+#define GD32F10X_IT_H
+
+#include "gd32f10x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32F10X_IT_H */
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_libopt.h b/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_libopt.h
new file mode 100644
index 0000000..0a3bf0b
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Include/gd32f10x_libopt.h differ
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h b/boot_source/platform/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h
new file mode 100644
index 0000000..80cf6c8
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h differ
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s
new file mode 100644
index 0000000..42f1105
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s differ
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s
new file mode 100644
index 0000000..440f308
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s
@@ -0,0 +1,369 @@
+;/*!
+; \file startup_gd32f10x_hd.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+;
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN = 3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN = 3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
+ DCD RTC_IRQHandler ; 19:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_IRQHandler ; 21:RCU
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
+ DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
+ DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
+ DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
+ DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
+ DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
+ DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt
+ DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt
+ DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD ADC2_IRQHandler ; 63:ADC2
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD SDIO_IRQHandler ; 65:SDIO
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_IRQHandler ; 70:TIMER5
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+MemManage_Handler PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+BusFault_Handler PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+
+UsageFault_Handler PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+DebugMon_Handler PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC0_1_IRQHandler [WEAK]
+ EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
+ EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBD_WKUP_IRQHandler [WEAK]
+ EXPORT TIMER7_BRK_IRQHandler [WEAK]
+ EXPORT TIMER7_UP_IRQHandler [WEAK]
+ EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
+ EXPORT TIMER7_Channel_IRQHandler [WEAK]
+ EXPORT ADC2_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT TIMER5_IRQHandler [WEAK]
+ EXPORT TIMER6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel0_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
+
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC0_1_IRQHandler
+USBD_HP_CAN0_TX_IRQHandler
+USBD_LP_CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_IRQHandler
+TIMER0_UP_IRQHandler
+TIMER0_TRG_CMT_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBD_WKUP_IRQHandler
+TIMER7_BRK_IRQHandler
+TIMER7_UP_IRQHandler
+TIMER7_TRG_CMT_IRQHandler
+TIMER7_Channel_IRQHandler
+ADC2_IRQHandler
+EXMC_IRQHandler
+SDIO_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_4_IRQHandler
+
+
+
+ B .
+ ENDP
+
+ ALIGN
+
+; user Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s
new file mode 100644
index 0000000..3c02759
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s
@@ -0,0 +1,326 @@
+;/*!
+; \file startup_gd32f10x_md.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+;
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN = 3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN = 3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
+ DCD RTC_IRQHandler ; 19:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_IRQHandler ; 21:RCU
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
+ DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
+ DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
+ DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
+ DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
+ DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXMC_IRQHandler ; 64:EXMC
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+MemManage_Handler PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+BusFault_Handler PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+
+UsageFault_Handler PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+DebugMon_Handler PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC0_1_IRQHandler [WEAK]
+ EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
+ EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBD_WKUP_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC0_1_IRQHandler
+USBD_HP_CAN0_TX_IRQHandler
+USBD_LP_CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_IRQHandler
+TIMER0_UP_IRQHandler
+TIMER0_TRG_CMT_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBD_WKUP_IRQHandler
+EXMC_IRQHandler
+
+
+
+ B .
+ ENDP
+
+ ALIGN
+
+; user Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s
new file mode 100644
index 0000000..b32be29
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s
@@ -0,0 +1,369 @@
+;/*!
+; \file startup_gd32f10x_xd.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+;
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN = 3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN = 3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
+ DCD RTC_IRQHandler ; 19:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_IRQHandler ; 21:RCU
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
+ DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
+ DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 global
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 global
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
+ DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break Interrupt and TIMER11 global
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update Interrupt and TIMER12 global
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13 global
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD ADC2_IRQHandler ; 63:ADC2
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD SDIO_IRQHandler ; 65:SDIO
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_IRQHandler ; 70:TIMER5
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+MemManage_Handler PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+BusFault_Handler PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+
+UsageFault_Handler PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+DebugMon_Handler PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC0_1_IRQHandler [WEAK]
+ EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
+ EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBD_WKUP_IRQHandler [WEAK]
+ EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
+ EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
+ EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
+ EXPORT TIMER7_Channel_IRQHandler [WEAK]
+ EXPORT ADC2_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT TIMER5_IRQHandler [WEAK]
+ EXPORT TIMER6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel0_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
+
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC0_1_IRQHandler
+USBD_HP_CAN0_TX_IRQHandler
+USBD_LP_CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_TIMER8_IRQHandler
+TIMER0_UP_TIMER9_IRQHandler
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBD_WKUP_IRQHandler
+TIMER7_BRK_TIMER11_IRQHandler
+TIMER7_UP_TIMER12_IRQHandler
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+TIMER7_Channel_IRQHandler
+ADC2_IRQHandler
+EXMC_IRQHandler
+SDIO_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_4_IRQHandler
+
+
+
+ B .
+ ENDP
+
+ ALIGN
+
+; user Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_stm32f10x_cl.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..a9815cc
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Source/ARM/startup_stm32f10x_cl.s differ
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s
new file mode 100644
index 0000000..9a281f5
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s
@@ -0,0 +1,527 @@
+;/*!
+; \file startup_gd32f10x_cl.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; top of stack
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
+ DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
+ DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
+ DCD FMC_IRQHandler ; Vector Number 20,FMC
+ DCD RCU_IRQHandler ; Vector Number 21,RCU
+ DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
+ DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
+ DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
+ DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
+ DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
+ DCD CAN0_TX_IRQHandler ; Vector Number 35,CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; Vector Number 36,CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break
+ DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update
+ DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation
+ DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
+ DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
+ DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
+ DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
+ DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
+ DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
+ DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
+ DCD SPI0_IRQHandler ; Vector Number 51,SPI0
+ DCD SPI1_IRQHandler ; Vector Number 52,SPI1
+ DCD USART0_IRQHandler ; Vector Number 53,USART0
+ DCD USART1_IRQHandler ; Vector Number 54,USART1
+ DCD USART2_IRQHandler ; Vector Number 55,USART2
+ DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
+ DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line
+ DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt
+ DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt
+ DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt
+ DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare
+ DCD 0 ; Reserved
+ DCD EXMC_IRQHandler ; Vector Number 64,EXMC
+ DCD 0 ; Reserved
+ DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4
+ DCD SPI2_IRQHandler ; Vector Number 67,SPI2
+ DCD UART3_IRQHandler ; Vector Number 68,UART3
+ DCD UART4_IRQHandler ; Vector Number 69,UART4
+ DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5
+ DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6
+ DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; Vector Number 75,DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; Vector Number 76,DMA1 Channel4
+ DCD ENET_IRQHandler ; Vector Number 77,Ethernet
+ DCD ENET_WKUP_IRQHandler ; Vector Number 78,Ethernet Wakeup through EXTI line
+ DCD CAN1_TX_IRQHandler ; Vector Number 79,CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; Vector Number 80,CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; Vector Number 81,CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; Vector Number 82,CAN1 EWMC
+ DCD USBFS_IRQHandler ; Vector Number 83,USBFS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, = SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDGT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+ B WWDGT_IRQHandler
+
+ PUBWEAK LVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+ B LVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK RCU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+ B RCU_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA0_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+ B DMA0_Channel0_IRQHandler
+
+ PUBWEAK DMA0_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+ B DMA0_Channel1_IRQHandler
+
+ PUBWEAK DMA0_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+ B DMA0_Channel2_IRQHandler
+
+ PUBWEAK DMA0_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+ B DMA0_Channel3_IRQHandler
+
+ PUBWEAK DMA0_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+ B DMA0_Channel4_IRQHandler
+
+ PUBWEAK DMA0_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+ B DMA0_Channel5_IRQHandler
+
+ PUBWEAK DMA0_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+ B DMA0_Channel6_IRQHandler
+
+ PUBWEAK ADC0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_1_IRQHandler
+ B ADC0_1_IRQHandler
+
+ PUBWEAK CAN0_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_TX_IRQHandler
+ B CAN0_TX_IRQHandler
+
+ PUBWEAK CAN0_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX0_IRQHandler
+ B CAN0_RX0_IRQHandler
+
+ PUBWEAK CAN0_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+ B CAN0_RX1_IRQHandler
+
+ PUBWEAK CAN0_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+ B CAN0_EWMC_IRQHandler
+
+ PUBWEAK EXTI5_9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+ B EXTI5_9_IRQHandler
+
+ PUBWEAK TIMER0_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_IRQHandler
+ B TIMER0_BRK_IRQHandler
+
+ PUBWEAK TIMER0_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_IRQHandler
+ B TIMER0_UP_IRQHandler
+
+ PUBWEAK TIMER0_TRG_CMT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_IRQHandler
+ B TIMER0_TRG_CMT_IRQHandler
+
+ PUBWEAK TIMER0_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+ B TIMER0_Channel_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK I2C0_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+ B I2C0_EV_IRQHandler
+
+ PUBWEAK I2C0_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+ B I2C0_ER_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+ B USART0_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI10_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+ B EXTI10_15_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBFS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_WKUP_IRQHandler
+ B USBFS_WKUP_IRQHandler
+
+ PUBWEAK TIMER7_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_BRK_IRQHandler
+ B TIMER7_BRK_IRQHandler
+
+ PUBWEAK TIMER7_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_UP_IRQHandler
+ B TIMER7_UP_IRQHandler
+
+ PUBWEAK TIMER7_TRG_CMT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_TRG_CMT_IRQHandler
+ B TIMER7_TRG_CMT_IRQHandler
+
+ PUBWEAK TIMER7_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_Channel_IRQHandler
+ B TIMER7_Channel_IRQHandler
+
+ PUBWEAK EXMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+ B EXMC_IRQHandler
+
+ PUBWEAK TIMER4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+ B TIMER4_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK TIMER5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler
+ B TIMER5_IRQHandler
+
+ PUBWEAK TIMER6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER6_IRQHandler
+ B TIMER6_IRQHandler
+
+ PUBWEAK DMA1_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+ B DMA1_Channel0_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK ENET_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_WKUP_IRQHandler
+ B ENET_WKUP_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_EWMC_IRQHandler
+ B CAN1_EWMC_IRQHandler
+
+ PUBWEAK USBFS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_IRQHandler
+ B USBFS_IRQHandler
+
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s
new file mode 100644
index 0000000..2b5ce4e
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s
@@ -0,0 +1,489 @@
+;/*!
+; \file startup_gd32f10x_hd.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; top of stack
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
+ DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
+ DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
+ DCD FMC_IRQHandler ; Vector Number 20,FMC
+ DCD RCU_IRQHandler ; Vector Number 21,RCU
+ DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
+ DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
+ DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
+ DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
+ DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
+ DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX
+ DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break
+ DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update
+ DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation
+ DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
+ DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
+ DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
+ DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
+ DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
+ DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
+ DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
+ DCD SPI0_IRQHandler ; Vector Number 51,SPI0
+ DCD SPI1_IRQHandler ; Vector Number 52,SPI1
+ DCD USART0_IRQHandler ; Vector Number 53,USART0
+ DCD USART1_IRQHandler ; Vector Number 54,USART1
+ DCD USART2_IRQHandler ; Vector Number 55,USART2
+ DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
+ DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line
+ DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt
+ DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt
+ DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt
+ DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare
+ DCD ADC2_IRQHandler ; Vector Number 63,ADC2
+ DCD EXMC_IRQHandler ; Vector Number 64,EXMC
+ DCD SDIO_IRQHandler ; Vector Number 65,SDIO
+ DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4
+ DCD SPI2_IRQHandler ; Vector Number 67,SPI2
+ DCD UART3_IRQHandler ; Vector Number 68,UART3
+ DCD UART4_IRQHandler ; Vector Number 69,UART4
+ DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5
+ DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6
+ DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2
+ DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, = SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDGT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+ B WWDGT_IRQHandler
+
+ PUBWEAK LVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+ B LVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK RCU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+ B RCU_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA0_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+ B DMA0_Channel0_IRQHandler
+
+
+ PUBWEAK DMA0_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+ B DMA0_Channel1_IRQHandler
+
+ PUBWEAK DMA0_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+ B DMA0_Channel2_IRQHandler
+
+ PUBWEAK DMA0_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+ B DMA0_Channel3_IRQHandler
+
+ PUBWEAK DMA0_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+ B DMA0_Channel4_IRQHandler
+
+ PUBWEAK DMA0_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+ B DMA0_Channel5_IRQHandler
+
+ PUBWEAK DMA0_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+ B DMA0_Channel6_IRQHandler
+
+ PUBWEAK ADC0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_1_IRQHandler
+ B ADC0_1_IRQHandler
+
+ PUBWEAK USBD_HP_CAN0_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_HP_CAN0_TX_IRQHandler
+ B USBD_HP_CAN0_TX_IRQHandler
+
+ PUBWEAK USBD_LP_CAN0_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_LP_CAN0_RX0_IRQHandler
+ B USBD_LP_CAN0_RX0_IRQHandler
+
+ PUBWEAK CAN0_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+ B CAN0_RX1_IRQHandler
+
+ PUBWEAK CAN0_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+ B CAN0_EWMC_IRQHandler
+
+ PUBWEAK EXTI5_9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+ B EXTI5_9_IRQHandler
+
+ PUBWEAK TIMER0_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_IRQHandler
+ B TIMER0_BRK_IRQHandler
+
+ PUBWEAK TIMER0_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_IRQHandler
+ B TIMER0_UP_IRQHandler
+
+ PUBWEAK TIMER0_TRG_CMT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_IRQHandler
+ B TIMER0_TRG_CMT_IRQHandler
+
+ PUBWEAK TIMER0_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+ B TIMER0_Channel_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK I2C0_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+ B I2C0_EV_IRQHandler
+
+ PUBWEAK I2C0_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+ B I2C0_ER_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+ B USART0_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI10_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+ B EXTI10_15_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBD_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_WKUP_IRQHandler
+ B USBD_WKUP_IRQHandler
+
+ PUBWEAK TIMER7_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_BRK_IRQHandler
+ B TIMER7_BRK_IRQHandler
+
+ PUBWEAK TIMER7_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_UP_IRQHandler
+ B TIMER7_UP_IRQHandler
+
+ PUBWEAK TIMER7_TRG_CMT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_TRG_CMT_IRQHandler
+ B TIMER7_TRG_CMT_IRQHandler
+
+ PUBWEAK TIMER7_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_Channel_IRQHandler
+ B TIMER7_Channel_IRQHandler
+
+ PUBWEAK ADC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+ B ADC2_IRQHandler
+
+ PUBWEAK EXMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+ B EXMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIMER4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+ B TIMER4_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK TIMER5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler
+ B TIMER5_IRQHandler
+
+ PUBWEAK TIMER6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER6_IRQHandler
+ B TIMER6_IRQHandler
+
+ PUBWEAK DMA1_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+ B DMA1_Channel0_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_4_IRQHandler
+ B DMA1_Channel3_4_IRQHandler
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s
new file mode 100644
index 0000000..5fb94f5
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s
@@ -0,0 +1,398 @@
+;/*!
+; \file startup_gd32f10x_md.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; top of stack
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
+ DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
+ DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
+ DCD FMC_IRQHandler ; Vector Number 20,FMC
+ DCD RCU_IRQHandler ; Vector Number 21,RCU
+ DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
+ DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
+ DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
+ DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
+ DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
+ DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX
+ DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break
+ DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update
+ DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation
+ DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
+ DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
+ DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
+ DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
+ DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
+ DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
+ DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
+ DCD SPI0_IRQHandler ; Vector Number 51,SPI0
+ DCD SPI1_IRQHandler ; Vector Number 52,SPI1
+ DCD USART0_IRQHandler ; Vector Number 53,USART0
+ DCD USART1_IRQHandler ; Vector Number 54,USART1
+ DCD USART2_IRQHandler ; Vector Number 55,USART2
+ DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
+ DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXMC_IRQHandler ; Vector Number 64,EXMC
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, = SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDGT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+ B WWDGT_IRQHandler
+
+ PUBWEAK LVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+ B LVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK RCU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+ B RCU_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA0_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+ B DMA0_Channel0_IRQHandler
+
+
+ PUBWEAK DMA0_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+ B DMA0_Channel1_IRQHandler
+
+ PUBWEAK DMA0_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+ B DMA0_Channel2_IRQHandler
+
+ PUBWEAK DMA0_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+ B DMA0_Channel3_IRQHandler
+
+ PUBWEAK DMA0_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+ B DMA0_Channel4_IRQHandler
+
+ PUBWEAK DMA0_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+ B DMA0_Channel5_IRQHandler
+
+ PUBWEAK DMA0_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+ B DMA0_Channel6_IRQHandler
+
+ PUBWEAK ADC0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_1_IRQHandler
+ B ADC0_1_IRQHandler
+
+ PUBWEAK USBD_HP_CAN0_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_HP_CAN0_TX_IRQHandler
+ B USBD_HP_CAN0_TX_IRQHandler
+
+ PUBWEAK USBD_LP_CAN0_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_LP_CAN0_RX0_IRQHandler
+ B USBD_LP_CAN0_RX0_IRQHandler
+
+ PUBWEAK CAN0_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+ B CAN0_RX1_IRQHandler
+
+ PUBWEAK CAN0_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+ B CAN0_EWMC_IRQHandler
+
+ PUBWEAK EXTI5_9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+ B EXTI5_9_IRQHandler
+
+ PUBWEAK TIMER0_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_IRQHandler
+ B TIMER0_BRK_IRQHandler
+
+ PUBWEAK TIMER0_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_IRQHandler
+ B TIMER0_UP_IRQHandler
+
+ PUBWEAK TIMER0_TRG_CMT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_IRQHandler
+ B TIMER0_TRG_CMT_IRQHandler
+
+ PUBWEAK TIMER0_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+ B TIMER0_Channel_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK I2C0_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+ B I2C0_EV_IRQHandler
+
+ PUBWEAK I2C0_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+ B I2C0_ER_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+ B USART0_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI10_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+ B EXTI10_15_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBD_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_WKUP_IRQHandler
+ B USBD_WKUP_IRQHandler
+
+ PUBWEAK EXMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+ B EXMC_IRQHandler
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s
new file mode 100644
index 0000000..74bd753
--- /dev/null
+++ b/boot_source/platform/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s
@@ -0,0 +1,489 @@
+;/*!
+; \file startup_gd32f10x_xd.s
+; \brief start up file
+;
+; \version 2024-01-05, V2.3.0, firmware for GD32F10x
+;*/
+
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+; Copyright (c) 2024, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;*/
+;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; top of stack
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer
+ DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt
+ DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line
+ DCD FMC_IRQHandler ; Vector Number 20,FMC
+ DCD RCU_IRQHandler ; Vector Number 21,RCU
+ DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0
+ DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1
+ DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2
+ DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3
+ DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0
+ DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1
+ DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2
+ DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3
+ DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4
+ DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5
+ DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6
+ DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1
+ DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX
+ DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; Vector Number 40,TIMER0 Break and TIMER8 global
+ DCD TIMER0_UP_TIMER9_IRQHandler ; Vector Number 41,TIMER0 Update and TIMER9 global
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global
+ DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1
+ DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2
+ DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3
+ DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event
+ DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
+ DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event
+ DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
+ DCD SPI0_IRQHandler ; Vector Number 51,SPI0
+ DCD SPI1_IRQHandler ; Vector Number 52,SPI1
+ DCD USART0_IRQHandler ; Vector Number 53,USART0
+ DCD USART1_IRQHandler ; Vector Number 54,USART1
+ DCD USART2_IRQHandler ; Vector Number 55,USART2
+ DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15
+ DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line
+ DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global
+ DCD TIMER7_UP_TIMER12_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 global
+ DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare
+ DCD ADC2_IRQHandler ; Vector Number 63,ADC2
+ DCD EXMC_IRQHandler ; Vector Number 64,EXMC
+ DCD SDIO_IRQHandler ; Vector Number 65,SDIO
+ DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4
+ DCD SPI2_IRQHandler ; Vector Number 67,SPI2
+ DCD UART3_IRQHandler ; Vector Number 68,UART3
+ DCD UART4_IRQHandler ; Vector Number 69,UART4
+ DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5
+ DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6
+ DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2
+ DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, = SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDGT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+ B WWDGT_IRQHandler
+
+ PUBWEAK LVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+ B LVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK RCU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+ B RCU_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA0_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+ B DMA0_Channel0_IRQHandler
+
+
+ PUBWEAK DMA0_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+ B DMA0_Channel1_IRQHandler
+
+ PUBWEAK DMA0_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+ B DMA0_Channel2_IRQHandler
+
+ PUBWEAK DMA0_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+ B DMA0_Channel3_IRQHandler
+
+ PUBWEAK DMA0_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+ B DMA0_Channel4_IRQHandler
+
+ PUBWEAK DMA0_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+ B DMA0_Channel5_IRQHandler
+
+ PUBWEAK DMA0_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+ B DMA0_Channel6_IRQHandler
+
+ PUBWEAK ADC0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_1_IRQHandler
+ B ADC0_1_IRQHandler
+
+ PUBWEAK USBD_HP_CAN0_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_HP_CAN0_TX_IRQHandler
+ B USBD_HP_CAN0_TX_IRQHandler
+
+ PUBWEAK USBD_LP_CAN0_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_LP_CAN0_RX0_IRQHandler
+ B USBD_LP_CAN0_RX0_IRQHandler
+
+ PUBWEAK CAN0_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+ B CAN0_RX1_IRQHandler
+
+ PUBWEAK CAN0_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+ B CAN0_EWMC_IRQHandler
+
+ PUBWEAK EXTI5_9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+ B EXTI5_9_IRQHandler
+
+ PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_TIMER8_IRQHandler
+ B TIMER0_BRK_TIMER8_IRQHandler
+
+ PUBWEAK TIMER0_UP_TIMER9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_TIMER9_IRQHandler
+ B TIMER0_UP_TIMER9_IRQHandler
+
+ PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+ B TIMER0_TRG_CMT_TIMER10_IRQHandler
+
+ PUBWEAK TIMER0_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+ B TIMER0_Channel_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK I2C0_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+ B I2C0_EV_IRQHandler
+
+ PUBWEAK I2C0_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+ B I2C0_ER_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+ B USART0_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI10_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+ B EXTI10_15_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBD_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBD_WKUP_IRQHandler
+ B USBD_WKUP_IRQHandler
+
+ PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_BRK_TIMER11_IRQHandler
+ B TIMER7_BRK_TIMER11_IRQHandler
+
+ PUBWEAK TIMER7_UP_TIMER12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_UP_TIMER12_IRQHandler
+ B TIMER7_UP_TIMER12_IRQHandler
+
+ PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+ B TIMER7_TRG_CMT_TIMER13_IRQHandler
+
+ PUBWEAK TIMER7_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_Channel_IRQHandler
+ B TIMER7_Channel_IRQHandler
+
+ PUBWEAK ADC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+ B ADC2_IRQHandler
+
+ PUBWEAK EXMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+ B EXMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIMER4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+ B TIMER4_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK TIMER5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler
+ B TIMER5_IRQHandler
+
+ PUBWEAK TIMER6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER6_IRQHandler
+ B TIMER6_IRQHandler
+
+ PUBWEAK DMA1_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+ B DMA1_Channel0_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_4_IRQHandler
+ B DMA1_Channel3_4_IRQHandler
+
+ END
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/gd32f10x_it.c b/boot_source/platform/CMSIS/GD/GD32F10x/Source/gd32f10x_it.c
new file mode 100644
index 0000000..24da9d2
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Source/gd32f10x_it.c differ
diff --git a/boot_source/platform/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c b/boot_source/platform/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c
new file mode 100644
index 0000000..9c72dd3
Binary files /dev/null and b/boot_source/platform/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c differ
diff --git a/boot_source/platform/CMSIS/ST/STM32F10x/Source/arm/startup_stm32f10x_cl.s b/boot_source/platform/CMSIS/ST/STM32F10x/Source/arm/startup_stm32f10x_cl.s
index 06d3138..d34c004 100644
Binary files a/boot_source/platform/CMSIS/ST/STM32F10x/Source/arm/startup_stm32f10x_cl.s and b/boot_source/platform/CMSIS/ST/STM32F10x/Source/arm/startup_stm32f10x_cl.s differ
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h
new file mode 100644
index 0000000..b039162
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h
@@ -0,0 +1,364 @@
+/*!
+ \file gd32f10x_adc.h
+ \brief definitions for the ADC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10x_ADC_H
+#define GD32F10x_ADC_H
+
+#include "gd32f10x.h"
+
+/* ADC definitions */
+#define ADC0 ADC_BASE
+#define ADC1 (ADC_BASE + 0x400U)
+#define ADC2 (ADC_BASE + 0x1800U)
+
+/* registers definitions */
+#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
+#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
+#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
+#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
+#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
+#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
+#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
+#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
+#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
+#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
+#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
+#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
+#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
+#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
+#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
+#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
+#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
+#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
+#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
+#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
+
+/* bits definitions */
+/* ADC_STAT */
+#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
+#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
+#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
+#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
+#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
+
+/* ADC_CTL0 */
+#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
+#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
+#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
+#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
+#define ADC_CTL0_SM BIT(8) /*!< scan mode */
+#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
+#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
+#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
+#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
+#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
+#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */
+#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
+#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
+#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
+
+/* ADC_CTL1 */
+#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
+#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
+#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
+#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
+#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
+#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
+#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
+#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
+#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
+#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
+#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
+#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
+#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
+
+/* ADC_SAMPTx x=0..1 */
+#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */
+
+/* ADC_IOFFx x=0..3 */
+#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
+
+/* ADC_WDHT */
+#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
+
+/* ADC_WDLT */
+#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
+
+/* ADC_RSQx x=0..2 */
+#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */
+#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
+
+/* ADC_ISQ */
+#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */
+#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
+
+/* ADC_IDATAx x=0..3*/
+#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */
+
+/* ADC_RDATA */
+#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
+#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */
+
+/* constants definitions */
+/* adc_stat register value */
+#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
+#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
+#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
+#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
+#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
+
+/* adc_ctl0 register value */
+#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
+
+/* scan mode */
+#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
+
+/* inserted channel group convert automatically */
+#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
+
+/* ADC sync mode */
+#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
+#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
+#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
+#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
+#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
+#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
+#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
+#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
+#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
+#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
+#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
+
+/* adc_ctl1 register value */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
+#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
+
+/* continuous mode */
+#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
+
+/* external trigger select for regular channel */
+#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
+/* for ADC0 and ADC1 regular channel */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
+#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */
+#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
+#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
+/* for ADC2 regular channel */
+#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */
+#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */
+#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
+#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */
+#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */
+#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */
+#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */
+
+/* external trigger mode for inserted channel */
+#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
+/* for ADC0 and ADC1 inserted channel */
+#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
+#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */
+#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
+/* for ADC2 inserted channel */
+#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
+#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
+#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */
+#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */
+#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */
+#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */
+#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */
+
+/* adc_samptx register value */
+#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
+#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
+#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
+#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
+#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
+#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
+#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
+#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
+#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
+
+/* adc_ioffx register value */
+#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
+
+/* adc_wdht register value */
+#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
+
+/* adc_wdlt register value */
+#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
+
+/* adc_rsqx register value */
+#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
+
+/* adc_isq register value */
+#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
+
+/* ADC channel group definitions */
+#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
+#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
+#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
+
+#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
+
+/* ADC inserted channel definitions */
+#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
+#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
+#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
+#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
+
+/* ADC channel definitions */
+#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
+#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
+#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
+#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
+#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
+#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
+#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
+#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
+#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
+#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
+#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
+#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
+#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
+#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
+#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
+#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
+#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
+#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
+
+/* ADC interrupt */
+#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
+#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
+#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
+
+/* ADC interrupt flag */
+#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
+#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
+#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
+
+/* function declarations */
+/* initialization config */
+/* reset ADC */
+void adc_deinit(uint32_t adc_periph);
+/* configure the ADC sync mode */
+void adc_mode_config(uint32_t mode);
+/* enable or disable ADC special function */
+void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
+/* configure ADC data alignment */
+void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
+/* enable ADC interface */
+void adc_enable(uint32_t adc_periph);
+/* disable ADC interface */
+void adc_disable(uint32_t adc_periph);
+/* ADC calibration and reset calibration(GD32F10x_MD series without this function) */
+void adc_calibration_enable(uint32_t adc_periph);
+/* enable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_enable(void);
+/* disable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_disable(void);
+
+/* DMA config */
+/* enable DMA request */
+void adc_dma_mode_enable(uint32_t adc_periph);
+/* disable DMA request */
+void adc_dma_mode_disable(uint32_t adc_periph);
+
+/* regular group and inserted group config */
+/* configure ADC discontinuous mode */
+void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
+
+/* configure the length of regular channel group or inserted channel group */
+void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
+/* configure ADC regular channel */
+void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
+/* configure ADC inserted channel */
+void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
+/* configure ADC inserted channel offset */
+void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
+
+/* configure ADC external trigger source */
+void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
+/* configure ADC external trigger */
+void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
+/* enable ADC software trigger */
+void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
+
+/* get channel data */
+/* read ADC regular group data register */
+uint16_t adc_regular_data_read(uint32_t adc_periph);
+/* read ADC inserted group data register */
+uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
+/* read the last ADC0 and ADC1 conversion result data in sync mode */
+uint32_t adc_sync_mode_convert_value_read(void);
+
+/* watchdog config */
+/* configure ADC analog watchdog single channel */
+void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
+/* configure ADC analog watchdog group channel */
+void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
+/* disable ADC analog watchdog */
+void adc_watchdog_disable(uint32_t adc_periph);
+/* configure ADC analog watchdog threshold */
+void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
+
+/* interrupt & flag functions */
+/* get the ADC flag bits */
+FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
+/* clear the ADC flag bits */
+void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
+/* get the bit state of ADCx software start conversion */
+FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
+/* get the bit state of ADCx software inserted channel start conversion */
+FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
+/* get the ADC interrupt bits */
+FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
+/* clear the ADC flag */
+void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
+/* enable ADC interrupt */
+void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
+/* disable ADC interrupt */
+void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
+
+#endif /* GD32F10x_ADC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h
new file mode 100644
index 0000000..465810d
Binary files /dev/null and b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h differ
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_can.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_can.h
new file mode 100644
index 0000000..89f7983
Binary files /dev/null and b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_can.h differ
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h
new file mode 100644
index 0000000..bf8c66b
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h
@@ -0,0 +1,77 @@
+/*!
+ \file gd32f10x_crc.h
+ \brief definitions for the CRC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_CRC_H
+#define GD32F10X_CRC_H
+
+#include "gd32f10x.h"
+
+/* CRC definitions */
+#define CRC CRC_BASE
+
+/* registers definitions */
+#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
+#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
+#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
+
+/* bits definitions */
+/* CRC_DATA */
+#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
+
+/* CRC_FDATA */
+#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
+
+/* CRC_CTL */
+#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
+
+/* function declarations */
+/* deinit CRC calculation unit */
+void crc_deinit(void);
+
+/* reset data register to the value of initializaiton data register */
+void crc_data_register_reset(void);
+/* read the value of the data register */
+uint32_t crc_data_register_read(void);
+
+/* read the value of the free data register */
+uint8_t crc_free_data_register_read(void);
+/* write data to the free data register */
+void crc_free_data_register_write(uint8_t free_data);
+
+/* calculate the CRC value of a 32-bit data */
+uint32_t crc_single_data_calculate(uint32_t sdata);
+/* calculate the CRC value of an array of 32-bit values */
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
+
+#endif /* GD32F10X_CRC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h
new file mode 100644
index 0000000..787838f
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h
@@ -0,0 +1,249 @@
+/*!
+ \file gd32f10x_dac.h
+ \brief definitions for the DAC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_DAC_H
+#define GD32F10X_DAC_H
+
+#include "gd32f10x.h"
+
+/* DACx(x=0) definitions */
+#define DAC0 (DAC_BASE)
+
+/* registers definitions */
+#define DAC_CTL0(dacx) REG32((dacx) + 0x00000000U) /*!< DACx control register 0 */
+#define DAC_SWT(dacx) REG32((dacx) + 0x00000004U) /*!< DACx software trigger register */
+
+#define DAC_OUT0_R12DH(dacx) REG32((dacx) + 0x00000008U) /*!< DACx_OUT0 12-bit right-aligned data holding register */
+#define DAC_OUT0_L12DH(dacx) REG32((dacx) + 0x0000000CU) /*!< DACx_OUT0 12-bit left-aligned data holding register */
+#define DAC_OUT0_R8DH(dacx) REG32((dacx) + 0x00000010U) /*!< DACx_OUT0 8-bit right-aligned data holding register */
+#define DAC_OUT1_R12DH(dacx) REG32((dacx) + 0x00000014U) /*!< DACx_OUT1 12-bit right-aligned data holding register */
+#define DAC_OUT1_L12DH(dacx) REG32((dacx) + 0x00000018U) /*!< DACx_OUT1 12-bit left-aligned data holding register */
+#define DAC_OUT1_R8DH(dacx) REG32((dacx) + 0x0000001CU) /*!< DACx_OUT1 8-bit right-aligned data holding register */
+#define DACC_R12DH(dacx) REG32((dacx) + 0x00000020U) /*!< DACx concurrent mode 12-bit right-aligned data holding register */
+#define DACC_L12DH(dacx) REG32((dacx) + 0x00000024U) /*!< DACx concurrent mode 12-bit left-aligned data holding register */
+#define DACC_R8DH(dacx) REG32((dacx) + 0x00000028U) /*!< DACx concurrent mode 8-bit right-aligned data holding register */
+#define DAC_OUT0_DO(dacx) REG32((dacx) + 0x0000002CU) /*!< DACx_OUT0 data output register */
+#define DAC_OUT1_DO(dacx) REG32((dacx) + 0x00000030U) /*!< DACx_OUT1 data output register */
+
+/* bits definitions */
+/* DAC_CTL0 */
+#define DAC_CTL0_DEN0 BIT(0) /*!< DACx_OUT0 enable */
+#define DAC_CTL0_DBOFF0 BIT(1) /*!< DACx_OUT0 output buffer turn off */
+#define DAC_CTL0_DTEN0 BIT(2) /*!< DACx_OUT0 trigger enable */
+#define DAC_CTL0_DTSEL0 BITS(3,5) /*!< DACx_OUT0 trigger selection */
+#define DAC_CTL0_DWM0 BITS(6,7) /*!< DACx_OUT0 noise wave mode */
+#define DAC_CTL0_DWBW0 BITS(8,11) /*!< DACx_OUT0 noise wave bit width */
+#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
+
+#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable */
+#define DAC_CTL0_DBOFF1 BIT(17) /*!< DACx_OUT1 output buffer turn off */
+#define DAC_CTL0_DTEN1 BIT(18) /*!< DACx_OUT1 trigger enable */
+#define DAC_CTL0_DTSEL1 BITS(19,21) /*!< DACx_OUT1 trigger selection */
+#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */
+#define DAC_CTL0_DWBW1 BITS(24,27) /*!< DACx_OUT1 noise wave bit width */
+#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DACx_OUT1 DMA enable */
+
+/* DAC_SWT */
+#define DAC_SWT_SWTR0 BIT(0) /*!< DACx_OUT0 software trigger */
+#define DAC_SWT_SWTR1 BIT(1) /*!< DACx_OUT1 software trigger */
+
+/* DAC_OUT0_R12DH */
+#define DAC_OUT0_DH_R12 BITS(0,11) /*!< DACx_OUT0 12-bit right-aligned data */
+
+/* DAC_OUT0_L12DH */
+#define DAC_OUT0_DH_L12 BITS(4,15) /*!< DACx_OUT0 12-bit left-aligned data */
+
+/* DAC_OUT0_R8DH */
+#define DAC_OUT0_DH_R8 BITS(0,7) /*!< DACx_OUT0 8-bit right-aligned data */
+
+/* DAC_OUT1_R12DH */
+#define DAC_OUT1_DH_R12 BITS(0,11) /*!< DACx_OUT1 12-bit right-aligned data */
+
+/* DAC_OUT1_L12DH */
+#define DAC_OUT1_DH_L12 BITS(4,15) /*!< DACx_OUT1 12-bit left-aligned data */
+
+/* DAC_OUT1_R8DH */
+#define DAC_OUT1_DH_R8 BITS(0,7) /*!< DACx_OUT1 8-bit right-aligned data */
+
+/* DACC_R12DH */
+#define DACC_OUT0_DH_R12 BITS(0,11) /*!< DAC concurrent mode DACx_OUT0 12-bit right-aligned data */
+#define DACC_OUT1_DH_R12 BITS(16,27) /*!< DAC concurrent mode DACx_OUT1 12-bit right-aligned data */
+
+/* DACC_L12DH */
+#define DACC_OUT0_DH_L12 BITS(4,15) /*!< DAC concurrent mode DACx_OUT0 12-bit left-aligned data */
+#define DACC_OUT1_DH_L12 BITS(20,31) /*!< DAC concurrent mode DACx_OUT1 12-bit left-aligned data */
+
+/* DACC_R8DH */
+#define DACC_OUT0_DH_R8 BITS(0,7) /*!< DAC concurrent mode DACx_OUT0 8-bit right-aligned data */
+#define DACC_OUT1_DH_R8 BITS(8,15) /*!< DAC concurrent mode DACx_OUT1 8-bit right-aligned data */
+
+/* DAC_OUT0_DO */
+#define DAC_OUT0_DO_BITS BITS(0,11) /*!< DACx_OUT0 12-bit output data */
+
+/* DAC_OUT1_DO */
+#define DAC_OUT1_DO_BITS BITS(0,11) /*!< DACx_OUT1 12-bit output data */
+
+/* constants definitions */
+/* DAC trigger source */
+#define CTL0_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define DAC_TRIGGER_T5_TRGO CTL0_DTSEL(0) /*!< TIMER5 TRGO */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define DAC_TRIGGER_T7_TRGO CTL0_DTSEL(1) /*!< TIMER7 TRGO */
+#elif defined(GD32F10X_CL)
+#define DAC_TRIGGER_T2_TRGO CTL0_DTSEL(1) /*!< TIMER2 TRGO */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+#define DAC_TRIGGER_T6_TRGO CTL0_DTSEL(2) /*!< TIMER6 TRGO */
+#define DAC_TRIGGER_T4_TRGO CTL0_DTSEL(3) /*!< TIMER4 TRGO */
+#define DAC_TRIGGER_T1_TRGO CTL0_DTSEL(4) /*!< TIMER1 TRGO */
+#define DAC_TRIGGER_T3_TRGO CTL0_DTSEL(5) /*!< TIMER3 TRGO */
+#define DAC_TRIGGER_EXTI_9 CTL0_DTSEL(6) /*!< EXTI interrupt line9 event */
+#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(7) /*!< software trigger */
+
+/* DAC noise wave mode */
+#define CTL0_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
+#define DAC_WAVE_DISABLE CTL0_DWM(0) /*!< wave disabled */
+#define DAC_WAVE_MODE_LFSR CTL0_DWM(1) /*!< LFSR noise mode */
+#define DAC_WAVE_MODE_TRIANGLE CTL0_DWM(2) /*!< triangle noise mode */
+
+/* DAC noise wave bit width */
+#define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8))
+#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
+#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
+#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
+#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
+#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
+#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
+#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
+#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
+#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
+#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
+#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
+#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
+
+/* unmask LFSR bits in DAC LFSR noise mode */
+#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
+#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
+#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
+#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
+#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
+#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
+#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
+#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
+#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
+#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
+#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
+#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
+
+/* triangle amplitude in DAC triangle noise mode */
+#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
+#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
+#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
+#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
+#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
+#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
+#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
+#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
+#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
+#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
+#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
+#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
+
+/* DAC data alignment */
+#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */
+#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */
+#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */
+
+/* DAC output channel definitions */
+#define DAC_OUT0 ((uint8_t)0x00U) /*!< DACx_OUT0 channel */
+#define DAC_OUT1 ((uint8_t)0x01U) /*!< DACx_OUT1 channel */
+
+/* function declarations */
+/* DAC initialization functions */
+/* deinitialize DAC */
+void dac_deinit(uint32_t dac_periph);
+/* enable DAC */
+void dac_enable(uint32_t dac_periph, uint8_t dac_out);
+/* disable DAC */
+void dac_disable(uint32_t dac_periph, uint8_t dac_out);
+/* enable DAC DMA function */
+void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out);
+/* disable DAC DMA function */
+void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out);
+
+/* DAC buffer functions */
+/* enable DAC output buffer */
+void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out);
+/* disable DAC output buffer */
+void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out);
+
+/* read and write operation functions */
+/* get DAC output value */
+uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out);
+/* set DAC data holding register value */
+void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data);
+
+/* DAC trigger configuration */
+/* enable DAC trigger */
+void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
+/* disable DAC trigger */
+void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out);
+/* configure DAC trigger source */
+void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource);
+/* enable DAC software trigger */
+void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
+
+/* DAC wave mode configuration */
+/* configure DAC wave mode */
+void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode);
+/* configure DAC LFSR noise mode */
+void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits);
+/* configure DAC triangle noise mode */
+void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude);
+
+/* DAC concurrent mode configuration */
+/* enable DAC concurrent mode */
+void dac_concurrent_enable(uint32_t dac_periph);
+/* disable DAC concurrent mode */
+void dac_concurrent_disable(uint32_t dac_periph);
+/* enable DAC concurrent software trigger */
+void dac_concurrent_software_trigger_enable(uint32_t dac_periph);
+/* enable DAC concurrent buffer function */
+void dac_concurrent_output_buffer_enable(uint32_t dac_periph);
+/* disable DAC concurrent buffer function */
+void dac_concurrent_output_buffer_disable(uint32_t dac_periph);
+/* set DAC concurrent mode data holding register value */
+void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1);
+
+#endif /* GD32F10X_DAC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h
new file mode 100644
index 0000000..00095a4
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h
@@ -0,0 +1,148 @@
+/*!
+ \file gd32f10x_dbg.h
+ \brief definitions for the DBG
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_DBG_H
+#define GD32F10X_DBG_H
+
+#include "gd32f10x.h"
+
+/* DBG definitions */
+#define DBG DBG_BASE
+
+/* registers definitions */
+#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
+#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
+
+/* DBG_CTL */
+#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
+#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
+#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
+#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
+#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
+#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
+#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
+#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
+#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
+#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
+#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
+#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
+#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
+#define DBG_CTL_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */
+#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
+#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
+#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
+#ifdef GD32F10X_CL
+#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
+#endif /* GD32F10X_CL */
+#ifdef GD32F10X_XD
+#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */
+#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */
+#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
+#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */
+#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */
+#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */
+#endif /* GD32F10X_XD */
+
+/* constants definitions */
+/* debug hold when core is halted */
+typedef enum
+{
+ DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
+ DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
+ DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
+ DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
+ DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
+ DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
+ DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
+ DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
+ DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
+ DBG_TIMER7_HOLD = BIT(17), /*!< hold TIMER7 counter when core is halted */
+ DBG_TIMER4_HOLD = BIT(18), /*!< hold TIMER4 counter when core is halted */
+ DBG_TIMER5_HOLD = BIT(19), /*!< hold TIMER5 counter when core is halted */
+ DBG_TIMER6_HOLD = BIT(20), /*!< hold TIMER6 counter when core is halted */
+#ifdef GD32F10X_CL
+ DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
+#endif /* GD32F10X_CL */
+#if (defined(GD32F10X_XD) || defined(GD32F10X_CL))
+ DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */
+ DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */
+ DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */
+ DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */
+ DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */
+ DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
+#endif /* GD32F10X_XD || GD32F10X_CL*/
+}dbg_periph_enum;
+
+/* DBG low power mode configurations */
+#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
+
+/* DBG_CTL0_TRACE_MODE configurations */
+#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
+#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
+#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
+#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
+#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
+
+/* function declarations */
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* low power behavior configuration */
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* peripheral behavior configuration */
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+/* trace pin assignment configuration */
+/* enable trace pin assignment */
+void dbg_trace_pin_enable(void);
+/* disable trace pin assignment */
+void dbg_trace_pin_disable(void);
+/* set trace pin mode */
+void dbg_trace_pin_mode_set(uint32_t trace_mode);
+
+#endif /* GD32F10X_DBG_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h
new file mode 100644
index 0000000..e80bfa0
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h
@@ -0,0 +1,285 @@
+/*!
+ \file gd32f10x_dma.h
+ \brief definitions for the DMA
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_DMA_H
+#define GD32F10X_DMA_H
+
+#include "gd32f10x.h"
+
+/* DMA definitions */
+#define DMA0 (DMA_BASE) /*!< DMA0 base address */
+#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
+
+/* registers definitions */
+#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
+#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
+
+#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
+#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
+#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
+#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
+
+#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
+#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
+#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
+#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
+
+#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
+#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
+#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
+#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
+
+#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
+#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
+#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
+#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
+
+#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
+#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
+#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
+#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
+
+#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
+#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
+#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
+#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
+
+#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
+#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
+#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
+#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
+
+/* bits definitions */
+/* DMA_INTF */
+#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
+#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
+#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
+#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
+
+/* DMA_INTC */
+#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
+#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
+#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
+#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
+
+/* DMA_CHxCTL, x=0..6 */
+#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
+#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
+#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
+#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
+#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
+#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
+#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
+#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
+#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
+#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
+
+/* DMA_CHxCNT, x=0..6 */
+#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
+
+/* DMA_CHxPADDR, x=0..6 */
+#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
+
+/* DMA_CHxMADDR, x=0..6 */
+#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
+
+/* constants definitions */
+/* DMA channel select */
+typedef enum
+{
+ DMA_CH0 = 0, /*!< DMA channel 0 */
+ DMA_CH1, /*!< DMA channel 1 */
+ DMA_CH2, /*!< DMA channel 2 */
+ DMA_CH3, /*!< DMA channel 3 */
+ DMA_CH4, /*!< DMA channel 4 */
+ DMA_CH5, /*!< DMA channel 5 */
+ DMA_CH6 /*!< DMA channel 6 */
+} dma_channel_enum;
+
+/* DMA initialize struct */
+typedef struct
+{
+ uint32_t periph_addr; /*!< peripheral base address */
+ uint32_t periph_width; /*!< transfer data size of peripheral */
+ uint32_t memory_addr; /*!< memory base address */
+ uint32_t memory_width; /*!< transfer data size of memory */
+ uint32_t number; /*!< channel transfer number */
+ uint32_t priority; /*!< channel priority level */
+ uint8_t periph_inc; /*!< peripheral increasing mode */
+ uint8_t memory_inc; /*!< memory increasing mode */
+ uint8_t direction; /*!< channel data transfer direction */
+
+} dma_parameter_struct;
+
+#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
+
+/* DMA_register address */
+#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
+#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
+#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
+#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
+
+/* DMA reset value */
+#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
+#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
+#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
+#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
+#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
+ DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
+
+/* DMA_INTF register */
+/* interrupt flag bits */
+#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
+#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
+
+/* flag bits */
+#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
+#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
+#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
+#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
+
+/* DMA_CHxCTL register */
+/* interrupt enable bits */
+#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
+
+/* transfer direction */
+#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
+#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
+/* circular mode */
+#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */
+#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */
+
+/* peripheral increasing mode */
+#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
+#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
+
+/* memory increasing mode */
+#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
+#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
+
+/* transfer data size of peripheral */
+#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
+#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
+#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
+#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
+
+/* transfer data size of memory */
+#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
+#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
+#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
+#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
+
+/* channel priority level */
+#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
+#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
+#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
+#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
+#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
+
+/* memory to memory mode */
+#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */
+#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */
+
+/* DMA_CHxCNT register */
+/* transfer counter */
+#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
+
+/* function declarations */
+/* DMA deinitialization and initialization functions */
+/* deinitialize DMA a channel registers */
+void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
+/* initialize the parameters of DMA struct with the default values */
+void dma_struct_para_init(dma_parameter_struct* init_struct);
+/* initialize DMA channel */
+void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
+/* enable DMA circulation mode */
+void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable DMA circulation mode */
+void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable memory to memory mode */
+void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable memory to memory mode */
+void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable DMA channel */
+void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable DMA channel */
+void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
+
+/* DMA configuration functions */
+/* set DMA peripheral base address */
+void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
+/* set DMA memory base address */
+void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
+/* set the number of remaining data to be transferred by the DMA */
+void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
+/* get the number of remaining data to be transferred by the DMA */
+uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
+/* configure priority level of DMA channel */
+void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
+/* configure transfer data size of memory */
+void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
+/* configure transfer data size of peripheral */
+void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
+/* enable next address increasement algorithm of memory */
+void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable next address increasement algorithm of memory */
+void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable next address increasement algorithm of peripheral */
+void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable next address increasement algorithm of peripheral */
+void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* configure the direction of data transfer on the channel */
+void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
+
+/* flag and interrupt functions */
+/* check DMA flag is set or not */
+FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* clear the flag of a DMA channel */
+void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* check DMA flag and interrupt enable bit is set or not */
+FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* clear the interrupt flag of a DMA channel */
+void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* enable DMA interrupt */
+void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
+/* disable DMA interrupt */
+void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
+
+#endif /* GD32F10X_DMA_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h
new file mode 100644
index 0000000..be14eab
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h
@@ -0,0 +1,1494 @@
+/*!
+ \file gd32f10x_enet.h
+ \brief definitions for the ENET
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10x_ENET_H
+#define GD32F10x_ENET_H
+
+#include "gd32f10x.h"
+#include
+
+#define IF_USE_EXTERNPHY_LIB 0
+#if (1 == IF_USE_EXTERNPHY_LIB)
+#include "phy.h"
+#endif
+
+#ifndef ENET_RXBUF_NUM
+#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */
+#endif
+
+#ifndef ENET_TXBUF_NUM
+#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */
+#endif
+
+#ifndef ENET_RXBUF_SIZE
+#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */
+#endif
+
+#ifndef ENET_TXBUF_SIZE
+#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */
+#endif
+
+/* #define USE_DELAY */
+
+#ifndef _PHY_H_
+#define DP83848 0
+#define LAN8700 1
+#define PHY_TYPE DP83848
+
+#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */
+
+/* PHY read write timeouts */
+#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */
+#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */
+
+/* PHY delay */
+#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */
+#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */
+
+/* PHY register address */
+#define PHY_REG_BCR 0U /*!< tranceiver basic control register */
+#define PHY_REG_BSR 1U /*!< tranceiver basic status register */
+
+/* PHY basic control register */
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */
+
+/* PHY basic status register */
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */
+
+#if(PHY_TYPE == LAN8700)
+#define PHY_SR 31U /*!< tranceiver status register */
+#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */
+#elif(PHY_TYPE == DP83848)
+#define PHY_SR 16U /*!< tranceiver status register */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */
+#endif /* PHY_TYPE */
+
+#endif /* _PHY_H_ */
+
+
+/* ENET definitions */
+#define ENET ENET_BASE
+
+/* registers definitions */
+#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */
+#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */
+#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */
+#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */
+#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */
+#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC PHY data register */
+#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */
+#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */
+#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */
+#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */
+#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */
+#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */
+#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */
+#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */
+#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */
+#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */
+#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */
+#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */
+#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */
+#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */
+#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */
+
+#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */
+#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */
+#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */
+#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */
+#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */
+#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */
+#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */
+#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */
+#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */
+#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */
+#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */
+
+#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */
+#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */
+#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */
+#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */
+#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */
+#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */
+#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */
+#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */
+#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */
+
+#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */
+#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */
+#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */
+#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */
+#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */
+#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */
+#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */
+#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */
+#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */
+#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */
+#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */
+#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */
+#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */
+
+/* bits definitions */
+/* ENET_MAC_CFG */
+#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */
+#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */
+#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */
+#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */
+#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */
+#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */
+#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */
+#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */
+#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */
+#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */
+#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */
+#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */
+#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */
+#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */
+#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */
+
+/* ENET_MAC_FRMF */
+#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */
+#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */
+#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */
+#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */
+#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */
+#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */
+#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */
+#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */
+#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */
+#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */
+#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */
+
+/* ENET_MAC_HLH */
+#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */
+
+/* ENET_MAC_HLL */
+#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */
+
+/* ENET_MAC_PHY_CTL */
+#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */
+#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */
+#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */
+#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */
+#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */
+
+/* ENET_MAC_PHY_DATA */
+#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */
+
+/* ENET_MAC_FCTL */
+#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */
+#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */
+#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */
+#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */
+#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */
+#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */
+#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */
+
+/* ENET_MAC_FCTH */
+#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */
+#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */
+
+/* ENET_MAC_VLT */
+#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */
+#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */
+
+/* ENET_MAC_RWFF */
+#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */
+
+/* ENET_MAC_WUM */
+#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */
+#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */
+#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */
+#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */
+#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */
+#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */
+#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */
+
+/* ENET_MAC_INTF */
+#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */
+#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */
+#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */
+#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */
+#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */
+
+/* ENET_MAC_INTMSK */
+#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */
+#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */
+
+/* ENET_MAC_ADDR0H */
+#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */
+#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */
+
+/* ENET_MAC_ADDR0L */
+#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */
+
+/* ENET_MAC_ADDR1H */
+#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */
+#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */
+#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */
+#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */
+
+/* ENET_MAC_ADDR1L */
+#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */
+
+/* ENET_MAC_ADDR2H */
+#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */
+#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */
+#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */
+#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */
+
+/* ENET_MAC_ADDR2L */
+#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */
+
+/* ENET_MAC_ADDR3H */
+#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */
+#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */
+#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */
+#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */
+
+/* ENET_MAC_ADDR3L */
+#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */
+
+/* ENET_MSC_CTL */
+#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */
+#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */
+#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */
+#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */
+
+/* ENET_MSC_RINTF */
+#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */
+#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */
+#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */
+
+/* ENET_MSC_TINTF */
+#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */
+#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */
+#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */
+
+/* ENET_MSC_RINTMSK */
+#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */
+#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */
+#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */
+
+/* ENET_MSC_TINTMSK */
+#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */
+#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */
+#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */
+
+/* ENET_MSC_SCCNT */
+#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */
+
+/* ENET_MSC_MSCCNT */
+#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */
+
+/* ENET_MSC_TGFCNT */
+#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */
+
+/* ENET_MSC_RFCECNT */
+#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */
+
+/* ENET_MSC_RFAECNT */
+#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */
+
+/* ENET_MSC_RGUFCNT */
+#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */
+
+/* ENET_PTP_TSCTL */
+#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */
+#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */
+#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */
+#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */
+#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */
+#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */
+
+/* ENET_PTP_SSINC */
+#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */
+
+/* ENET_PTP_TSH */
+#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */
+
+/* ENET_PTP_TSL */
+#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */
+#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */
+
+/* ENET_PTP_TSUH */
+#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */
+
+/* ENET_PTP_TSUL */
+#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */
+#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */
+
+/* ENET_PTP_TSADDEND */
+#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */
+
+/* ENET_PTP_ETH */
+#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */
+
+/* ENET_PTP_ETL */
+#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */
+
+/* ENET_DMA_BCTL */
+#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */
+#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */
+#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */
+#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */
+#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */
+#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */
+#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */
+#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */
+#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */
+#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */
+
+/* ENET_DMA_TPEN */
+#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */
+
+/* ENET_DMA_RPEN */
+#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */
+
+/* ENET_DMA_RDTADDR */
+#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */
+
+/* ENET_DMA_TDTADDR */
+#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */
+
+/* ENET_DMA_STAT */
+#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */
+#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */
+#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */
+#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */
+#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */
+#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */
+#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */
+#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */
+#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */
+#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */
+#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */
+#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */
+#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */
+#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */
+#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */
+#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */
+#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */
+#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */
+#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */
+#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */
+#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */
+
+/* ENET_DMA_CTL */
+#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */
+#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */
+#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */
+#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */
+#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */
+#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */
+#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */
+#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */
+#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */
+#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */
+#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */
+#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */
+
+/* ENET_DMA_INTEN */
+#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */
+#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */
+#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */
+#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */
+#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */
+#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */
+#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */
+#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */
+#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */
+#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */
+#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */
+#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */
+#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */
+#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */
+#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */
+
+/* ENET_DMA_MFBOCNT */
+#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */
+#define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */
+#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */
+#define ENET_DMA_MFBOCNT_OBFOC BIT(28) /*!< Overflow bit for FIFO overflow counter */
+
+/* ENET_DMA_CTDADDR */
+#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */
+
+/* ENET_DMA_CRDADDR */
+#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */
+
+/* ENET_DMA_CTBADDR */
+#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */
+
+/* ENET_DMA_CRBADDR */
+#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */
+
+/* ENET DMA Tx descriptor TDES0 */
+#define ENET_TDES0_DB BIT(0) /*!< deferred */
+#define ENET_TDES0_UFE BIT(1) /*!< underflow error */
+#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */
+#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */
+#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */
+#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */
+#define ENET_TDES0_LCO BIT(9) /*!< late collision */
+#define ENET_TDES0_NCA BIT(10) /*!< no carrier */
+#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */
+#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */
+#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */
+#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */
+#define ENET_TDES0_ES BIT(15) /*!< error summary */
+#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */
+#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */
+#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */
+#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/
+#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */
+#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */
+#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */
+#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */
+#define ENET_TDES0_FSG BIT(28) /*!< first segment */
+#define ENET_TDES0_LSG BIT(29) /*!< last segment */
+#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */
+#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */
+
+/* ENET DMA Tx descriptor TDES1 */
+#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */
+#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */
+
+/* ENET DMA Tx descriptor TDES2 */
+#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */
+
+/* ENET DMA Tx descriptor TDES3 */
+#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
+
+/* ENET DMA Rx descriptor RDES0 */
+#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */
+#define ENET_RDES0_CERR BIT(1) /*!< CRC error */
+#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */
+#define ENET_RDES0_RERR BIT(3) /*!< receive error */
+#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */
+#define ENET_RDES0_FRMT BIT(5) /*!< frame type */
+#define ENET_RDES0_LCO BIT(6) /*!< late collision */
+#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */
+#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */
+#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */
+#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */
+#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */
+#define ENET_RDES0_LERR BIT(12) /*!< length error */
+#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */
+#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */
+#define ENET_RDES0_ERRS BIT(15) /*!< error summary */
+#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */
+#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */
+#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */
+
+/* ENET DMA Rx descriptor RDES1 */
+#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */
+#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */
+#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/
+#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */
+#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */
+
+/* ENET DMA Rx descriptor RDES2 */
+#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */
+
+/* ENET DMA Rx descriptor RDES3 */
+#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */
+
+/* constants definitions */
+/* define bit position and its register index offset */
+#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6)))
+#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
+
+/* ENET clock range judgement */
+#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m)))
+
+/* define MAC address configuration and reference address */
+#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4])
+#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0])
+#define ENET_ADDRH_BASE ((ENET) + 0x40U)
+#define ENET_ADDRL_BASE ((ENET) + 0x44U)
+#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU))
+
+/* register offset */
+#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */
+#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */
+#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */
+#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */
+
+#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */
+#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */
+#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */
+#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */
+#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */
+#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */
+#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */
+#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */
+#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */
+#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */
+
+#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */
+#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */
+#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */
+#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */
+#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */
+#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */
+#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */
+#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */
+
+/* ENET status flag get */
+typedef enum
+{
+ /* ENET_MAC_WUM register */
+ ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */
+ ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */
+ /* ENET_MAC_FCTL register */
+ ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */
+ /* ENET_MAC_INTF register */
+ ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */
+ ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */
+ ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */
+ ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */
+ ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */
+ /* ENET_MSC_RINTF register */
+ ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */
+ ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */
+ ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */
+ /* ENET_MSC_TINTF register */
+ ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */
+ ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */
+ ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */
+ /* ENET_DMA_STAT register */
+ ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
+ ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
+ ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
+ ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
+ ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
+ ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
+ ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
+ ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
+ ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
+ ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
+ ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
+ ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
+ ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
+ ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
+ ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
+ ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */
+ ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */
+ ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */
+ ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */
+ ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */
+ ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */
+}enet_flag_enum;
+
+/* ENET stutus flag clear */
+typedef enum
+{
+ /* ENET_DMA_STAT register */
+ ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
+ ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
+ ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
+ ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
+ ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
+ ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
+ ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
+ ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
+ ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
+ ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
+ ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
+ ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
+ ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
+ ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
+ ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
+}enet_flag_clear_enum;
+
+/* ENET interrupt enable/disable */
+typedef enum
+{
+ /* ENET_MAC_INTMSK register */
+ ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */
+ ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */
+ /* ENET_MSC_RINTMSK register */
+ ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */
+ ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */
+ ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */
+ /* ENET_MSC_TINTMSK register */
+ ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */
+ ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */
+ ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */
+ /* ENET_DMA_INTEN register */
+ ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */
+ ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */
+ ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */
+ ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */
+ ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */
+ ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */
+ ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */
+ ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */
+ ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */
+ ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */
+ ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */
+ ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */
+ ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */
+ ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */
+ ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */
+}enet_int_enum;
+
+/* ENET interrupt flag get */
+typedef enum
+{
+ /* ENET_MAC_INTF register */
+ ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */
+ ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */
+ ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */
+ ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */
+ ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */
+ /* ENET_MSC_RINTF register */
+ ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */
+ ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */
+ ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */
+ /* ENET_MSC_TINTF register */
+ ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */
+ ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */
+ ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */
+ /* ENET_DMA_STAT register */
+ ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
+ ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
+ ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
+ ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
+ ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
+ ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
+ ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
+ ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
+ ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
+ ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
+ ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
+ ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
+ ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
+ ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
+ ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
+ ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */
+ ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */
+ ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */
+}enet_int_flag_enum;
+
+/* ENET interrupt flag clear */
+typedef enum
+{
+ /* ENET_DMA_STAT register */
+ ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */
+ ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */
+ ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */
+ ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */
+ ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */
+ ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */
+ ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */
+ ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */
+ ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */
+ ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */
+ ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */
+ ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */
+ ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */
+ ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */
+ ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */
+}enet_int_flag_clear_enum;
+
+/* current RX/TX descriptor/buffer/descriptor table address get */
+typedef enum
+{
+ ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */
+ ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */
+ ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */
+ ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */
+ ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */
+ ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */
+}enet_desc_reg_enum;
+
+/* MAC statistics counter get */
+typedef enum
+{
+ ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */
+ ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */
+ ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */
+ ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */
+ ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */
+ ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */
+}enet_msc_counter_enum;
+
+/* function option, used for ENET initialization */
+typedef enum
+{
+ FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */
+ DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */
+ DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */
+ DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */
+ STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */
+ DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */
+ VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */
+ FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */
+ HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */
+ HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */
+ FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */
+ HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */
+ TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */
+ INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */
+}enet_option_enum;
+
+/* phy mode and mac loopback configurations */
+typedef enum
+{
+ ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */
+ ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */
+ ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */
+ ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */
+ ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */
+ ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */
+}enet_mediamode_enum;
+
+/* IP frame checksum function */
+typedef enum
+{
+ ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */
+ ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */
+ ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame
+ with only payload error but no other errors will not be dropped */
+}enet_chksumconf_enum;
+
+/* received frame filter function */
+typedef enum
+{
+ ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */
+ ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */
+ ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */
+ ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */
+}enet_frmrecept_enum;
+
+/* register group value get */
+typedef enum
+{
+ ALL_MAC_REG = 0, /*!< MAC register group */
+ ALL_MSC_REG = 22, /*!< MSC register group */
+ ALL_PTP_REG = 33, /*!< PTP register group */
+ ALL_DMA_REG = 44, /*!< DMA register group */
+}enet_registers_type_enum;
+
+/* dma direction select */
+typedef enum
+{
+ ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */
+ ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */
+}enet_dmadirection_enum;
+
+/* PHY operation direction select */
+typedef enum
+{
+ ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */
+ ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */
+}enet_phydirection_enum;
+
+/* register operation direction select */
+typedef enum
+{
+ ENET_REG_READ, /*!< read register */
+ ENET_REG_WRITE /*!< write register */
+}enet_regdirection_enum;
+
+/* ENET MAC addresses */
+typedef enum
+{
+ ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */
+ ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */
+ ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */
+ ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */
+}enet_macaddress_enum;
+
+/* descriptor information */
+typedef enum
+{
+ TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */
+ TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */
+ RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */
+ RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */
+ RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */
+ RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */
+}enet_descstate_enum;
+
+/* structure for initialization of the ENET */
+typedef struct
+{
+ uint32_t option_enable; /*!< select which function to configure */
+ uint32_t forward_frame; /*!< frame forward related parameters */
+ uint32_t dmabus_mode; /*!< DMA bus mode related parameters */
+ uint32_t dma_maxburst; /*!< DMA max burst related parameters */
+ uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */
+ uint32_t store_forward_mode; /*!< store forward mode related parameters */
+ uint32_t dma_function; /*!< DMA control related parameters */
+ uint32_t vlan_config; /*!< VLAN tag related parameters */
+ uint32_t flow_control; /*!< flow control related parameters */
+ uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */
+ uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */
+ uint32_t framesfilter_mode; /*!< frame filter control related parameters */
+ uint32_t halfduplex_param; /*!< halfduplex related parameters */
+ uint32_t timer_config; /*!< frame timer related parameters */
+ uint32_t interframegap; /*!< inter frame gap related parameters */
+}enet_initpara_struct;
+
+/* structure for ENET DMA desciptors */
+typedef struct
+{
+ uint32_t status; /*!< status */
+ uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */
+ uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */
+ uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */
+} enet_descriptors_struct;
+
+/* structure of PTP system time */
+typedef struct
+{
+ uint32_t second; /*!< second of system time */
+ uint32_t nanosecond; /*!< nanosecond of system time */
+ uint32_t sign; /*!< sign of system time */
+}enet_ptp_systime_struct;
+
+/* mac_cfg register value */
+#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */
+#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */
+#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */
+#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */
+#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */
+
+#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */
+#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */
+#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */
+#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */
+#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */
+#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */
+#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */
+#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */
+#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */
+
+#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */
+#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */
+
+#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */
+#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */
+
+#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */
+#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */
+
+#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */
+#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */
+
+#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */
+#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */
+
+#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */
+#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */
+
+#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */
+#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */
+
+#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */
+#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */
+
+#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/
+#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */
+
+#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */
+#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */
+#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */
+
+#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */
+#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */
+
+/* mac_frmf register value */
+#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */
+#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */
+#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */
+#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */
+#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */
+
+#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */
+#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */
+
+#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */
+#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */
+#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */
+#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */
+#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */
+
+#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */
+#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */
+
+#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */
+#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */
+#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */
+
+#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */
+#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */
+
+#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */
+#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */
+#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */
+#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */
+#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */
+#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */
+#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */
+
+#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */
+#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */
+#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */
+#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */
+
+/* mac_phy_ctl register value */
+#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */
+#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */
+#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */
+
+#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */
+
+#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */
+
+/* mac_phy_data register value */
+#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */
+
+/* mac_fctl register value */
+#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */
+#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */
+#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */
+#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */
+#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */
+
+#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */
+#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */
+#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */
+
+#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */
+#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */
+
+#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */
+#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */
+#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */
+
+#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */
+#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */
+#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */
+
+#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */
+#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */
+#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */
+
+#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */
+/* mac_vlt register value */
+#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */
+
+#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */
+#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */
+
+/* mac_wum register value */
+#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */
+#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */
+#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */
+#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */
+#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */
+#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */
+#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */
+
+/* mac_addr0h register value */
+#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */
+
+/* mac_addrxh register value, x = 1,2,3 */
+#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */
+
+#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */
+#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */
+#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */
+#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */
+#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */
+#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */
+
+#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */
+#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */
+
+/* mac_fcth register value */
+#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */
+#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */
+#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */
+#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */
+#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */
+#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */
+#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */
+#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */
+
+#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */
+#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */
+#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */
+#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */
+#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */
+#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */
+#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */
+#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */
+
+/* msc_ctl register value */
+#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */
+#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */
+#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */
+
+/* ptp_tsctl register value */
+#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */
+#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */
+
+/* ptp_ssinc register value */
+#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */
+
+/* ptp_tsl register value */
+#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */
+
+#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */
+#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */
+
+#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */
+
+/* ptp_tsul register value */
+#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */
+
+#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */
+#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */
+
+/* dma_bctl register value */
+#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */
+#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */
+
+#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */
+#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */
+#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */
+#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */
+#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */
+#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */
+#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */
+#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */
+#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */
+#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */
+#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */
+#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */
+#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */
+
+#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */
+#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/
+#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/
+#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */
+#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */
+#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */
+
+#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */
+#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */
+
+#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */
+#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */
+#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */
+#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */
+#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */
+#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */
+#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */
+#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */
+#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */
+#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */
+#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */
+#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */
+#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */
+
+#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */
+#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */
+
+#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */
+#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */
+
+/* dma_stat register value */
+#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */
+#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */
+#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */
+#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */
+#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */
+#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */
+#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */
+
+#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */
+#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */
+#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */
+#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */
+#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */
+#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */
+#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */
+
+#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */
+#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */
+#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */
+#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */
+
+/* dma_ctl register value */
+#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */
+#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */
+#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */
+#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */
+#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */
+
+#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */
+#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */
+#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */
+#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */
+#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */
+#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */
+#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */
+#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */
+#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */
+
+#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */
+#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */
+
+#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */
+#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */
+
+#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */
+#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */
+#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */
+
+#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */
+#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */
+
+#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2) /*!< all frame received with error except runt error are forwarded to memory */
+#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */
+#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2) /*!< the function that all frame received with error except runt error are forwarded to memory */
+
+#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2) /*!< forward undersized good frames */
+#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */
+#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2) /*!< the function that forwarding undersized good frames */
+
+#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/
+#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */
+#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */
+
+/* dma_mfbocnt register value */
+#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */
+
+#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */
+
+/* dma tx descriptor tdes0 register value */
+#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */
+#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */
+
+#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */
+#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */
+#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */
+#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */
+#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */
+
+/* dma tx descriptor tdes1 register value */
+#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */
+
+#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */
+
+/* dma rx descriptor rdes0 register value */
+#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */
+#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */
+
+/* dma rx descriptor rdes1 register value */
+#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */
+#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */
+
+#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */
+
+#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */
+
+/* dma rx descriptor rdes4 register value */
+#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */
+#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */
+
+#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */
+#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */
+
+/* ENET register mask value */
+#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */
+#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */
+#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */
+#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */
+
+#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */
+#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */
+
+typedef enum{
+ ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */
+ ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */
+ ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */
+ ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */
+ ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */
+}enet_ptp_function_enum;
+
+
+/* ENET remote wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */
+
+/* ENET frame size */
+#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */
+
+/* ENET delay timeout */
+#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */
+#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */
+
+/* function declarations */
+/* main function */
+/* deinitialize the ENET, and reset structure parameters for ENET initialization */
+void enet_deinit(void);
+/* configure the parameters which are usually less cared for initialization */
+void enet_initpara_config(enet_option_enum option, uint32_t para);
+/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */
+ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept);
+/* reset all core internal registers located in CLK_TX and CLK_RX */
+ErrStatus enet_software_reset(void);
+/* check receive frame valid and return frame size */
+uint32_t enet_rxframe_size_get(void);
+/* initialize the dma tx/rx descriptors's parameters in chain mode */
+void enet_descriptors_chain_init(enet_dmadirection_enum direction);
+/* initialize the dma tx/rx descriptors's parameters in ring mode */
+void enet_descriptors_ring_init(enet_dmadirection_enum direction);
+/* handle current received frame data to application buffer */
+ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize);
+/* handle current received frame but without data copy to application buffer */
+#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U)
+/* handle application buffer data to transmit it */
+ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length);
+/* handle current transmit frame but without data copy from application buffer */
+#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len))
+/* configure the transmit IP frame checksum offload calculation and insertion */
+void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum);
+/* ENET Tx and Rx function enable (include MAC and DMA module) */
+void enet_enable(void);
+/* ENET Tx and Rx function disable (include MAC and DMA module) */
+void enet_disable(void);
+/* configure MAC address */
+void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]);
+/* get MAC address */
+void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]);
+
+/* get the ENET MAC/MSC/PTP/DMA status flag */
+FlagStatus enet_flag_get(enet_flag_enum enet_flag);
+/* clear the ENET DMA status flag */
+void enet_flag_clear(enet_flag_clear_enum enet_flag);
+/* enable ENET MAC/MSC/DMA interrupt */
+void enet_interrupt_enable(enet_int_enum enet_int);
+/* disable ENET MAC/MSC/DMA interrupt */
+void enet_interrupt_disable(enet_int_enum enet_int);
+/* get ENET MAC/MSC/DMA interrupt flag */
+FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag);
+/* clear ENET DMA interrupt flag */
+void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear);
+
+/* MAC function */
+/* ENET Tx function enable (include MAC and DMA module) */
+void enet_tx_enable(void);
+/* ENET Tx function disable (include MAC and DMA module) */
+void enet_tx_disable(void);
+/* ENET Rx function enable (include MAC and DMA module) */
+void enet_rx_enable(void);
+/* ENET Rx function disable (include MAC and DMA module) */
+void enet_rx_disable(void);
+/* put registers value into the application buffer */
+void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num);
+/* enable the MAC address filter */
+void enet_address_filter_enable(enet_macaddress_enum mac_addr);
+/* disable the MAC address filter */
+void enet_address_filter_disable(enet_macaddress_enum mac_addr);
+/* configure the MAC address filter */
+void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type);
+/* PHY interface configuration (configure SMI clock and reset PHY chip) */
+ErrStatus enet_phy_config(void);
+/* write to/read from a PHY register */
+ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue);
+/* enable the loopback function of phy chip */
+ErrStatus enet_phyloopback_enable(void);
+/* disable the loopback function of phy chip */
+ErrStatus enet_phyloopback_disable(void);
+/* enable ENET forward feature */
+void enet_forward_feature_enable(uint32_t feature);
+/* disable ENET forward feature */
+void enet_forward_feature_disable(uint32_t feature);
+/* enable ENET filter feature */
+void enet_fliter_feature_enable(uint32_t feature);
+/* disable ENET filter feature */
+void enet_fliter_feature_disable(uint32_t feature);
+
+/* flow control function */
+/* generate the pause frame, ENET will send pause frame after enable transmit flow control */
+ErrStatus enet_pauseframe_generate(void);
+/* configure the pause frame detect type */
+void enet_pauseframe_detect_config(uint32_t detect);
+/* configure the pause frame parameters */
+void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold);
+/* configure the threshold of the flow control(deactive and active threshold) */
+void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active);
+/* enable ENET flow control feature */
+void enet_flowcontrol_feature_enable(uint32_t feature);
+/* disable ENET flow control feature */
+void enet_flowcontrol_feature_disable(uint32_t feature);
+
+/* DMA function */
+/* get the dma transmit/receive process state */
+uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction);
+/* poll the dma transmission/reception enable */
+void enet_dmaprocess_resume(enet_dmadirection_enum direction);
+/* check and recover the Rx process */
+void enet_rxprocess_check_recovery(void);
+/* flush the ENET transmit fifo, and wait until the flush operation completes */
+ErrStatus enet_txfifo_flush(void);
+/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */
+uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get);
+/* get the Tx or Rx descriptor information */
+uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get);
+/* get the number of missed frames during receiving */
+void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop);
+
+/* descriptor function */
+/* get the bit flag of ENET dma descriptor */
+FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag);
+/* set the bit flag of ENET dma tx descriptor */
+void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag);
+/* clear the bit flag of ENET dma tx descriptor */
+void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag);
+/* when receiving the completed, set RS bit in ENET_DMA_STAT register will set */
+void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc);
+/* when receiving the completed, set RS bit in ENET_DMA_STAT register will not set */
+void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc);
+/* drop current receive frame */
+void enet_rxframe_drop(void);
+/* enable DMA feature */
+void enet_dma_feature_enable(uint32_t feature);
+/* disable DMA feature */
+void enet_dma_feature_disable(uint32_t feature);
+
+/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */
+void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
+/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */
+void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab);
+/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */
+ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]);
+/* handle current received frame but without data copy to application buffer in PTP normal mode */
+#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr))
+/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */
+ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]);
+/* handle current transmit frame but without data copy from application buffer in PTP normal mode */
+#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr))
+
+/* WUM function */
+/* wakeup frame filter register pointer reset */
+void enet_wum_filter_register_pointer_reset(void);
+/* set the remote wakeup frame registers */
+void enet_wum_filter_config(uint32_t pdata[]);
+/* enable wakeup management features */
+void enet_wum_feature_enable(uint32_t feature);
+/* disable wakeup management features */
+void enet_wum_feature_disable(uint32_t feature);
+
+/* MSC function */
+/* reset the MAC statistics counters */
+void enet_msc_counters_reset(void);
+/* enable the MAC statistics counter features */
+void enet_msc_feature_enable(uint32_t feature);
+/* disable the MAC statistics counter features */
+void enet_msc_feature_disable(uint32_t feature);
+/* get MAC statistics counter */
+uint32_t enet_msc_counters_get(enet_msc_counter_enum counter);
+
+/* PTP function */
+/* change subsecond to nanosecond */
+uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond);
+/* change nanosecond to subsecond */
+uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond);
+/* enable the PTP features */
+void enet_ptp_feature_enable(uint32_t feature);
+/* disable the PTP features */
+void enet_ptp_feature_disable(uint32_t feature);
+/* configure the PTP timestamp function */
+ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func);
+/* configure the PTP system time subsecond increment value */
+void enet_ptp_subsecond_increment_config(uint32_t subsecond);
+/* adjusting the PTP clock frequency only in fine update mode */
+void enet_ptp_timestamp_addend_config(uint32_t add);
+/* initializing or adding/subtracting to second of the PTP system time */
+void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond);
+/* configure the PTP expected target time */
+void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond);
+/* get the PTP current system time */
+void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct);
+/* configure and start PTP timestamp counter */
+void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg);
+/* adjust frequency in fine method by configure addend register */
+void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg);
+/* update system time in coarse method */
+void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct);
+/* set system time in fine method */
+void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct);
+/* get the ptp flag status */
+FlagStatus enet_ptp_flag_get(uint32_t flag);
+
+/* internal function */
+/* reset the ENET initpara struct, call it before using enet_initpara_config() */
+void enet_initpara_reset(void);
+/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */
+static void enet_default_init(void);
+#ifdef USE_DELAY
+/* user can provide more timing precise _ENET_DELAY_ function */
+#define _ENET_DELAY_ delay_ms
+#else
+/* insert a delay time */
+static void enet_delay(uint32_t ncount);
+/* default _ENET_DELAY_ function with less precise timing */
+#define _ENET_DELAY_ enet_delay
+#endif
+
+#endif /* GD32F10X_ENET_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h
new file mode 100644
index 0000000..3116d95
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h
@@ -0,0 +1,428 @@
+/*!
+ \file gd32f10x_exmc.h
+ \brief definitions for the EXMC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_EXMC_H
+#define GD32F10X_EXMC_H
+
+#include "gd32f10x.h"
+
+/* EXMC definitions */
+#define EXMC (EXMC_BASE) /*!< EXMC register base address */
+
+/* registers definitions */
+/* NOR/PSRAM */
+#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
+#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
+#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
+
+#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */
+#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */
+#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */
+
+#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */
+#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */
+#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */
+
+#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */
+#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */
+#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */
+
+/* NAND/PC card */
+#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */
+#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */
+#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */
+#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */
+#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */
+
+#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */
+#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */
+#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */
+#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */
+#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */
+
+#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */
+#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */
+#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */
+#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */
+#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */
+
+/* bits definitions */
+/* NOR/PSRAM */
+/* EXMC_SNCTLx,x=0..3 */
+#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
+#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
+#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
+#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
+#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
+#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
+#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
+#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
+#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
+#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
+#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
+#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
+#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
+#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */
+
+/* EXMC_SNTCFGx,x=0..3 */
+#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
+#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
+#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
+#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
+#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
+#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */
+#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
+
+/* EXMC_SNWTCFGx,x=0..3 */
+#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */
+#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */
+#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */
+#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
+#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */
+#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
+
+/* NAND/PC card */
+/* EXMC_NPCTLx,x=1..3 */
+#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
+#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
+#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
+#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
+#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
+#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
+#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
+#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
+
+/* EXMC_NPINTENx,x=1..3 */
+#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
+#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
+#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
+#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
+#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
+#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
+#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
+
+/* EXMC_NPCTCFGx,x=1..3 */
+#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
+#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
+#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
+#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
+
+/* EXMC_NPATCFGx,x=1..3 */
+#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
+#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
+#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
+#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
+
+/* EXMC_PIOTCFG3 */
+#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
+#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
+#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
+#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
+
+/* EXMC_NECCx,x=1,2 */
+#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
+
+/* constants definitions */
+/* EXMC NOR/SRAM timing initialize struct */
+typedef struct
+{
+ uint32_t asyn_access_mode; /*!< asynchronous access mode */
+ uint32_t syn_data_latency; /*!< configure the data latency */
+ uint32_t syn_clk_division; /*!< configure the clock divide ratio */
+ uint32_t bus_latency; /*!< configure the bus latency */
+ uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
+ uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
+ uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
+}exmc_norsram_timing_parameter_struct;
+
+/* EXMC NOR/SRAM initialize struct */
+typedef struct
+{
+ uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
+ uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
+ uint32_t extended_mode; /*!< enable or disable the extended mode */
+ uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
+ uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
+ uint32_t memory_write; /*!< enable or disable the write operation */
+ uint32_t nwait_config; /*!< NWAIT signal configuration */
+ uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
+ uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
+ uint32_t burst_mode; /*!< enable or disable the burst mode */
+ uint32_t databus_width; /*!< specifies the databus width of external memory */
+ uint32_t memory_type; /*!< specifies the type of external memory */
+ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
+ exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing
+ parameters for read if the extended mode is used */
+ exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */
+}exmc_norsram_parameter_struct;
+
+/* EXMC NAND/PC card timing initialize struct */
+typedef struct
+{
+ uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
+ uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
+ uint32_t waittime; /*!< configure the minimum wait time */
+ uint32_t setuptime; /*!< configure the address setup time */
+}exmc_nand_pccard_timing_parameter_struct;
+
+/* EXMC NAND initialize struct */
+typedef struct
+{
+ uint32_t nand_bank; /*!< select the bank of NAND */
+ uint32_t ecc_size; /*!< the page size for the ECC calculation */
+ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
+ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
+ uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
+ uint32_t databus_width; /*!< the NAND flash databus width */
+ uint32_t wait_feature; /*!< enables or disables the wait feature */
+ exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
+ exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
+}exmc_nand_parameter_struct;
+
+/* EXMC PC card initialize struct */
+typedef struct
+{
+ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
+ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
+ uint32_t wait_feature; /*!< enables or disables the Wait feature */
+ exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
+ exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
+ exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */
+}exmc_pccard_parameter_struct;;
+
+/* EXMC register address */
+#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
+#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */
+
+#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */
+#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */
+#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */
+#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */
+#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */
+
+/* NOR bank memory data bus width */
+#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
+#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
+
+/* NOR bank memory type */
+#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
+#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
+#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
+
+/* asynchronous access mode */
+#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
+#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
+#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
+#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
+#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
+
+/* data latency for NOR flash */
+#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
+#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */
+#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */
+#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */
+#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */
+#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */
+#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */
+#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */
+#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */
+#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */
+#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */
+#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */
+#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */
+#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */
+#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */
+#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */
+#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */
+
+/* synchronous clock divide ratio */
+#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
+#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
+#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< frequency EXMC_CLK = HCLK/2 */
+#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< frequency EXMC_CLK = HCLK/3 */
+#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< frequency EXMC_CLK = HCLK/4 */
+#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< frequency EXMC_CLK = HCLK/5 */
+#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< frequency EXMC_CLK = HCLK/6 */
+#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< frequency EXMC_CLK = HCLK/7 */
+#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< frequency EXMC_CLK = HCLK/8 */
+#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< frequency EXMC_CLK = HCLK/9 */
+#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< frequency EXMC_CLK = HCLK/10 */
+#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< frequency EXMC_CLK = HCLK/11 */
+#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< frequency EXMC_CLK = HCLK/12 */
+#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< frequency EXMC_CLK = HCLK/13 */
+#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< frequency EXMC_CLK = HCLK/14 */
+#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< frequency EXMC_CLK = HCLK/15 */
+#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< frequency EXMC_CLK = HCLK/16 */
+
+/* ECC size */
+#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
+#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */
+#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */
+#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */
+#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */
+#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */
+#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */
+
+/* ALE to RE delay */
+#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
+#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
+#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
+#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
+#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
+#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
+#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
+#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
+#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
+#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
+#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
+#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
+#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
+#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
+#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
+#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
+#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
+
+/* CLE to RE delay */
+#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
+#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
+#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
+#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
+#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
+#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
+#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
+#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
+#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
+#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
+#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
+#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
+#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
+#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
+#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
+#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
+#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
+
+/* NAND bank memory data bus width */
+#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */
+#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */
+
+/* EXMC NOR/SRAM bank region definition */
+#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
+#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
+#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
+#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
+
+/* EXMC NOR/SRAM write mode */
+#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
+#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */
+
+/* EXMC NWAIT signal configuration */
+#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
+#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */
+
+/* EXMC NWAIT signal polarity configuration */
+#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
+#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
+
+/* EXMC NAND/PC card bank definition */
+#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */
+#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */
+#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */
+
+/* EXMC flag bits */
+#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
+#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
+#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
+#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
+
+/* EXMC interrupt flag bits */
+#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */
+#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */
+#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */
+
+/* function declarations */
+/* deinitialize EXMC NOR/SRAM region */
+void exmc_norsram_deinit(uint32_t norsram_region);
+/* exmc_norsram_parameter_struct parameter initialize */
+void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
+/* initialize EXMC NOR/SRAM region */
+void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
+/* EXMC NOR/SRAM bank enable */
+void exmc_norsram_enable(uint32_t norsram_region);
+/* EXMC NOR/SRAM bank disable */
+void exmc_norsram_disable(uint32_t norsram_region);
+
+/* deinitialize EXMC NAND bank */
+void exmc_nand_deinit(uint32_t nand_bank);
+/* initialize EXMC NAND bank */
+void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
+/* exmc_nand_init_struct parameter initialize */
+void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
+/* EXMC NAND bank enable */
+void exmc_nand_enable(uint32_t nand_bank);
+/* EXMC NAND bank disable */
+void exmc_nand_disable(uint32_t nand_bank);
+/* enable or disable the EXMC NAND ECC function */
+void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue);
+/* get the EXMC ECC value */
+uint32_t exmc_ecc_get(uint32_t nand_bank);
+
+/* deinitialize EXMC PC card bank */
+void exmc_pccard_deinit(void);
+/* initialize EXMC PC card bank */
+void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
+/* exmc_pccard_parameter_struct parameter initialize */
+void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
+/* EXMC PC card bank enable */
+void exmc_pccard_enable(void);
+/* EXMC PC card bank disable */
+void exmc_pccard_disable(void);
+
+/* enable EXMC interrupt */
+void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source);
+/* disable EXMC interrupt */
+void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source);
+/* check EXMC flag is set or not */
+FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag);
+/* clear EXMC flag */
+void exmc_flag_clear(uint32_t bank, uint32_t flag);
+/* check EXMC flag is set or not */
+FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source);
+/* clear EXMC flag */
+void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source);
+
+#endif /* GD32F10X_EXMC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h
new file mode 100644
index 0000000..ebb07da
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h
@@ -0,0 +1,252 @@
+/*!
+ \file gd32f10x_exti.h
+ \brief definitions for the EXTI
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_EXTI_H
+#define GD32F10X_EXTI_H
+
+#include "gd32f10x.h"
+
+/* EXTI definitions */
+#define EXTI EXTI_BASE
+
+/* registers definitions */
+#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */
+#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */
+#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */
+#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */
+#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */
+#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */
+
+/* bits definitions */
+/* EXTI_INTEN */
+#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
+#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
+#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
+#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
+#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
+#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
+#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
+#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
+#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
+#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
+#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
+#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
+#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
+#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
+#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
+#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
+#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
+#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
+#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
+#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
+
+/* EXTI_EVEN */
+#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
+#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
+#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
+#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
+#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
+#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
+#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
+#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
+#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
+#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
+#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
+#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
+#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
+#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
+#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
+#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
+#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
+#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
+#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
+#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
+
+/* EXTI_RTEN */
+#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
+#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
+#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
+#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
+#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
+#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
+#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
+#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
+#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
+#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
+#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
+#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
+#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
+#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
+#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
+#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
+#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
+#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
+#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
+#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
+
+/* EXTI_FTEN */
+#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
+#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
+#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
+#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
+#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
+#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
+#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
+#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
+#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
+#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
+#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
+#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
+#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
+#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
+#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
+#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
+#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
+#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
+#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
+#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
+
+/* EXTI_SWIEV */
+#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
+#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
+#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
+#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
+#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
+#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
+#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
+#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
+#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
+#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
+#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
+#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
+#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
+#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
+#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
+#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
+#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
+#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
+#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
+#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
+
+/* EXTI_PD */
+#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
+#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
+#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
+#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
+#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
+#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
+#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
+#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
+#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
+#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
+#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
+#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
+#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
+#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
+#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
+#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
+#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
+#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
+#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */
+#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
+
+/* constants definitions */
+/* EXTI line number */
+typedef enum {
+ EXTI_0 = BIT(0), /*!< EXTI line 0 */
+ EXTI_1 = BIT(1), /*!< EXTI line 1 */
+ EXTI_2 = BIT(2), /*!< EXTI line 2 */
+ EXTI_3 = BIT(3), /*!< EXTI line 3 */
+ EXTI_4 = BIT(4), /*!< EXTI line 4 */
+ EXTI_5 = BIT(5), /*!< EXTI line 5 */
+ EXTI_6 = BIT(6), /*!< EXTI line 6 */
+ EXTI_7 = BIT(7), /*!< EXTI line 7 */
+ EXTI_8 = BIT(8), /*!< EXTI line 8 */
+ EXTI_9 = BIT(9), /*!< EXTI line 9 */
+ EXTI_10 = BIT(10), /*!< EXTI line 10 */
+ EXTI_11 = BIT(11), /*!< EXTI line 11 */
+ EXTI_12 = BIT(12), /*!< EXTI line 12 */
+ EXTI_13 = BIT(13), /*!< EXTI line 13 */
+ EXTI_14 = BIT(14), /*!< EXTI line 14 */
+ EXTI_15 = BIT(15), /*!< EXTI line 15 */
+ EXTI_16 = BIT(16), /*!< EXTI line 16 */
+ EXTI_17 = BIT(17), /*!< EXTI line 17 */
+ EXTI_18 = BIT(18), /*!< EXTI line 18 */
+ EXTI_19 = BIT(19) /*!< EXTI line 19 */
+} exti_line_enum;
+
+/* external interrupt and event */
+typedef enum {
+ EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
+ EXTI_EVENT /*!< EXTI event mode */
+} exti_mode_enum;
+
+/* interrupt and event trigger mode */
+typedef enum {
+ EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
+ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
+ EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
+ EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
+} exti_trig_type_enum;
+
+/* function declarations */
+/* initialization, EXTI lines configuration functions */
+/* deinitialize the EXTI */
+void exti_deinit(void);
+/* initialize the EXTI line x */
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
+/* enable the interrupts from EXTI line x */
+void exti_interrupt_enable(exti_line_enum linex);
+/* disable the interrupts from EXTI line x */
+void exti_interrupt_disable(exti_line_enum linex);
+/* enable the events from EXTI line x */
+void exti_event_enable(exti_line_enum linex);
+/* disable the events from EXTI line x */
+void exti_event_disable(exti_line_enum linex);
+/* enable the software interrupt event from EXTI line x */
+void exti_software_interrupt_enable(exti_line_enum linex);
+/* disable the software interrupt event from EXTI line x */
+void exti_software_interrupt_disable(exti_line_enum linex);
+
+/* interrupt & flag functions */
+/* get EXTI line x interrupt pending flag */
+FlagStatus exti_flag_get(exti_line_enum linex);
+/* clear EXTI line x interrupt pending flag */
+void exti_flag_clear(exti_line_enum linex);
+/* get EXTI line x interrupt pending flag */
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
+/* clear EXTI line x interrupt pending flag */
+void exti_interrupt_flag_clear(exti_line_enum linex);
+
+#endif /* GD32F10X_EXTI_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h
new file mode 100644
index 0000000..035d6ff
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h
@@ -0,0 +1,366 @@
+/*!
+ \file gd32f10x_fmc.h
+ \brief definitions for the FMC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_FMC_H
+#define GD32F10X_FMC_H
+
+#include "gd32f10x.h"
+
+/* FMC and option byte definition */
+#define FMC FMC_BASE /*!< FMC register base address */
+#define OB OB_BASE /*!< option bytes base address */
+
+/* registers definitions */
+#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
+#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
+#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
+#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
+#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
+#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
+#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
+#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
+#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */
+#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */
+#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */
+#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */
+#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
+#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
+
+#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
+#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
+#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
+#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
+#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */
+#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */
+
+/* bits definitions */
+/* FMC_WS */
+#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
+
+/* FMC_KEY0 */
+#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
+
+/* FMC_OBKEY */
+#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
+
+/* FMC_STAT0 */
+#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
+#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
+#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
+#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
+
+/* FMC_CTL0 */
+#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
+#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
+#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
+#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
+#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
+#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
+#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
+#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
+#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
+#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
+
+/* FMC_ADDR0 */
+#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */
+
+/* FMC_OBSTAT */
+#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
+#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
+#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
+#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */
+
+/* FMC_WP */
+#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
+
+/* FMC_KEY1 */
+#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */
+
+/* FMC_STAT1 */
+#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */
+#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */
+#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */
+#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */
+
+/* FMC_CTL1 */
+#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */
+#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */
+#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */
+#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */
+#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */
+#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */
+#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
+
+/* FMC_ADDR1 */
+#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */
+
+/* FMC_WSEN */
+#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
+
+/* FMC_PID */
+#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
+
+/* constants definitions */
+/* define the FMC bit position and its register index offset */
+#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
+#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
+#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
+#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
+#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
+#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
+#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
+
+/* configuration register */
+#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
+#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
+#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */
+#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */
+#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
+
+/* fmc state */
+typedef enum
+{
+ FMC_READY, /*!< the operation has been completed */
+ FMC_BUSY, /*!< the operation is in progress */
+ FMC_PGERR, /*!< program error */
+ FMC_WPERR, /*!< erase/program protection error */
+ FMC_TOERR, /*!< timeout error */
+}fmc_state_enum;
+
+/* FMC interrupt enable */
+typedef enum
+{
+ FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
+ FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
+ FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */
+ FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */
+}fmc_int_enum;
+
+/* FMC flags */
+typedef enum
+{
+ FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */
+ FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */
+ FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */
+ FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */
+ FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
+ FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */
+ FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */
+ FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */
+ FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */
+}fmc_flag_enum;
+
+/* FMC interrupt flags */
+typedef enum
+{
+ FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */
+ FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */
+ FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */
+ FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */
+ FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */
+ FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */
+}fmc_interrupt_flag_enum;
+
+/* unlock key */
+#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
+#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
+
+/* FMC wait state counter */
+#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
+#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
+#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
+#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */
+
+/* option bytes software/hardware free watch dog timer */
+#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
+#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
+
+/* option bytes reset or not entering deep sleep mode */
+#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
+#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
+
+/* option bytes reset or not entering standby mode */
+#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */
+#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
+
+/* option bytes boot bank value */
+#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */
+#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */
+
+#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */
+
+/* read protect configure */
+#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
+#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */
+
+/* OB_SPC */
+#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */
+#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */
+
+/* OB_USER */
+#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */
+#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */
+
+/* OB_WP0 */
+#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */
+
+/* OB_WP1 */
+#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */
+
+/* OB_WP2 */
+#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */
+
+/* OB_WP3 */
+#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */
+
+/* option bytes write protection */
+#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
+#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
+#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
+#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
+#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
+#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
+#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
+#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
+#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
+#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
+#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
+#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
+#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
+#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
+#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
+#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
+#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
+#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
+#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
+#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
+#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
+#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
+#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
+#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
+#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
+#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
+#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
+#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
+#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
+#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
+#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
+#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */
+#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
+
+/* FMC timeout */
+#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */
+
+/* FMC BANK address */
+#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */
+#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */
+#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */
+
+/* function declarations */
+/* FMC main memory programming functions */
+/* set the FMC wait state counter */
+void fmc_wscnt_set(uint32_t wscnt);
+/* unlock the main FMC operation */
+void fmc_unlock(void);
+/* unlock the FMC bank0 operation */
+void fmc_bank0_unlock(void);
+/* unlock the FMC bank1 operation */
+void fmc_bank1_unlock(void);
+/* lock the main FMC operation */
+void fmc_lock(void);
+/* lock the bank0 FMC operation */
+void fmc_bank0_lock(void);
+/* lock the bank1 FMC operation */
+void fmc_bank1_lock(void);
+/* FMC erase page */
+fmc_state_enum fmc_page_erase(uint32_t page_address);
+/* FMC erase whole chip */
+fmc_state_enum fmc_mass_erase(void);
+/* FMC erase whole bank0 */
+fmc_state_enum fmc_bank0_erase(void);
+/* FMC erase whole bank1 */
+fmc_state_enum fmc_bank1_erase(void);
+/* FMC program a word at the corresponding address */
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
+/* FMC program a half word at the corresponding address */
+fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
+
+/* FMC option bytes programming functions */
+/* unlock the option byte operation */
+void ob_unlock(void);
+/* lock the option byte operation */
+void ob_lock(void);
+/* erase the option byte */
+fmc_state_enum ob_erase(void);
+/* enable write protect */
+fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
+/* configure the option byte security protection */
+fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
+/* write the FMC option byte */
+fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
+/* program option bytes data */
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
+/* get the FMC option byte user */
+uint8_t ob_user_get(void);
+/* get OB_DATA in register FMC_OBSTAT */
+uint16_t ob_data_get(void);
+/* get the FMC option byte write protection */
+uint32_t ob_write_protection_get(void);
+/* get option byte security protection code value */
+FlagStatus ob_spc_get(void);
+
+/* FMC interrupts and flags management functions */
+/* enable FMC interrupt */
+void fmc_interrupt_enable(uint32_t interrupt);
+/* disable FMC interrupt */
+void fmc_interrupt_disable(uint32_t interrupt);
+/* check flag is set or not */
+FlagStatus fmc_flag_get(uint32_t flag);
+/* clear the FMC flag */
+void fmc_flag_clear(uint32_t flag);
+/* get FMC interrupt flag state */
+FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
+/* clear FMC interrupt flag state */
+void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
+/* return the FMC bank0 state */
+fmc_state_enum fmc_bank0_state_get(void);
+/* return the FMC bank1 state */
+fmc_state_enum fmc_bank1_state_get(void);
+/* check FMC bank0 ready or not */
+fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
+/* check FMC bank1 ready or not */
+fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
+
+#endif /* GD32F10X_FMC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h
new file mode 100644
index 0000000..8b48cad
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h
@@ -0,0 +1,111 @@
+/*!
+ \file gd32f10x_fwdgt.h
+ \brief definitions for the FWDGT
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_FWDGT_H
+#define GD32F10X_FWDGT_H
+
+#include "gd32f10x.h"
+
+/* FWDGT definitions */
+#define FWDGT FWDGT_BASE /*!< FWDGT base address */
+
+/* registers definitions */
+#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
+#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
+#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
+#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
+
+/* bits definitions */
+/* FWDGT_CTL */
+#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
+
+/* FWDGT_PSC */
+#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
+
+/* FWDGT_RLD */
+#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
+
+/* FWDGT_STAT */
+#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
+
+/* constants definitions */
+/* psc register value */
+#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
+
+/* control value */
+#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
+
+/* FWDGT timeout value */
+#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
+
+/* FWDGT flag definitions */
+#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
+#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
+
+/* write value to FWDGT_RLD_RLD bit field */
+#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/* function declarations */
+/* enable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_enable(void);
+/* disable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_disable(void);
+/* start the free watchdog timer counter */
+void fwdgt_enable(void);
+
+/* configure the free watchdog timer counter prescaler value */
+ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
+/* configure the free watchdog timer counter reload value */
+ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
+/* reload the counter of FWDGT */
+void fwdgt_counter_reload(void);
+/* configure counter reload value, and prescaler divider value */
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
+
+/* get flag state of FWDGT */
+FlagStatus fwdgt_flag_get(uint16_t flag);
+
+#endif /* GD32F10X_FWDGT_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h
new file mode 100644
index 0000000..76e19c4
Binary files /dev/null and b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h differ
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h
new file mode 100644
index 0000000..0de0d0d
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h
@@ -0,0 +1,345 @@
+/*!
+ \file gd32f10x_i2c.h
+ \brief definitions for the I2C
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_I2C_H
+#define GD32F10X_I2C_H
+
+#include "gd32f10x.h"
+
+/* I2Cx(x=0,1) definitions */
+#define I2C0 I2C_BASE /*!< I2C0 base address */
+#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
+
+/* registers definitions */
+#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
+#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
+#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/
+#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */
+#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
+#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
+#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
+#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
+#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
+
+/* bits definitions */
+/* I2Cx_CTL0 */
+#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
+#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
+#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
+#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
+#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
+#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
+#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
+#define I2C_CTL0_START BIT(8) /*!< start generation */
+#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
+#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
+#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
+#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
+#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
+#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
+
+/* I2Cx_CTL1 */
+#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
+#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
+#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
+#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
+#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
+#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
+
+/* I2Cx_SADDR0 */
+#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
+#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
+
+/* I2Cx_SADDR1 */
+#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
+#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
+
+/* I2Cx_DATA */
+#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
+
+/* I2Cx_STAT0 */
+#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
+#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
+#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
+#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
+#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
+#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
+#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
+#define I2C_STAT0_BERR BIT(8) /*!< bus error */
+#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
+#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
+#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
+#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
+#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
+#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
+
+/* I2Cx_STAT1 */
+#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
+#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
+#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
+#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
+#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
+#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
+#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
+#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
+
+/* I2Cx_CKCFG */
+#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
+#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
+#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
+
+/* I2Cx_RT */
+#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
+
+/* constants definitions */
+/* define the I2C bit position and its register index offset */
+#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
+#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
+#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+ | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
+#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
+
+/* register offset */
+#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
+#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
+#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
+
+/* I2C flags */
+typedef enum
+{
+ /* flags in STAT0 register */
+ I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
+ I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
+ I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
+ I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
+ I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
+ I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
+ I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
+ I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
+ I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
+ I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
+ I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
+ I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
+ I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
+ I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
+ /* flags in STAT1 register */
+ I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
+ I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
+ I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
+ I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
+ I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
+ I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
+ I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
+}i2c_flag_enum;
+
+/* I2C interrupt flags */
+typedef enum
+{
+ /* interrupt flags in CTL1 register */
+ I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
+ I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
+ I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
+ I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
+ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
+ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
+ I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
+ I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
+ I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
+ I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
+ I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
+ I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
+ I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
+ I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
+}i2c_interrupt_flag_enum;
+
+/* I2C interrupt enable or disable */
+typedef enum
+{
+ /* interrupt in CTL1 register */
+ I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
+ I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
+ I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
+}i2c_interrupt_enum;
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
+#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
+#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
+
+/* I2C transfer direction */
+#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
+#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
+
+/* whether or not to send an ACK */
+#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
+#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
+
+/* I2C POAP position*/
+#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
+#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
+
+/* I2C dual-address mode switch */
+#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
+#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
+
+/* whether or not to stretch SCL low */
+#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
+#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */
+
+/* whether or not to response to a general call */
+#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
+#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
+
+/* software reset I2C */
+#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
+#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
+
+/* I2C DMA mode configure */
+/* DMA mode switch */
+#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
+#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
+
+/* flag indicating DMA last transfer */
+#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
+#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
+
+/* I2C PEC configure */
+/* PEC enable */
+#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
+#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
+
+/* PEC transfer */
+#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
+#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
+
+/* I2C SMBus configure */
+/* issue or not alert through SMBA pin */
+#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
+#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
+
+/* ARP protocol in SMBus switch */
+#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */
+#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */
+
+/* transmit I2C data */
+#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* receive I2C data */
+#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
+
+/* I2C duty cycle in fast mode */
+#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */
+
+/* address mode for the I2C slave */
+#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
+#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
+
+/* function declarations */
+/* initialization functions */
+/* reset I2C */
+void i2c_deinit(uint32_t i2c_periph);
+/* configure I2C clock */
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
+/* configure I2C address */
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
+
+/* application function declarations */
+/* select SMBus type */
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
+/* whether or not to send an ACK */
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
+/* configure I2C POAP position */
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
+/* master sends slave address */
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
+/* enable dual-address mode */
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
+/* disable dual-address mode */
+void i2c_dualaddr_disable(uint32_t i2c_periph);
+/* enable I2C */
+void i2c_enable(uint32_t i2c_periph);
+/* disable I2C */
+void i2c_disable(uint32_t i2c_periph);
+/* generate a START condition on I2C bus */
+void i2c_start_on_bus(uint32_t i2c_periph);
+/* generate a STOP condition on I2C bus */
+void i2c_stop_on_bus(uint32_t i2c_periph);
+/* I2C transmit data function */
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
+/* I2C receive data function */
+uint8_t i2c_data_receive(uint32_t i2c_periph);
+/* configure I2C DMA mode */
+void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
+/* configure whether next DMA EOT is DMA last transfer or not */
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
+/* whether to stretch SCL low when data is not ready in slave mode */
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
+/* whether or not to response to a general call */
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
+/* configure software reset of I2C */
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
+/* configure I2C PEC calculation */
+void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
+/* configure whether to transfer PEC value */
+void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
+/* get packet error checking value */
+uint8_t i2c_pec_value_get(uint32_t i2c_periph);
+/* configure I2C alert through SMBA pin */
+void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
+/* configure I2C ARP protocol in SMBus */
+void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
+
+/* interrupt & flag functions */
+/* get I2C flag status */
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
+/* clear I2C flag status */
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
+/* enable I2C interrupt */
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* disable I2C interrupt */
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* get I2C interrupt flag status */
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
+/* clear I2C interrupt flag status */
+void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
+
+#endif /* GD32E10X_I2C_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h
new file mode 100644
index 0000000..3d63018
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h
@@ -0,0 +1,91 @@
+/*!
+ \file gd32f10x_misc.h
+ \brief definitions for the MISC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_MISC_H
+#define GD32F10X_MISC_H
+
+#include "gd32f10x.h"
+
+/* constants definitions */
+/* set the RAM and FLASH base address */
+#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */
+#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
+
+/* set the NVIC vector table offset mask */
+#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U)
+
+/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
+#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U)
+
+/* priority group - define the pre-emption priority and the subpriority */
+#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700U) /*!< 0 bits for pre-emption priority, 4 bits for subpriority */
+#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600U) /*!< 1 bits for pre-emption priority, 3 bits for subpriority */
+#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500U) /*!< 2 bits for pre-emption priority, 2 bits for subpriority */
+#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400U) /*!< 3 bits for pre-emption priority, 1 bits for subpriority */
+#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300U) /*!< 4 bits for pre-emption priority, 0 bits for subpriority */
+
+/* choose the method to enter or exit the low power mode */
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the system whether enter low power mode by exiting from ISR */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the system enter the DEEPSLEEP mode or SLEEP mode */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the low power mode */
+
+#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
+#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
+#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
+
+/* choose the systick clock source */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
+
+/* function declarations */
+/* set the priority group */
+void nvic_priority_group_set(uint32_t nvic_prigroup);
+
+/* enable NVIC interrupt request */
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
+/* disable NVIC interrupt request */
+void nvic_irq_disable(uint8_t nvic_irq);
+
+/* set the NVIC vector table base address */
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
+
+/* set the state of the low power mode */
+void system_lowpower_set(uint8_t lowpower_mode);
+/* reset the state of the low power mode */
+void system_lowpower_reset(uint8_t lowpower_mode);
+
+/* set the systick clock source */
+void systick_clksource_set(uint32_t systick_clksource);
+
+#endif /* GD32F10X_MISC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h
new file mode 100644
index 0000000..65a1d3f
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h
@@ -0,0 +1,126 @@
+/*!
+ \file gd32f10x_pmu.h
+ \brief definitions for the PMU
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_PMU_H
+#define GD32F10X_PMU_H
+
+#include "gd32f10x.h"
+
+/* PMU definitions */
+#define PMU PMU_BASE /*!< PMU base address */
+
+/* registers definitions */
+#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */
+#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
+
+/* bits definitions */
+/* PMU_CTL */
+#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
+#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
+#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
+#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
+#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
+#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
+#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
+
+/* PMU_CS */
+#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
+#define PMU_CS_STBF BIT(1) /*!< standby flag */
+#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
+#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
+
+/* constants definitions */
+/* PMU ldo definitions */
+#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
+#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
+
+/* PMU low voltage detector threshold definitions */
+#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
+#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
+#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
+#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
+#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
+#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
+#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
+#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
+#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
+
+/* PMU flag definitions */
+#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
+#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
+#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
+
+/* PMU flag reset definitions */
+#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
+#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
+
+/* PMU command constants definitions */
+#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
+#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
+
+/* function declarations */
+/* reset PMU registers */
+void pmu_deinit(void);
+
+/* LVD functions */
+/* select low voltage detector threshold */
+void pmu_lvd_select(uint32_t lvdt_n);
+/* disable PMU lvd */
+void pmu_lvd_disable(void);
+
+/* set PMU mode */
+/* PMU work in sleep mode */
+void pmu_to_sleepmode(uint8_t sleepmodecmd);
+/* PMU work in deepsleep mode */
+void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
+/* PMU work in standby mode */
+void pmu_to_standbymode(void);
+/* enable PMU wakeup pin */
+void pmu_wakeup_pin_enable(void);
+/* disable PMU wakeup pin */
+void pmu_wakeup_pin_disable(void);
+
+/* backup related functions */
+/* enable write access to the registers in backup domain */
+void pmu_backup_write_enable(void);
+/* disable write access to the registers in backup domain */
+void pmu_backup_write_disable(void);
+
+/* flag functions */
+/* get flag state */
+FlagStatus pmu_flag_get(uint32_t flag);
+/* clear flag bit */
+void pmu_flag_clear(uint32_t flag);
+
+#endif /* GD32F10X_PMU_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h
new file mode 100644
index 0000000..b9aa80f
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h
@@ -0,0 +1,919 @@
+/*!
+ \file gd32f10x_rcu.h
+ \brief definitions for the RCU
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_RCU_H
+#define GD32F10X_RCU_H
+
+#include "gd32f10x.h"
+
+/* RCU definitions */
+#define RCU RCU_BASE
+
+/* registers definitions */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
+#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */
+#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
+#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
+#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
+#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */
+#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
+#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
+#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
+#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */
+#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
+#elif defined(GD32F10X_CL)
+#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */
+#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */
+#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */
+#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
+#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
+#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */
+#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
+#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
+#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
+#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */
+#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */
+#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */
+#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/* bits definitions */
+/* RCU_CTL */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
+#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
+#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
+#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
+#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */
+#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
+#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
+#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
+#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
+#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
+#elif defined(GD32F10X_CL)
+#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
+#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
+#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
+#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
+#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */
+#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
+#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
+#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
+#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */
+#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
+#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */
+#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */
+#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */
+#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/* RCU_CFG0 */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
+#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
+#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
+#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
+#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
+#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */
+#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
+#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */
+#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */
+#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */
+#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */
+#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */
+#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */
+#elif defined(GD32F10X_CL)
+#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
+#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
+#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
+#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
+#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
+#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */
+#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
+#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */
+#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */
+#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */
+#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */
+#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */
+#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/* RCU_INT */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
+#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
+#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
+#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
+#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
+#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
+#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
+#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
+#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
+#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
+#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
+#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */
+#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */
+#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */
+#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */
+#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
+#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
+#elif defined(GD32F10X_CL)
+#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
+#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
+#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
+#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
+#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
+#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */
+#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */
+#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
+#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
+#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
+#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
+#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
+#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
+#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */
+#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */
+#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */
+#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */
+#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */
+#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */
+#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
+#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */
+#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */
+#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/* RCU_APB2RST */
+#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */
+#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */
+#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */
+#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */
+#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */
+#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */
+#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */
+#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */
+#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */
+#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */
+#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */
+#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */
+#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */
+#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */
+#ifndef GD32F10X_CL
+#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */
+#endif /* GD32F10X_CL */
+#ifdef GD32F10X_XD
+#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */
+#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */
+#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */
+#endif /* GD32F10X_XD */
+
+/* RCU_APB1RST */
+#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */
+#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */
+#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */
+#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */
+#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */
+#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */
+#ifdef GD32F10X_XD
+#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */
+#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */
+#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */
+#endif /* GD32F10X_XD */
+#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */
+#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */
+#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */
+#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */
+#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */
+#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */
+#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */
+#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */
+#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */
+#ifdef GD32F10X_CL
+#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */
+#endif /* GD32F10X_CL */
+#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */
+#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */
+#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */
+
+/* RCU_AHBEN */
+#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */
+#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */
+#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */
+#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */
+#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */
+#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */
+#elif defined(GD32F10X_CL)
+#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */
+#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */
+#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */
+#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/* RCU_APB2EN */
+#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */
+#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */
+#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */
+#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */
+#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */
+#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */
+#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */
+#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */
+#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */
+#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */
+#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */
+#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */
+#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */
+#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */
+#ifndef GD32F10X_CL
+#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */
+#endif /* GD32F10X_CL */
+#ifdef GD32F10X_XD
+#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */
+#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */
+#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */
+#endif /* GD32F10X_XD */
+
+/* RCU_APB1EN */
+#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */
+#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */
+#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */
+#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */
+#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */
+#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */
+#ifdef GD32F10X_XD
+#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */
+#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */
+#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */
+#endif /* GD32F10X_XD */
+#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */
+#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */
+#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */
+#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */
+#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */
+#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */
+#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */
+#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */
+#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */
+#ifdef GD32F10X_CL
+#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */
+#endif /* GD32F10X_CL */
+#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */
+#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */
+#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */
+
+/* RCU_BDCTL */
+#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */
+#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */
+#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */
+#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */
+#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */
+#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */
+
+/* RCU_RSTSCK */
+#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */
+#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */
+#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */
+#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */
+#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */
+#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */
+#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */
+#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */
+#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */
+
+#ifdef GD32F10X_CL
+/* RCU_AHBRST */
+#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */
+#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */
+#endif /* GD32F10X_CL */
+
+#if defined(GD32F10X_CL)
+/* RCU_CFG1 */
+#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */
+#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */
+#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */
+#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */
+#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */
+#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */
+#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */
+#endif /* GD32F10X_CL */
+
+/* RCU_DSV */
+#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */
+
+/* constants definitions */
+/* define the peripheral clock enable bit position and its register index offset */
+#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
+#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
+
+/* register offset */
+/* peripherals enable */
+#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */
+#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */
+#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */
+
+/* peripherals reset */
+#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */
+#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */
+#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */
+#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */
+
+/* clock control */
+#define CTL_REG_OFFSET 0x00U /*!< control register offset */
+#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */
+
+/* clock stabilization and stuck interrupt */
+#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */
+
+/* configuration register */
+#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */
+#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */
+
+/* peripheral clock enable */
+typedef enum
+{
+ /* AHB peripherals */
+ RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
+ RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
+ RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */
+ RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */
+#elif defined(GD32F10X_CL)
+ RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */
+ RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */
+ RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */
+ RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+ /* APB1 peripherals */
+ RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */
+ RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */
+ RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */
+ RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */
+ RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */
+ RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */
+#if defined(GD32F10X_XD)
+ RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */
+ RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */
+ RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */
+#endif /* GD32F10X_XD */
+ RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */
+ RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */
+ RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */
+ RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */
+ RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */
+ RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */
+ RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */
+ RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */
+ RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+ RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */
+#ifdef GD32F10X_CL
+ RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */
+#endif /* GD32F10X_CL */
+ RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */
+ RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */
+ RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */
+ RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */
+
+ /* APB2 peripherals */
+ RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */
+ RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */
+ RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */
+ RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */
+ RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */
+ RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */
+ RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */
+ RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */
+ RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */
+ RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */
+ RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */
+ RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */
+ RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */
+ RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */
+#ifndef GD32F10X_CL
+ RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */
+#endif /* GD32F10X_CL */
+#ifdef GD32F10X_XD
+ RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */
+ RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */
+ RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */
+#endif /* GD32F10X_XD */
+}rcu_periph_enum;
+
+/* peripheral clock enable when sleep mode*/
+typedef enum
+{
+ /* AHB peripherals */
+ RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
+ RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
+}rcu_periph_sleep_enum;
+
+/* peripherals reset */
+typedef enum
+{
+ /* AHB peripherals */
+#ifdef GD32F10X_CL
+ RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
+ RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */
+#endif /* GD32F10X_CL */
+
+ /* APB1 peripherals */
+ RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */
+ RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */
+ RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */
+ RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */
+ RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */
+ RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */
+#ifdef GD32F10X_XD
+ RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */
+ RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */
+ RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */
+#endif /* GD32F10X_XD */
+ RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */
+ RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */
+ RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */
+ RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */
+ RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */
+ RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */
+ RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */
+ RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */
+ RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+ RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */
+#ifdef GD32F10X_CL
+ RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */
+#endif /* GD32F10X_CL */
+ RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */
+ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */
+ RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */
+
+ /* APB2 peripherals */
+ RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */
+ RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */
+ RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */
+ RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */
+ RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */
+ RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */
+ RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */
+ RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */
+ RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */
+ RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */
+ RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */
+ RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */
+ RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */
+ RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */
+#ifndef GD32F10X_CL
+ RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */
+#endif /* GD32F10X_CL */
+#ifdef GD32F10X_XD
+ RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */
+ RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */
+ RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */
+#endif /* GD32F10X_XD */
+}rcu_periph_reset_enum;
+
+/* clock stabilization and peripheral reset flags */
+typedef enum
+{
+ /* clock stabilization flags */
+ RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
+ RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
+ RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */
+#ifdef GD32F10X_CL
+ RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */
+ RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */
+#endif /* GD32F10X_CL */
+ RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */
+ RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */
+ /* reset source flags */
+ RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */
+ RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */
+ RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */
+ RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */
+ RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */
+ RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */
+}rcu_flag_enum;
+
+/* clock stabilization and ckm interrupt flags */
+typedef enum
+{
+ RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
+ RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
+ RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
+ RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */
+ RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */
+#ifdef GD32F10X_CL
+ RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */
+ RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */
+#endif /* GD32F10X_CL */
+ RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */
+}rcu_int_flag_enum;
+
+/* clock stabilization and stuck interrupt flags clear */
+typedef enum
+{
+ RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
+ RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
+ RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
+ RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */
+ RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */
+#ifdef GD32F10X_CL
+ RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */
+ RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */
+#endif /* GD32F10X_CL */
+ RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */
+}rcu_int_flag_clear_enum;
+
+/* clock stabilization interrupt enable or disable */
+typedef enum
+{
+ RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
+ RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
+ RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
+ RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */
+ RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */
+#ifdef GD32F10X_CL
+ RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */
+ RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
+#endif /* GD32F10X_CL */
+}rcu_int_enum;
+
+/* oscillator types */
+typedef enum
+{
+ RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */
+ RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */
+ RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */
+ RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */
+ RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */
+#ifdef GD32F10X_CL
+ RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */
+ RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */
+#endif /* GD32F10X_CL */
+}rcu_osci_type_enum;
+
+/* rcu clock frequency */
+typedef enum
+{
+ CK_SYS = 0, /*!< system clock */
+ CK_AHB, /*!< AHB clock */
+ CK_APB1, /*!< APB1 clock */
+ CK_APB2, /*!< APB2 clock */
+}rcu_clock_freq_enum;
+
+/* RCU_CFG0 register bit define */
+/* system clock source select */
+#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */
+#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */
+#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */
+
+/* system clock source select status */
+#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */
+#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */
+#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */
+
+/* AHB prescaler selection */
+#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */
+#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */
+#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */
+#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */
+#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */
+#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */
+#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */
+#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */
+#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */
+
+/* APB1 prescaler selection */
+#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
+#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */
+#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */
+#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */
+#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */
+#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */
+
+/* APB2 prescaler selection */
+#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
+#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */
+#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */
+#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */
+#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */
+#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */
+
+/* ADC prescaler select */
+#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */
+#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */
+#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */
+#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */
+#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */
+#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */
+
+/* PLL clock source selection */
+#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */
+#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */
+
+/* PLL clock multiplication factor */
+#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */
+
+#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
+#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */
+#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */
+#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */
+#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */
+#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */
+#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */
+#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */
+#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */
+#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */
+#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */
+#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */
+#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */
+#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */
+#elif defined(GD32F10X_CL)
+#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */
+#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */
+#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */
+#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */
+#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */
+#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */
+#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */
+#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */
+#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */
+#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */
+#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */
+#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */
+#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */
+#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */
+#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */
+#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */
+#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */
+
+/* USBD/USBFS prescaler select */
+#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
+#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */
+#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */
+#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */
+#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */
+
+/* CKOUT0 clock source selection */
+#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
+#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */
+#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */
+#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */
+#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */
+#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */
+#ifdef GD32F10X_CL
+#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */
+#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */
+#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */
+#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */
+#endif /* GD32F10X_CL */
+
+/* RTC clock entry selection */
+#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */
+#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */
+#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */
+#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */
+
+/* PREDV0 division factor */
+#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
+#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */
+#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */
+#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */
+#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */
+#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */
+#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */
+#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */
+#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */
+#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */
+#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */
+#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */
+#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */
+#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */
+#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */
+#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */
+#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */
+
+/* PREDV1 division factor */
+#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */
+#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */
+#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */
+#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */
+#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */
+#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */
+#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */
+#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */
+#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */
+#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */
+#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */
+#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */
+#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */
+#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */
+#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */
+#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */
+
+/* PLL1 clock multiplication factor */
+#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
+#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */
+#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */
+#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */
+#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */
+#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */
+#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */
+#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */
+#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */
+#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */
+#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */
+
+/* PLL2 clock multiplication factor */
+#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12))
+#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */
+#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */
+#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */
+#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */
+#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */
+#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */
+#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */
+#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */
+#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */
+#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */
+
+#ifdef GD32F10X_CL
+/* PREDV0 input clock source selection */
+#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */
+#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */
+
+/* I2S1 clock source selection */
+#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */
+#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */
+
+/* I2S2 clock source selection */
+#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */
+#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */
+#endif /* GD32F10X_CL */
+
+/* deep-sleep mode voltage */
+#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */
+
+/* function declarations */
+/* initialization, peripheral clock enable/disable functions */
+/* deinitialize the RCU */
+void rcu_deinit(void);
+/* enable the peripherals clock */
+void rcu_periph_clock_enable(rcu_periph_enum periph);
+/* disable the peripherals clock */
+void rcu_periph_clock_disable(rcu_periph_enum periph);
+/* enable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
+/* disable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
+/* reset the peripherals */
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
+/* disable reset the peripheral */
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
+/* reset the BKP domain */
+void rcu_bkp_reset_enable(void);
+/* disable the BKP domain reset */
+void rcu_bkp_reset_disable(void);
+
+/* clock configuration functions */
+/* configure the system clock source */
+void rcu_system_clock_source_config(uint32_t ck_sys);
+/* get the system clock source */
+uint32_t rcu_system_clock_source_get(void);
+/* configure the AHB prescaler selection */
+void rcu_ahb_clock_config(uint32_t ck_ahb);
+/* configure the APB1 prescaler selection */
+void rcu_apb1_clock_config(uint32_t ck_apb1);
+/* configure the APB2 prescaler selection */
+void rcu_apb2_clock_config(uint32_t ck_apb2);
+/* configure the CK_OUT0 clock source and divider */
+void rcu_ckout0_config(uint32_t ckout0_src);
+/* configure the PLL clock source selection and PLL multiply factor */
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+/* configure the PREDV0 division factor and clock source */
+void rcu_predv0_config(uint32_t predv0_div);
+#elif defined(GD32F10X_CL)
+/* configure the PREDV0 division factor and clock source */
+void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div);
+/* configure the PREDV1 division factor */
+void rcu_predv1_config(uint32_t predv1_div);
+/* configure the PLL1 clock */
+void rcu_pll1_config(uint32_t pll_mul);
+/* configure the PLL2 clock */
+void rcu_pll2_config(uint32_t pll_mul);
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/* peripheral clock configuration functions */
+/* configure the ADC division factor */
+void rcu_adc_clock_config(uint32_t adc_psc);
+/* configure the USBD/USBFS prescaler factor */
+void rcu_usb_clock_config(uint32_t usb_psc);
+/* configure the RTC clock source selection */
+void rcu_rtc_clock_config(uint32_t rtc_clock_source);
+#ifdef GD32F10X_CL
+/* configure the I2S1 clock source selection */
+void rcu_i2s1_clock_config(uint32_t i2s_clock_source);
+/* configure the I2S2 clock source selection */
+void rcu_i2s2_clock_config(uint32_t i2s_clock_source);
+#endif /* GD32F10X_CL */
+
+/* oscillator configuration functions */
+/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
+/* turn on the oscillator */
+void rcu_osci_on(rcu_osci_type_enum osci);
+/* turn off the oscillator */
+void rcu_osci_off(rcu_osci_type_enum osci);
+/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
+/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
+/* enable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_enable(void);
+/* disable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_disable(void);
+
+/* set the IRC8M adjust value */
+void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
+/* set the deep sleep mode voltage */
+void rcu_deepsleep_voltage_set(uint32_t dsvol);
+/* get the system clock, bus and peripheral clock frequency */
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
+
+/* interrupt & flag functions */
+/* get the clock stabilization and periphral reset flags */
+FlagStatus rcu_flag_get(rcu_flag_enum flag);
+/* clear the reset flag */
+void rcu_all_reset_flag_clear(void);
+/* get the clock stabilization interrupt and ckm flags */
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
+/* clear the interrupt flags */
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
+/* enable the stabilization interrupt */
+void rcu_interrupt_enable(rcu_int_enum stab_int);
+/* disable the stabilization interrupt */
+void rcu_interrupt_disable(rcu_int_enum stab_int);
+
+#endif /* GD32F10X_RCU_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h
new file mode 100644
index 0000000..08ce561
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h
@@ -0,0 +1,148 @@
+/*!
+ \file gd32f10x_rtc.h
+ \brief definitions for the RTC
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_RTC_H
+#define GD32F10X_RTC_H
+
+#include "gd32f10x.h"
+
+/* RTC definitions */
+#define RTC RTC_BASE
+
+/* registers definitions */
+#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
+#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
+#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
+#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
+#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
+#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
+#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
+#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
+#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
+#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
+
+/* bits definitions */
+/* RTC_INTEN */
+#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
+#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
+#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
+
+/* RTC_CTL */
+#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
+#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
+#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
+#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
+#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
+#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
+
+/* RTC_PSCH */
+#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
+
+/* RTC_PSCL */
+#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
+
+/* RTC_DIVH */
+#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
+
+/* RTC_DIVL */
+#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
+
+/* RTC_CNTH */
+#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
+
+/* RTC_CNTL */
+#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
+
+/* RTC_ALRMH */
+#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
+
+/* RTC_ALRML */
+#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
+
+/* constants definitions */
+/* RTC interrupt enable or disable definitions */
+#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
+#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
+#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
+
+/* RTC interrupt flag definitions */
+#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
+#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
+#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
+
+/* RTC flag definitions */
+#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
+#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
+#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
+#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
+#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
+
+/* function declarations */
+/* initialization functions */
+/* enter RTC configuration mode */
+void rtc_configuration_mode_enter(void);
+/* exit RTC configuration mode */
+void rtc_configuration_mode_exit(void);
+/* set RTC counter value */
+void rtc_counter_set(uint32_t cnt);
+/* set RTC prescaler value */
+void rtc_prescaler_set(uint32_t psc);
+
+/* operation functions */
+/* wait RTC last write operation finished flag set */
+void rtc_lwoff_wait(void);
+/* wait RTC registers synchronized flag set */
+void rtc_register_sync_wait(void);
+/* set RTC alarm value */
+void rtc_alarm_config(uint32_t alarm);
+/* get RTC counter value */
+uint32_t rtc_counter_get(void);
+/* get RTC divider value */
+uint32_t rtc_divider_get(void);
+
+/* flag & interrupt functions */
+/* get RTC flag status */
+FlagStatus rtc_flag_get(uint32_t flag);
+/* clear RTC flag status */
+void rtc_flag_clear(uint32_t flag);
+/* get RTC interrupt flag status */
+FlagStatus rtc_interrupt_flag_get(uint32_t flag);
+/* clear RTC interrupt flag status */
+void rtc_interrupt_flag_clear(uint32_t flag);
+/* enable RTC interrupt */
+void rtc_interrupt_enable(uint32_t interrupt);
+/* disable RTC interrupt */
+void rtc_interrupt_disable(uint32_t interrupt);
+
+#endif /* GD32F10X_RTC_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h
new file mode 100644
index 0000000..4ba9e25
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h
@@ -0,0 +1,430 @@
+/*!
+ \file gd32f10x_sdio.h
+ \brief definitions for the SDIO
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_SDIO_H
+#define GD32F10X_SDIO_H
+
+#include "gd32f10x.h"
+
+/* SDIO definitions */
+#define SDIO SDIO_BASE
+
+/* registers definitions */
+#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */
+#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */
+#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */
+#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */
+#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */
+#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */
+#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */
+#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */
+#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */
+#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */
+#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */
+#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */
+#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */
+#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */
+#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */
+#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */
+#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */
+#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */
+
+/* bits definitions */
+/* SDIO_PWRCTL */
+#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
+
+/* SDIO_CLKCTL */
+#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */
+#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */
+#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
+#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */
+#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */
+#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */
+#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */
+
+/* SDIO_CMDAGMT */
+#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
+
+/* SDIO_CMDCTL */
+#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
+#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */
+#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */
+#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */
+#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */
+#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */
+#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */
+#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */
+#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */
+
+/* SDIO_DATATO */
+#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
+
+/* SDIO_DATALEN */
+#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
+
+/* SDIO_DATACTL */
+#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
+#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
+#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */
+#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */
+#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
+#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */
+#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */
+#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */
+#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */
+
+/* SDIO_STAT */
+#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
+#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
+#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
+#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
+#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
+#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
+#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
+#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
+#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */
+#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */
+#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
+#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */
+#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */
+#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */
+#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
+#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
+#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
+#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
+#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
+#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
+#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */
+#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */
+#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
+#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */
+
+/* SDIO_INTC */
+#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
+#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
+#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
+#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
+#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
+#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
+#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
+#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
+#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
+#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */
+#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
+#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
+#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */
+
+/* SDIO_INTEN */
+#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
+#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
+#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
+#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
+#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
+#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
+#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
+#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
+#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
+#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */
+#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
+#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */
+#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */
+#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */
+#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
+#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
+#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */
+#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
+#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
+#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */
+#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */
+#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */
+#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
+#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */
+
+/* SDIO_FIFO */
+#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */
+
+/* constants definitions */
+/* SDIO flags */
+#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
+#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
+#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
+#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
+#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
+#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
+#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
+#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
+#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
+#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */
+#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
+#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */
+#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */
+#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */
+#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
+#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
+#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
+#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
+#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
+#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
+#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */
+#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */
+#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
+#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */
+
+/* SDIO interrupt enable or disable */
+#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
+#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
+#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
+#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
+#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
+#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
+#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
+#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
+#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
+#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */
+#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
+#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
+#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
+#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
+#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
+#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
+#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */
+#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
+#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
+#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */
+#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
+#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
+#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
+#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
+
+/* SDIO interrupt flags */
+#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */
+#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */
+#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */
+#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */
+#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */
+#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */
+#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */
+#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */
+#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */
+#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */
+#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */
+#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */
+#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */
+#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */
+#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */
+#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */
+#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */
+#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */
+#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */
+#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */
+#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */
+#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */
+#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */
+#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */
+
+/* SDIO power control */
+#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
+#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
+
+/* SDIO card bus mode control */
+#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
+#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
+#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
+#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
+
+/* SDIO_CLK clock edge selection */
+#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
+#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
+
+/* clock bypass enable or disable */
+#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */
+#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */
+
+/* SDIO_CLK clock dynamic switch on/off for power saving */
+#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */
+#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
+
+/* SDIO command response type */
+#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
+#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
+#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
+#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
+
+/* command state machine wait type */
+#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */
+#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
+#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
+
+#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */
+#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */
+#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */
+#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */
+
+/* SDIO data block size */
+#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
+#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
+#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
+#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
+#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
+#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
+#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
+#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
+#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
+#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
+#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
+#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
+#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
+#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
+#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
+
+/* SDIO data transfer mode */
+#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */
+#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */
+
+/* SDIO data transfer direction */
+#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */
+#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
+
+/* SDIO read wait type */
+#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */
+#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
+
+/* function declarations */
+/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */
+/* deinitialize the SDIO */
+void sdio_deinit(void);
+/* configure the SDIO clock */
+void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
+/* enable hardware clock control */
+void sdio_hardware_clock_enable(void);
+/* disable hardware clock control */
+void sdio_hardware_clock_disable(void);
+/* set different SDIO card bus mode */
+void sdio_bus_mode_set(uint32_t bus_mode);
+/* set the SDIO power state */
+void sdio_power_state_set(uint32_t power_state);
+/* get the SDIO power state */
+uint32_t sdio_power_state_get(void);
+/* enable SDIO_CLK clock output */
+void sdio_clock_enable(void);
+/* disable SDIO_CLK clock output */
+void sdio_clock_disable(void);
+
+/* configure the command index, argument, response type, wait type and CSM to send command functions */
+/* configure the command and response */
+void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
+/* set the command state machine wait type */
+void sdio_wait_type_set(uint32_t wait_type);
+/* enable the CSM(command state machine) */
+void sdio_csm_enable(void);
+/* disable the CSM(command state machine) */
+void sdio_csm_disable(void);
+/* get the last response command index */
+uint8_t sdio_command_index_get(void);
+/* get the response for the last received command */
+uint32_t sdio_response_get(uint32_t responsex);
+
+/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */
+/* configure the data timeout, data length and data block size */
+void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
+/* configure the data transfer mode and direction */
+void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
+/* enable the DSM(data state machine) for data transfer */
+void sdio_dsm_enable(void);
+/* disable the DSM(data state machine) */
+void sdio_dsm_disable(void);
+/* write data(one word) to the transmit FIFO */
+void sdio_data_write(uint32_t data);
+/* read data(one word) from the receive FIFO */
+uint32_t sdio_data_read(void);
+/* get the number of remaining data bytes to be transferred to card */
+uint32_t sdio_data_counter_get(void);
+/* get the number of words remaining to be written or read from FIFO */
+uint32_t sdio_fifo_counter_get(void);
+/* enable the DMA request for SDIO */
+void sdio_dma_enable(void);
+/* disable the DMA request for SDIO */
+void sdio_dma_disable(void);
+
+/* flag and interrupt functions */
+/* get the flags state of SDIO */
+FlagStatus sdio_flag_get(uint32_t flag);
+/* clear the pending flags of SDIO */
+void sdio_flag_clear(uint32_t flag);
+/* enable the SDIO interrupt */
+void sdio_interrupt_enable(uint32_t int_flag);
+/* disable the SDIO interrupt */
+void sdio_interrupt_disable(uint32_t int_flag);
+/* get the interrupt flags state of SDIO */
+FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
+/* clear the interrupt pending flags of SDIO */
+void sdio_interrupt_flag_clear(uint32_t int_flag);
+
+/* SD I/O card functions */
+/* enable the read wait mode(SD I/O only) */
+void sdio_readwait_enable(void);
+/* disable the read wait mode(SD I/O only) */
+void sdio_readwait_disable(void);
+/* enable the function that stop the read wait process(SD I/O only) */
+void sdio_stop_readwait_enable(void);
+/* disable the function that stop the read wait process(SD I/O only) */
+void sdio_stop_readwait_disable(void);
+/* set the read wait type(SD I/O only) */
+void sdio_readwait_type_set(uint32_t readwait_type);
+/* enable the SD I/O mode specific operation(SD I/O only) */
+void sdio_operation_enable(void);
+/* disable the SD I/O mode specific operation(SD I/O only) */
+void sdio_operation_disable(void);
+/* enable the SD I/O suspend operation(SD I/O only) */
+void sdio_suspend_enable(void);
+/* disable the SD I/O suspend operation(SD I/O only) */
+void sdio_suspend_disable(void);
+
+/* CE-ATA functions */
+/* enable the CE-ATA command(CE-ATA only) */
+void sdio_ceata_command_enable(void);
+/* disable the CE-ATA command(CE-ATA only) */
+void sdio_ceata_command_disable(void);
+/* enable the CE-ATA interrupt(CE-ATA only) */
+void sdio_ceata_interrupt_enable(void);
+/* disable the CE-ATA interrupt(CE-ATA only) */
+void sdio_ceata_interrupt_disable(void);
+/* enable the CE-ATA command completion signal(CE-ATA only) */
+void sdio_ceata_command_completion_enable(void);
+/* disable the CE-ATA command completion signal(CE-ATA only) */
+void sdio_ceata_command_completion_disable(void);
+
+#endif /* GD32F10X_SDIO_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h
new file mode 100644
index 0000000..e7a86bf
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h
@@ -0,0 +1,324 @@
+/*!
+ \file gd32f10x_spi.h
+ \brief definitions for the SPI
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_SPI_H
+#define GD32F10X_SPI_H
+
+#include "gd32f10x.h"
+
+/* SPIx(x=0,1,2) definitions */
+#define SPI0 (SPI_BASE + 0x0000F800U)
+#define SPI1 SPI_BASE
+#define SPI2 (SPI_BASE + 0x00000400U)
+
+/* registers definitions */
+#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
+#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
+#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
+#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
+#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
+#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
+#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
+#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
+#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
+
+/* bits definitions */
+/* SPI_CTL0 */
+#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
+#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
+#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
+#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
+#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
+#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
+#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
+#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
+#define SPI_CTL0_RO BIT(10) /*!< receive only */
+#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
+#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
+#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
+#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
+#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
+
+/* SPI_CTL1 */
+#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */
+#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */
+#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
+#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
+#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
+#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
+
+/* SPI_STAT */
+#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
+#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
+#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
+#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
+#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
+#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
+#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
+#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
+
+/* SPI_DATA */
+#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
+
+/* SPI_CRCPOLY */
+#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
+
+/* SPI_RCRC */
+#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
+
+/* SPI_TCRC */
+#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
+
+/* SPI_I2SCTL */
+#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
+#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
+#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
+#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
+#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
+#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
+#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
+#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
+
+/* SPI_I2SPSC */
+#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
+#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
+#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
+
+/* constants definitions */
+/* SPI and I2S parameter struct definitions */
+typedef struct {
+ uint32_t device_mode; /*!< SPI master or slave */
+ uint32_t trans_mode; /*!< SPI transfer type */
+ uint32_t frame_size; /*!< SPI frame size */
+ uint32_t nss; /*!< SPI NSS control by handware or software */
+ uint32_t endian; /*!< SPI big endian or little endian */
+ uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
+ uint32_t prescale; /*!< SPI prescaler factor */
+} spi_parameter_struct;
+
+/* SPI mode definitions */
+#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
+#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
+
+/* SPI bidirectional transfer direction */
+#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
+#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
+
+/* SPI transmit type */
+#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
+#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
+#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
+#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
+
+/* SPI frame size */
+#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
+#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
+
+/* SPI NSS control mode */
+#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
+#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
+
+/* SPI transmit way */
+#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
+#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
+
+/* SPI clock phase and polarity */
+#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
+#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
+#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
+#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
+
+/* SPI clock prescaler factor */
+#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */
+#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */
+#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */
+#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */
+#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */
+#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */
+#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */
+#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */
+
+/* I2S audio sample rate */
+#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
+#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
+#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
+#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
+#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
+#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
+#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
+#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
+#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
+
+/* I2S frame format */
+#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
+#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
+#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
+
+/* I2S master clock output */
+#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
+#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
+
+/* I2S operation mode */
+#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
+#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
+#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
+#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
+
+/* I2S standard */
+#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
+#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
+#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
+#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
+#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
+
+/* I2S clock polarity */
+#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
+#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
+
+/* SPI DMA constants definitions */
+#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
+#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
+
+/* SPI CRC constants definitions */
+#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
+#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
+
+/* SPI/I2S interrupt enable/disable constants definitions */
+#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */
+#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */
+#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */
+
+/* SPI/I2S interrupt flag constants definitions */
+#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
+#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
+#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
+#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
+
+/* SPI/I2S flag definitions */
+#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
+#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
+#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
+#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
+#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
+#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
+#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
+#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
+#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
+#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
+#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
+#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
+
+/* function declarations */
+/* SPI deinitialization and initialization functions */
+/* reset SPI and I2S */
+void spi_i2s_deinit(uint32_t spi_periph);
+/* initialize the parameters of SPI structure with the default values */
+void spi_struct_para_init(spi_parameter_struct *spi_struct);
+/* initialize SPI parameters */
+void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
+/* enable SPI */
+void spi_enable(uint32_t spi_periph);
+/* disable SPI */
+void spi_disable(uint32_t spi_periph);
+
+/* I2S initialization functions */
+/* initialize I2S parameters */
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
+/* configure I2S prescaler */
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
+/* enable I2S */
+void i2s_enable(uint32_t spi_periph);
+/* disable I2S */
+void i2s_disable(uint32_t spi_periph);
+
+/* NSS functions */
+/* enable SPI NSS output */
+void spi_nss_output_enable(uint32_t spi_periph);
+/* disable SPI NSS output */
+void spi_nss_output_disable(uint32_t spi_periph);
+/* SPI NSS pin high level in software mode */
+void spi_nss_internal_high(uint32_t spi_periph);
+/* SPI NSS pin low level in software mode */
+void spi_nss_internal_low(uint32_t spi_periph);
+
+/* DMA functions */
+/* enable SPI DMA send or receive */
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
+/* disable SPI DMA send or receive */
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
+
+/* communication functions */
+/* configure SPI data frame format */
+void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
+/* configure SPI bidirectional transfer direction */
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
+/* SPI transmit data */
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
+/* SPI receive data */
+uint16_t spi_i2s_data_receive(uint32_t spi_periph);
+
+/* SPI CRC functions */
+/* set SPI CRC polynomial */
+void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
+/* get SPI CRC polynomial */
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
+/* turn on SPI CRC function */
+void spi_crc_on(uint32_t spi_periph);
+/* turn off SPI CRC function */
+void spi_crc_off(uint32_t spi_periph);
+/* SPI next data is CRC value */
+void spi_crc_next(uint32_t spi_periph);
+/* get SPI CRC send value or receive value */
+uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
+/* clear SPI CRC error flag status */
+void spi_crc_error_clear(uint32_t spi_periph);
+
+/* flag and interrupt functions */
+/* get SPI and I2S flag status */
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
+/* enable SPI and I2S interrupt */
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
+/* disable SPI and I2S interrupt */
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S interrupt status */
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
+
+#endif /* GD32F10X_SPI_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h
new file mode 100644
index 0000000..561858b
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h
@@ -0,0 +1,725 @@
+/*!
+ \file gd32f10x_timer.h
+ \brief definitions for the TIMER
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_TIMER_H
+#define GD32F10X_TIMER_H
+
+#include "gd32f10x.h"
+
+/* TIMERx(x=0..13) definitions */
+#define TIMER0 (TIMER_BASE + 0x00012C00U)
+#define TIMER1 (TIMER_BASE + 0x00000000U)
+#define TIMER2 (TIMER_BASE + 0x00000400U)
+#define TIMER3 (TIMER_BASE + 0x00000800U)
+#define TIMER4 (TIMER_BASE + 0x00000C00U)
+#define TIMER5 (TIMER_BASE + 0x00001000U)
+#define TIMER6 (TIMER_BASE + 0x00001400U)
+#define TIMER7 (TIMER_BASE + 0x00013400U)
+#define TIMER8 (TIMER_BASE + 0x00014C00U)
+#define TIMER9 (TIMER_BASE + 0x00015000U)
+#define TIMER10 (TIMER_BASE + 0x00015400U)
+#define TIMER11 (TIMER_BASE + 0x00001800U)
+#define TIMER12 (TIMER_BASE + 0x00001C00U)
+#define TIMER13 (TIMER_BASE + 0x00002000U)
+
+/* registers definitions */
+#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */
+#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */
+#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */
+#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */
+#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
+#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */
+#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */
+#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */
+#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */
+#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */
+#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */
+#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */
+#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */
+#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */
+#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */
+#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */
+#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */
+#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */
+#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */
+#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */
+
+/* bits definitions */
+/* TIMER_CTL0 */
+#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */
+#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */
+#define TIMER_CTL0_UPS BIT(2) /*!< update source */
+#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
+#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */
+#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
+#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
+#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */
+
+/* TIMER_CTL1 */
+#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */
+#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */
+#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */
+#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
+#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
+#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */
+#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */
+#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */
+#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */
+#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */
+#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */
+#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */
+
+/* TIMER_SMCFG */
+#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
+#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */
+#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
+#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */
+#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */
+#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */
+#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */
+
+/* TIMER_DMAINTEN */
+#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */
+#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */
+#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */
+#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */
+#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */
+#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */
+#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */
+
+/* TIMER_INTF */
+#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */
+#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */
+#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */
+#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */
+#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */
+#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */
+#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */
+#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */
+#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */
+#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */
+#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */
+#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */
+
+/* TIMER_SWEVG */
+#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */
+#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */
+#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */
+#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */
+#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */
+#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */
+#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */
+#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */
+
+/* TIMER_CHCTL0 */
+/* output compare mode */
+#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */
+#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */
+#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */
+#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */
+#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */
+#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */
+#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */
+#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */
+#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */
+#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */
+#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */
+#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */
+#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */
+
+/* TIMER_CHCTL1 */
+/* output compare mode */
+#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */
+#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */
+#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */
+#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */
+#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */
+#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */
+#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */
+#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */
+#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */
+#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */
+#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */
+#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */
+#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */
+
+/* TIMER_CHCTL2 */
+#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */
+#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */
+#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */
+#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */
+#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */
+#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */
+#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */
+#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */
+#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */
+#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */
+#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */
+#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */
+#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */
+#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */
+
+/* TIMER_CNT */
+#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */
+
+/* TIMER_PSC */
+#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */
+
+/* TIMER_CAR */
+#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */
+
+/* TIMER_CREP */
+#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */
+
+/* TIMER_CH0CV */
+#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */
+
+/* TIMER_CH1CV */
+#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */
+
+/* TIMER_CH2CV */
+#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */
+
+/* TIMER_CH3CV */
+#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */
+
+/* TIMER_CCHP */
+#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */
+#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */
+#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */
+#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */
+#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */
+#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */
+#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */
+#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */
+
+/* TIMER_DMACFG */
+#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */
+#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */
+
+/* TIMER_DMATB */
+#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */
+
+/* constants definitions */
+/* TIMER init parameter struct definitions */
+typedef struct
+{
+ uint16_t prescaler; /*!< prescaler value */
+ uint16_t alignedmode; /*!< aligned mode */
+ uint16_t counterdirection; /*!< counter direction */
+ uint32_t period; /*!< period value */
+ uint16_t clockdivision; /*!< clock division value */
+ uint8_t repetitioncounter; /*!< the counter repetition value */
+}timer_parameter_struct;
+
+/* break parameter struct definitions*/
+typedef struct
+{
+ uint16_t runoffstate; /*!< run mode off-state */
+ uint16_t ideloffstate; /*!< idle mode off-state */
+ uint16_t deadtime; /*!< dead time */
+ uint16_t breakpolarity; /*!< break polarity */
+ uint16_t outputautostate; /*!< output automatic enable */
+ uint16_t protectmode; /*!< complementary register protect control */
+ uint16_t breakstate; /*!< break enable */
+}timer_break_parameter_struct;
+
+/* channel output parameter struct definitions */
+typedef struct
+{
+ uint16_t outputstate; /*!< channel output state */
+ uint16_t outputnstate; /*!< channel complementary output state */
+ uint16_t ocpolarity; /*!< channel output polarity */
+ uint16_t ocnpolarity; /*!< channel complementary output polarity */
+ uint16_t ocidlestate; /*!< idle state of channel output */
+ uint16_t ocnidlestate; /*!< idle state of channel complementary output */
+}timer_oc_parameter_struct;
+
+/* channel input parameter struct definitions */
+typedef struct
+{
+ uint16_t icpolarity; /*!< channel input polarity */
+ uint16_t icselection; /*!< channel input mode selection */
+ uint16_t icprescaler; /*!< channel input capture prescaler */
+ uint16_t icfilter; /*!< channel input capture filter control */
+}timer_ic_parameter_struct;
+
+/* TIMER interrupt enable or disable */
+#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */
+#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */
+#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */
+#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */
+#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */
+#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */
+#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */
+#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */
+
+/* TIMER interrupt flag */
+#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */
+#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */
+#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */
+#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */
+#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */
+#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */
+#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */
+#define TIMER_INT_FLAG_BRK TIMER_INT_BRK
+
+/* TIMER flag */
+#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */
+#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */
+#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */
+#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */
+#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */
+#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */
+#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */
+#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */
+#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */
+#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */
+#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */
+#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */
+/* TIMER DMA source enable */
+#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
+#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
+#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */
+#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */
+#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */
+#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */
+#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */
+
+/* channel DMA request source selection */
+#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */
+#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */
+
+/* DMA access base address */
+#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
+#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */
+#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */
+#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */
+#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */
+#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */
+#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */
+#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */
+#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */
+#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */
+#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */
+#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */
+#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */
+#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */
+#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */
+#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */
+#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */
+#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */
+#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */
+#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */
+
+/* DMA access burst length */
+#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
+#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */
+#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */
+#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */
+#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */
+#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */
+#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */
+#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */
+#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */
+#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */
+#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */
+#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */
+#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */
+#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */
+#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */
+#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */
+#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */
+#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */
+#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */
+
+/* TIMER software event generation source */
+#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */
+#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */
+#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */
+#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */
+#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */
+
+/* center-aligned mode selection */
+#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
+#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */
+#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */
+#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */
+#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */
+
+/* TIMER prescaler reload mode */
+#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */
+#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */
+
+/* count direction */
+#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */
+#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */
+
+/* specify division ratio between TIMER clock and dead-time and sampling clock */
+#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */
+#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */
+#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
+
+/* single pulse mode */
+#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */
+#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */
+
+/* update source */
+#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */
+#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
+
+/* run mode off-state configure */
+#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */
+
+/* idle mode off-state configure */
+#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */
+
+/* break input polarity */
+#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */
+#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */
+
+/* output automatic enable */
+#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */
+#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */
+
+/* complementary register protect control */
+#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */
+#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */
+#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */
+#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */
+
+/* break input enable */
+#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */
+#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */
+
+/* TIMER channel n(n=0,1,2,3) */
+#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */
+#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */
+#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */
+#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */
+
+/* channel enable state */
+#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */
+#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */
+
+/* channel complementary output enable state */
+#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */
+#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */
+
+/* channel output polarity */
+#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */
+#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */
+
+/* channel complementary output polarity */
+#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */
+#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */
+
+/* idle state of channel output */
+#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */
+#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */
+
+/* idle state of channel complementary output */
+#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */
+#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */
+
+/* channel output compare mode */
+#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */
+#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */
+#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */
+#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */
+#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */
+#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */
+#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */
+#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/
+
+/* channel output compare shadow enable */
+#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */
+#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */
+
+/* channel output compare fast enable */
+#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */
+#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */
+
+/* channel output compare clear enable */
+#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */
+#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */
+
+/* channel control shadow register update control */
+#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */
+#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
+
+/* channel input capture polarity */
+#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */
+#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */
+
+/* timer input capture selection */
+#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */
+#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */
+#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */
+
+/* channel input capture prescaler */
+#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */
+#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */
+#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */
+#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */
+
+/* trigger selection */
+#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */
+#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */
+#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */
+#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */
+#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */
+#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */
+#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */
+#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */
+
+/* master mode control */
+#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */
+#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
+#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */
+#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */
+#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */
+
+/* slave mode control */
+#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
+#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
+#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */
+#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */
+#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */
+#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
+#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
+#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
+#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */
+
+/* master slave mode selection */
+#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */
+#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */
+
+/* external trigger prescaler */
+#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
+#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */
+#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */
+#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */
+#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */
+
+/* external trigger polarity */
+#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */
+#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */
+
+/* channel 0 trigger input selection */
+#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */
+#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */
+
+/* TIMERx(x=0..4,7..13) write CHxVAL register selection */
+#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */
+#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */
+
+/* function declarations */
+/* TIMER timebase */
+/* deinit a TIMER */
+void timer_deinit(uint32_t timer_periph);
+/* initialize TIMER init parameter struct */
+void timer_struct_para_init(timer_parameter_struct* initpara);
+/* initialize TIMER counter */
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
+/* enable a TIMER */
+void timer_enable(uint32_t timer_periph);
+/* disable a TIMER */
+void timer_disable(uint32_t timer_periph);
+/* enable the auto reload shadow function */
+void timer_auto_reload_shadow_enable(uint32_t timer_periph);
+/* disable the auto reload shadow function */
+void timer_auto_reload_shadow_disable(uint32_t timer_periph);
+/* enable the update event */
+void timer_update_event_enable(uint32_t timer_periph);
+/* disable the update event */
+void timer_update_event_disable(uint32_t timer_periph);
+/* set TIMER counter alignment mode */
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
+/* set TIMER counter up direction */
+void timer_counter_up_direction(uint32_t timer_periph);
+/* set TIMER counter down direction */
+void timer_counter_down_direction(uint32_t timer_periph);
+/* configure TIMER prescaler */
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload);
+/* configure TIMER repetition register value */
+void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition);
+/* configure TIMER autoreload register value */
+void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload);
+/* configure TIMER counter register value */
+void timer_counter_value_config(uint32_t timer_periph, uint32_t counter);
+/* read TIMER counter value */
+uint32_t timer_counter_read(uint32_t timer_periph);
+/* read TIMER prescaler value */
+uint16_t timer_prescaler_read(uint32_t timer_periph);
+/* configure TIMER single pulse mode */
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
+/* configure TIMER update source */
+void timer_update_source_config(uint32_t timer_periph, uint32_t update);
+
+/* timer DMA and event */
+/* enable the TIMER DMA */
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
+/* disable the TIMER DMA */
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
+/* channel DMA request source selection */
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request);
+/* configure the TIMER DMA transfer */
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
+/* software generate events */
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
+
+/* TIMER channel complementary protection */
+/* initialize TIMER break parameter struct */
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
+/* configure TIMER break function */
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
+/* enable TIMER break function */
+void timer_break_enable(uint32_t timer_periph);
+/* disable TIMER break function */
+void timer_break_disable(uint32_t timer_periph);
+/* enable TIMER output automatic function */
+void timer_automatic_output_enable(uint32_t timer_periph);
+/* disable TIMER output automatic function */
+void timer_automatic_output_disable(uint32_t timer_periph);
+/* enable or disable TIMER primary output function */
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
+/* enable or disable channel capture/compare control shadow register */
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
+/* configure TIMER channel control shadow register update control */
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl);
+
+/* TIMER channel output */
+/* initialize TIMER channel output parameter struct */
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output function */
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output compare mode */
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
+/* configure TIMER channel output pulse value */
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint16_t pulse);
+/* configure TIMER channel output shadow function */
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
+/* configure TIMER channel output fast function */
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
+/* configure TIMER channel output clear function */
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
+/* configure TIMER channel output polarity */
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
+/* configure TIMER channel complementary output polarity */
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
+/* configure TIMER channel enable state */
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
+/* configure TIMER channel complementary output enable state */
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
+
+/* TIMER channel input */
+/* initialize TIMER channel input parameter struct */
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
+/* configure TIMER input capture parameter */
+void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
+/* configure TIMER channel input capture prescaler value */
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
+/* read TIMER channel capture compare register value */
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
+/* configure TIMER input pwm capture function */
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
+/* configure TIMER hall sensor mode */
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
+
+/* TIMER master and slave */
+/* select TIMER input trigger source */
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
+/* select TIMER master mode output trigger source */
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
+/* select TIMER slave mode */
+void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
+/* configure TIMER master slave mode */
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
+/* configure TIMER external trigger input */
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
+/* configure TIMER quadrature decoder mode */
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
+/* configure TIMER internal clock mode */
+void timer_internal_clock_config(uint32_t timer_periph);
+/* configure TIMER the internal trigger as external clock input */
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
+/* configure TIMER the external trigger as external clock input */
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint8_t extfilter);
+/* configure TIMER the external clock mode 0 */
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
+/* configure TIMER the external clock mode 1 */
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
+/* disable TIMER the external clock mode 1 */
+void timer_external_clock_mode1_disable(uint32_t timer_periph);
+
+/* TIMER interrupt and flag */
+/* enable the TIMER interrupt */
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
+/* disable the TIMER interrupt */
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER interrupt flag */
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
+/* clear TIMER interrupt flag */
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER flag */
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
+/* clear TIMER flag */
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
+
+#endif /* GD32E10X_TIMER_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h
new file mode 100644
index 0000000..206dab1
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h
@@ -0,0 +1,373 @@
+/*!
+ \file gd32f10x_usart.h
+ \brief definitions for the USART
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_USART_H
+#define GD32F10X_USART_H
+
+#include "gd32f10x.h"
+
+/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
+#define USART1 USART_BASE /*!< USART1 base address */
+#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */
+#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */
+#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */
+#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */
+
+/* registers definitions */
+#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */
+#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */
+#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */
+#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */
+#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */
+#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */
+#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */
+
+/* bits definitions */
+/* USARTx_STAT */
+#define USART_STAT_PERR BIT(0) /*!< parity error flag */
+#define USART_STAT_FERR BIT(1) /*!< frame error flag */
+#define USART_STAT_NERR BIT(2) /*!< noise error flag */
+#define USART_STAT_ORERR BIT(3) /*!< overrun error */
+#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */
+#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */
+#define USART_STAT_TC BIT(6) /*!< transmission complete */
+#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */
+#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
+#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
+
+/* USARTx_DATA */
+#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */
+
+/* USARTx_BAUD */
+#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */
+#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */
+
+/* USARTx_CTL0 */
+#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
+#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
+#define USART_CTL0_REN BIT(2) /*!< enable receiver */
+#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */
+#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */
+#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */
+#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */
+#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */
+#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */
+#define USART_CTL0_PM BIT(9) /*!< parity mode */
+#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */
+#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
+#define USART_CTL0_WL BIT(12) /*!< word length */
+#define USART_CTL0_UEN BIT(13) /*!< enable USART */
+
+/* USARTx_CTL1 */
+#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
+#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
+#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */
+#define USART_CTL1_CLEN BIT(8) /*!< CK length */
+#define USART_CTL1_CPH BIT(9) /*!< CK phase */
+#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
+#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */
+#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
+#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */
+
+/* USARTx_CTL2 */
+#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */
+#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */
+#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
+#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
+#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
+#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */
+#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */
+#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */
+#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */
+#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */
+#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */
+
+/* USARTx_GP */
+#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
+#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
+
+/* constants definitions */
+/* define the USART bit position and its register index offset */
+#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6)))
+#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU))
+#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+ | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
+#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16)
+
+/* register offset */
+#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */
+#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */
+#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */
+#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */
+
+/* USART flags */
+typedef enum
+{
+ /* flags in STAT register */
+ USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
+ USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
+ USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
+ USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
+ USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
+ USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
+ USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
+ USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
+ USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
+ USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
+}usart_flag_enum;
+
+/* USART interrupt flags */
+typedef enum
+{
+ /* interrupt flags in CTL0 register */
+ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
+ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
+ USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
+ USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
+ USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
+ USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
+ /* interrupt flags in CTL1 register */
+ USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
+ /* interrupt flags in CTL2 register */
+ USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
+ USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
+ USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
+ USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
+}usart_interrupt_flag_enum;
+
+/* USART interrupt enable or disable */
+typedef enum
+{
+ /* interrupt in CTL0 register */
+ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
+ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
+ USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
+ USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
+ USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
+ /* interrupt in CTL1 register */
+ USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
+ /* interrupt in CTL2 register */
+ USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
+ USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
+}usart_interrupt_enum;
+
+/* configure USART receiver */
+#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
+#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
+
+/* configure USART transmitter */
+#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
+#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
+#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
+
+/* USART parity bits definitions */
+#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
+#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
+#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
+#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
+
+/* USART wakeup method in mute mode */
+#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
+#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
+#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
+
+/* USART word length definitions */
+#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
+#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
+#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
+
+/* USART stop bits definitions */
+#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
+#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
+#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
+#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
+#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
+
+/* USART LIN break frame length */
+#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
+#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */
+#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */
+
+/* USART CK length */
+#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
+#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
+
+/* USART clock phase */
+#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
+#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
+
+/* USART clock polarity */
+#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
+#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
+#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
+
+/* configure USART DMA */
+#define CLT2_RECEIVE_DMAEN(regval) (BIT(6) & ((uint32_t)(regval) << 6))
+#define CTL2_TRANSMIT_DMAEN(regval) (BIT(7) & ((uint32_t)(regval) << 7))
+#define USART_RECEIVE_DMA_ENABLE CLT2_RECEIVE_DMAEN(1) /* enable DMA request for reception */
+#define USART_RECEIVE_DMA_DISABLE CLT2_RECEIVE_DMAEN(0) /* disable DMA request for reception */
+#define USART_TRANSMIT_DMA_ENABLE CTL2_TRANSMIT_DMAEN(1) /* enable DMA request for transmission */
+#define USART_TRANSMIT_DMA_DISABLE CTL2_TRANSMIT_DMAEN(0) /* disable DMA request for transmission */
+
+/* configure USART RTS */
+#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */
+#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */
+
+/* configure USART CTS */
+#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */
+#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */
+
+/* enable USART IrDA low-power */
+#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
+#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
+
+/* function declarations */
+/* initialization functions */
+/* reset USART */
+void usart_deinit(uint32_t usart_periph);
+/* configure USART baud rate value */
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
+/* configure USART parity function */
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
+/* configure USART word length */
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
+/* configure USART stop bit length */
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
+
+/* USART normal mode communication */
+/* enable USART */
+void usart_enable(uint32_t usart_periph);
+/* disable USART */
+void usart_disable(uint32_t usart_periph);
+/* configure USART transmitter */
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
+/* configure USART receiver */
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
+/* USART transmit data function */
+void usart_data_transmit(uint32_t usart_periph, uint16_t data);
+/* USART receive data function */
+uint16_t usart_data_receive(uint32_t usart_periph);
+
+/* multi-processor communication */
+/* configure address of the USART */
+void usart_address_config(uint32_t usart_periph, uint8_t addr);
+/* enable mute mode */
+void usart_mute_mode_enable(uint32_t usart_periph);
+/* disable mute mode */
+void usart_mute_mode_disable(uint32_t usart_periph);
+/* configure wakeup method in mute mode */
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
+
+/* LIN mode communication */
+/* enable LIN mode */
+void usart_lin_mode_enable(uint32_t usart_periph);
+/* disable LIN mode */
+void usart_lin_mode_disable(uint32_t usart_periph);
+/* configure LIN break frame length */
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
+/* send break frame */
+void usart_send_break(uint32_t usart_periph);
+
+/* half-duplex communication */
+/* enable half-duplex */
+void usart_halfduplex_enable(uint32_t usart_periph);
+/* disable half-duplex */
+void usart_halfduplex_disable(uint32_t usart_periph);
+
+/* synchronous communication */
+/* enable CK pin in synchronous mode */
+void usart_synchronous_clock_enable(uint32_t usart_periph);
+/* disable CK pin in synchronous mode */
+void usart_synchronous_clock_disable(uint32_t usart_periph);
+/* configure usart synchronous mode parameters */
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
+
+/* smartcard communication */
+/* configure guard time value in smartcard mode */
+void usart_guard_time_config(uint32_t usart_periph,uint8_t gaut);
+/* enable smartcard mode */
+void usart_smartcard_mode_enable(uint32_t usart_periph);
+/* disable smartcard mode */
+void usart_smartcard_mode_disable(uint32_t usart_periph);
+/* enable NACK in smartcard mode */
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
+/* disable NACK in smartcard mode */
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
+
+/* IrDA communication */
+/* enable IrDA mode */
+void usart_irda_mode_enable(uint32_t usart_periph);
+/* disable IrDA mode */
+void usart_irda_mode_disable(uint32_t usart_periph);
+/* configure the peripheral clock prescaler */
+void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
+/* configure IrDA low-power */
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
+
+/* hardware flow communication */
+/* configure hardware flow control RTS */
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
+/* configure hardware flow control CTS */
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
+
+/* DMA communication */
+/* configure USART DMA for reception */
+void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig);
+/* configure USART DMA for transmission */
+void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig);
+
+/* flag functions */
+/* get flag in STAT register */
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
+/* clear flag in STAT register */
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
+
+/* interrupt functions */
+/* enable USART interrupt */
+void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt);
+/* disable USART interrupt */
+void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt);
+/* get USART interrupt and flag status */
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
+/* clear interrupt flag in STAT register */
+void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag);
+#endif /* GD32F10X_USART_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h
new file mode 100644
index 0000000..c9e6109
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h
@@ -0,0 +1,91 @@
+/*!
+ \file gd32f10x_wwdgt.h
+ \brief definitions for the WWDGT
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F10X_WWDGT_H
+#define GD32F10X_WWDGT_H
+
+#include "gd32f10x.h"
+
+/* WWDGT definitions */
+#define WWDGT WWDGT_BASE /*!< WWDGT base address */
+
+/* registers definitions */
+#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
+#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */
+#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */
+
+/* bits definitions */
+/* WWDGT_CTL */
+#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
+
+/* WWDGT_CFG */
+#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
+
+/* WWDGT_STAT */
+#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
+
+/* constants definitions */
+#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+
+/* write value to WWDGT_CTL_CNT bit field */
+#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
+/* write value to WWDGT_CFG_WIN bit field */
+#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
+
+/* function declarations */
+/* reset the window watchdog timer configuration */
+void wwdgt_deinit(void);
+/* start the window watchdog timer counter */
+void wwdgt_enable(void);
+
+/* configure the window watchdog timer counter value */
+void wwdgt_counter_update(uint16_t counter_value);
+/* configure counter value, window value, and prescaler divider value */
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
+
+/* check early wakeup interrupt state of WWDGT */
+FlagStatus wwdgt_flag_get(void);
+/* clear early wakeup interrupt state of WWDGT */
+void wwdgt_flag_clear(void);
+/* enable early wakeup interrupt of WWDGT */
+void wwdgt_interrupt_enable(void);
+
+#endif /* GD32F10X_WWDGT_H */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c
new file mode 100644
index 0000000..33d5bf0
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c
@@ -0,0 +1,929 @@
+/*!
+ \file gd32f10x_adc.c
+ \brief ADC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_adc.h"
+
+/* discontinuous mode macro*/
+#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
+
+/* ADC regular channel macro */
+#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U)
+#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U)
+#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
+#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U)
+
+/* ADC sampling time macro */
+#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
+#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U)
+#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U)
+
+/* ADC inserted channel macro */
+#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U)
+#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U)
+
+/* ADC inserted channel offset macro */
+#define ADC_OFFSET_LENGTH ((uint8_t)3U)
+#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U)
+
+/*!
+ \brief reset ADC
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_deinit(uint32_t adc_periph)
+{
+ switch(adc_periph){
+ case ADC0:
+ /* reset ADC0 */
+ rcu_periph_reset_enable(RCU_ADC0RST);
+ rcu_periph_reset_disable(RCU_ADC0RST);
+ break;
+ case ADC1:
+ /* reset ADC1 */
+ rcu_periph_reset_enable(RCU_ADC1RST);
+ rcu_periph_reset_disable(RCU_ADC1RST);
+ break;
+#ifndef GD32F10X_CL
+ case ADC2:
+ rcu_periph_reset_enable(RCU_ADC2RST);
+ rcu_periph_reset_disable(RCU_ADC2RST);
+ break;
+#endif /* GD32F10X_CL */
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure the ADC sync mode
+ \param[in] mode: ADC mode
+ only one parameter can be selected which is shown as below:
+ \arg ADC_MODE_FREE: all the ADCs work independently
+ \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
+ \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
+ \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
+ \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
+ \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
+ \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
+ \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
+ \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
+ \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
+ \param[out] none
+ \retval none
+*/
+void adc_mode_config(uint32_t mode)
+{
+ ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
+ ADC_CTL0(ADC0) |= mode;
+}
+
+/*!
+ \brief enable or disable ADC special function
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] function: the function to config
+ only one parameter can be selected which is shown as below:
+ \arg ADC_SCAN_MODE: scan mode select
+ \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
+ \arg ADC_CONTINUOUS_MODE: continuous mode select
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
+{
+ if(newvalue){
+ if(0U != (function & ADC_SCAN_MODE)){
+ /* enable scan mode */
+ ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
+ }
+ if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
+ /* enable inserted channel group convert automatically */
+ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
+ }
+ if(0U != (function & ADC_CONTINUOUS_MODE)){
+ /* enable continuous mode */
+ ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
+ }
+ }else{
+ if(0U != (function & ADC_SCAN_MODE)){
+ /* disable scan mode */
+ ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
+ }
+ if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
+ /* disable inserted channel group convert automatically */
+ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
+ }
+ if(0U != (function & ADC_CONTINUOUS_MODE)){
+ /* disable continuous mode */
+ ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
+ }
+ }
+}
+
+/*!
+ \brief configure ADC data alignment
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] data_alignment: data alignment select
+ only one parameter can be selected which is shown as below:
+ \arg ADC_DATAALIGN_RIGHT: LSB alignment
+ \arg ADC_DATAALIGN_LEFT: MSB alignment
+ \param[out] none
+ \retval none
+*/
+void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
+{
+ if(ADC_DATAALIGN_RIGHT != data_alignment){
+ /* MSB alignment */
+ ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
+ }else{
+ /* LSB alignment */
+ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
+ }
+}
+
+/*!
+ \brief enable ADC interface
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_enable(uint32_t adc_periph)
+{
+ if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
+ /* enable ADC */
+ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
+ }
+}
+
+/*!
+ \brief disable ADC interface
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_disable(uint32_t adc_periph)
+{
+ /* disable ADC */
+ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
+}
+
+/*!
+ \brief ADC calibration and reset calibration(GD32F10x_MD series without this function)
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_calibration_enable(uint32_t adc_periph)
+{
+ /* reset the selected ADC1 calibration registers */
+ ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
+ /* check the RSTCLB bit state */
+ while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
+ }
+ /* enable ADC calibration process */
+ ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
+ /* check the CLB bit state */
+ while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
+ }
+}
+
+/*!
+ \brief enable the temperature sensor and Vrefint channel
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_tempsensor_vrefint_enable(void)
+{
+ /* enable the temperature sensor and Vrefint channel */
+ ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
+}
+
+/*!
+ \brief disable the temperature sensor and Vrefint channel
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_tempsensor_vrefint_disable(void)
+{
+ /* disable the temperature sensor and Vrefint channel */
+ ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
+}
+
+/*!
+ \brief enable DMA request
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_dma_mode_enable(uint32_t adc_periph)
+{
+ /* enable DMA request */
+ ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
+}
+
+/*!
+ \brief disable DMA request
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_dma_mode_disable(uint32_t adc_periph)
+{
+ /* disable DMA request */
+ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
+}
+
+/*!
+ \brief configure ADC discontinuous mode
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel_group: select the channel group
+ only one parameter can be selected which is shown as below:
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
+ \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
+ for regular channel, the number has no effect for inserted channel
+ \param[out] none
+ \retval none
+*/
+void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
+{
+ /* disable discontinuous mode of regular & inserted channel */
+ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
+ switch(adc_channel_group){
+ case ADC_REGULAR_CHANNEL:
+ /* config the number of conversions in discontinuous mode */
+ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
+ ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
+ /* enable regular channel group discontinuous mode */
+ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
+ break;
+ case ADC_INSERTED_CHANNEL:
+ /* enable inserted channel group discontinuous mode */
+ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
+ break;
+ case ADC_CHANNEL_DISCON_DISABLE:
+ /* disable discontinuous mode of regular & inserted channel */
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure the length of regular channel group or inserted channel group
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel_group: select the channel group
+ only one parameter can be selected which is shown as below:
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] length: the length of the channel
+ regular channel 1-16
+ inserted channel 1-4
+ \param[out] none
+ \retval none
+*/
+void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
+{
+ switch(adc_channel_group){
+ case ADC_REGULAR_CHANNEL:
+ /* configure the length of regular channel group */
+ ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
+ ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
+ break;
+ case ADC_INSERTED_CHANNEL:
+ /* configure the length of inserted channel group */
+ ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
+ ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure ADC regular channel
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
+ \param[in] adc_channel: the selected ADC channel
+ only one parameter can be selected which is shown as below:
+ \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
+ \param[in] sample_time: the sample time value
+ only one parameter can be selected which is shown as below:
+ \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
+ \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
+ \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
+ \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
+ \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
+ \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
+ \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
+ \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
+ \param[out] none
+ \retval none
+*/
+void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
+{
+ uint32_t rsq,sampt;
+
+ /* ADC regular sequence config */
+ if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
+ /* the regular group sequence rank is smaller than six */
+ rsq = ADC_RSQ2(adc_periph);
+ rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
+ /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
+ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
+ ADC_RSQ2(adc_periph) = rsq;
+ }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
+ /* the regular group sequence rank is smaller than twelve */
+ rsq = ADC_RSQ1(adc_periph);
+ rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
+ /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
+ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
+ ADC_RSQ1(adc_periph) = rsq;
+ }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
+ /* the regular group sequence rank is smaller than sixteen */
+ rsq = ADC_RSQ0(adc_periph);
+ rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
+ /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
+ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
+ ADC_RSQ0(adc_periph) = rsq;
+ }else{
+ }
+
+ /* ADC sampling time config */
+ if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
+ /* the regular group sequence rank is smaller than ten */
+ sampt = ADC_SAMPT1(adc_periph);
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
+ /* channel sample time set*/
+ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
+ ADC_SAMPT1(adc_periph) = sampt;
+ }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
+ /* the regular group sequence rank is smaller than eighteen */
+ sampt = ADC_SAMPT0(adc_periph);
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
+ /* channel sample time set*/
+ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
+ ADC_SAMPT0(adc_periph) = sampt;
+ }else{
+ }
+}
+
+/*!
+ \brief configure ADC inserted channel
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
+ \param[in] adc_channel: the selected ADC channel
+ only one parameter can be selected which is shown as below:
+ \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
+ \param[in] sample_time: The sample time value
+ only one parameter can be selected which is shown as below:
+ \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
+ \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
+ \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
+ \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
+ \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
+ \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
+ \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
+ \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
+ \param[out] none
+ \retval none
+*/
+void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
+{
+ uint8_t inserted_length;
+ uint32_t isq,sampt;
+ /* get inserted channel group length */
+ inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
+ /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
+ isq = ADC_ISQ(adc_periph);
+ isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)));
+ isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH));
+ ADC_ISQ(adc_periph) = isq;
+
+ /* ADC sampling time config */
+ if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
+ /* the inserted group sequence rank is smaller than ten */
+ sampt = ADC_SAMPT1(adc_periph);
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
+ /* channel sample time set*/
+ sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
+ ADC_SAMPT1(adc_periph) = sampt;
+ }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
+ /* the inserted group sequence rank is smaller than eighteen */
+ sampt = ADC_SAMPT0(adc_periph);
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
+ /* channel sample time set*/
+ sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
+ ADC_SAMPT0(adc_periph) = sampt;
+ }else{
+ }
+}
+
+/*!
+ \brief configure ADC inserted channel offset
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] inserted_channel: insert channel select
+ only one parameter can be selected
+ \arg ADC_INSERTED_CHANNEL_0: inserted channel0
+ \arg ADC_INSERTED_CHANNEL_1: inserted channel1
+ \arg ADC_INSERTED_CHANNEL_2: inserted channel2
+ \arg ADC_INSERTED_CHANNEL_3: inserted channel3
+ \param[in] offset: the offset data
+ \param[out] none
+ \retval none
+*/
+void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
+{
+ uint8_t inserted_length;
+ uint32_t num = 0U;
+
+ inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
+ num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
+
+ if(num <= ADC_OFFSET_LENGTH){
+ /* calculate the offset of the register */
+ num = num * ADC_OFFSET_SHIFT_LENGTH;
+ /* config the offset of the selected channels */
+ REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
+ }
+}
+
+/*!
+ \brief configure ADC external trigger source
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel_group: select the channel group
+ only one parameter can be selected which is shown as below:
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] external_trigger_source: regular or inserted group trigger source
+ only one parameter can be selected
+ for regular channel:
+ \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select
+ \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select
+ \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
+ \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select
+ \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select
+ \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select
+ \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select
+ \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
+ \arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select
+ \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select
+ \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
+ \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select
+ \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select
+ \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select
+ \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select
+ \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger
+ for inserted channel:
+ \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
+ \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
+ \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select
+ \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select
+ \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select
+ \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select
+ \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
+ \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select
+ \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
+ \arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
+ \arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select
+ \arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select
+ \arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select
+ \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select
+ \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select
+ \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger
+ \param[out] none
+ \retval none
+*/
+void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
+{
+ switch(adc_channel_group){
+ case ADC_REGULAR_CHANNEL:
+ /* configure ADC regular group external trigger source */
+ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
+ ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
+ break;
+ case ADC_INSERTED_CHANNEL:
+ /* configure ADC inserted group external trigger source */
+ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
+ ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure ADC external trigger
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel_group: select the channel group
+ one or more parameters can be selected which are shown as below:
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
+{
+ if(newvalue){
+ if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
+ /* enable ADC regular channel group external trigger */
+ ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
+ }
+ if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
+ /* enable ADC inserted channel group external trigger */
+ ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
+ }
+ }else{
+ if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
+ /* disable ADC regular channel group external trigger */
+ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
+ }
+ if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
+ /* disable ADC regular channel group external trigger */
+ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
+ }
+ }
+}
+
+/*!
+ \brief enable ADC software trigger
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel_group: select the channel group
+ one or more parameters can be selected which are shown as below:
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[out] none
+ \retval none
+*/
+void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
+{
+ if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
+ /* enable ADC regular channel group software trigger */
+ ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
+ }
+ if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
+ /* enable ADC inserted channel group software trigger */
+ ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
+ }
+}
+
+/*!
+ \brief read ADC regular group data register
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] none
+ \param[out] none
+ \retval the conversion value
+*/
+uint16_t adc_regular_data_read(uint32_t adc_periph)
+{
+ return (uint16_t)(ADC_RDATA(adc_periph));
+}
+
+/*!
+ \brief read ADC inserted group data register
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] inserted_channel: insert channel select
+ only one parameter can be selected
+ \arg ADC_INSERTED_CHANNEL_0: inserted Channel0
+ \arg ADC_INSERTED_CHANNEL_1: inserted channel1
+ \arg ADC_INSERTED_CHANNEL_2: inserted Channel2
+ \arg ADC_INSERTED_CHANNEL_3: inserted Channel3
+ \param[out] none
+ \retval the conversion value
+*/
+uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
+{
+ uint32_t idata;
+ /* read the data of the selected channel */
+ switch(inserted_channel){
+ case ADC_INSERTED_CHANNEL_0:
+ /* read the data of channel 0 */
+ idata = ADC_IDATA0(adc_periph);
+ break;
+ case ADC_INSERTED_CHANNEL_1:
+ /* read the data of channel 1 */
+ idata = ADC_IDATA1(adc_periph);
+ break;
+ case ADC_INSERTED_CHANNEL_2:
+ /* read the data of channel 2 */
+ idata = ADC_IDATA2(adc_periph);
+ break;
+ case ADC_INSERTED_CHANNEL_3:
+ /* read the data of channel 3 */
+ idata = ADC_IDATA3(adc_periph);
+ break;
+ default:
+ idata = 0U;
+ break;
+ }
+ return (uint16_t)idata;
+}
+
+/*!
+ \brief read the last ADC0 and ADC1 conversion result data in sync mode
+ \param[in] none
+ \param[out] none
+ \retval the conversion value
+*/
+uint32_t adc_sync_mode_convert_value_read(void)
+{
+ /* return conversion value */
+ return ADC_RDATA(ADC0);
+}
+
+
+/*!
+ \brief configure ADC analog watchdog single channel
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel: the selected ADC channel
+ only one parameter can be selected which is shown as below:
+ \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
+{
+ ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+ /* analog watchdog channel select */
+ ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
+ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+}
+
+/*!
+ \brief configure ADC analog watchdog group channel
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_channel_group: the channel group use analog watchdog
+ only one parameter can be selected which is shown as below:
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
+{
+ ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+ /* select the group */
+ switch(adc_channel_group){
+ case ADC_REGULAR_CHANNEL:
+ /* regular channel analog watchdog enable */
+ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
+ break;
+ case ADC_INSERTED_CHANNEL:
+ /* inserted channel analog watchdog enable */
+ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
+ break;
+ case ADC_REGULAR_INSERTED_CHANNEL:
+ /* regular and inserted channel analog watchdog enable */
+ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief disable ADC analog watchdog
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_disable(uint32_t adc_periph)
+{
+ ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+}
+
+/*!
+ \brief configure ADC analog watchdog threshold
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] low_threshold: analog watchdog low threshold, 0..4095
+ \param[in] high_threshold: analog watchdog high threshold, 0..4095
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
+{
+ ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
+ ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
+}
+
+/*!
+ \brief get the ADC flag bits
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_flag: the adc flag bits
+ only one parameter can be selected which is shown as below:
+ \arg ADC_FLAG_WDE: analog watchdog event flag
+ \arg ADC_FLAG_EOC: end of group conversion flag
+ \arg ADC_FLAG_EOIC: end of inserted group conversion flag
+ \arg ADC_FLAG_STIC: start flag of inserted channel group
+ \arg ADC_FLAG_STRC: start flag of regular channel group
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
+{
+ FlagStatus reval = RESET;
+ if(ADC_STAT(adc_periph) & adc_flag){
+ reval = SET;
+ }
+ return reval;
+}
+
+/*!
+ \brief clear the ADC flag bits
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_flag: the adc flag bits
+ one or more parameters can be selected which are shown as below:
+ \arg ADC_FLAG_WDE: analog watchdog event flag
+ \arg ADC_FLAG_EOC: end of group conversion flag
+ \arg ADC_FLAG_EOIC: end of inserted group conversion flag
+ \arg ADC_FLAG_STIC: start flag of inserted channel group
+ \arg ADC_FLAG_STRC: start flag of regular channel group
+ \param[out] none
+ \retval none
+*/
+void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
+{
+ ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
+}
+
+/*!
+ \brief get the bit state of ADCx software start conversion
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
+{
+ FlagStatus reval = RESET;
+ if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
+ reval = SET;
+ }
+ return reval;
+}
+
+/*!
+ \brief get the bit state of ADCx software inserted channel start conversion
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
+{
+ FlagStatus reval = RESET;
+ if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
+ reval = SET;
+ }
+ return reval;
+}
+
+/*!
+ \brief get the ADC interrupt bits
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_interrupt: the adc interrupt bits
+ only one parameter can be selected which is shown as below:
+ \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
+ \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
+ \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+ FlagStatus interrupt_flag = RESET;
+ uint32_t state;
+ /* check the interrupt bits */
+ switch(adc_interrupt){
+ case ADC_INT_FLAG_WDE:
+ /* get the ADC analog watchdog interrupt bits */
+ state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
+ if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
+ interrupt_flag = SET;
+ }
+ break;
+ case ADC_INT_FLAG_EOC:
+ /* get the ADC end of group conversion interrupt bits */
+ state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
+ if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
+ interrupt_flag = SET;
+ }
+ break;
+ case ADC_INT_FLAG_EOIC:
+ /* get the ADC end of inserted group conversion interrupt bits */
+ state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
+ if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
+ interrupt_flag = SET;
+ }
+ break;
+ default:
+ break;
+ }
+ return interrupt_flag;
+}
+
+/*!
+ \brief clear the ADC flag
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_interrupt: the adc status flag
+ one or more parameters can be selected which are shown as below:
+ \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
+ \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
+ \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
+ \param[out] none
+ \retval none
+*/
+void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+ ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
+}
+
+/*!
+ \brief enable ADC interrupt
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_interrupt: the adc interrupt
+ one or more parameters can be selected which are shown as below:
+ \arg ADC_INT_WDE: analog watchdog interrupt flag
+ \arg ADC_INT_EOC: end of group conversion interrupt flag
+ \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
+ \param[out] none
+ \retval none
+*/
+void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+ /* enable ADC analog watchdog interrupt */
+ if(0U != (adc_interrupt & ADC_INT_WDE)){
+ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
+ }
+ /* enable ADC end of group conversion interrupt */
+ if(0U != (adc_interrupt & ADC_INT_EOC)){
+ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
+ }
+ /* enable ADC end of inserted group conversion interrupt */
+ if(0U != (adc_interrupt & ADC_INT_EOIC)){
+ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
+ }
+}
+
+/*!
+ \brief disable ADC interrupt
+ \param[in] adc_periph: ADCx, x=0,1,2
+ \param[in] adc_interrupt: the adc interrupt flag
+ one or more parameters can be selected which are shown as below:
+ \arg ADC_INT_WDE: analog watchdog interrupt flag
+ \arg ADC_INT_EOC: end of group conversion interrupt flag
+ \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
+ \param[out] none
+ \retval none
+*/
+void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+ /* disable ADC analog watchdog interrupt */
+ if(0U != (adc_interrupt & ADC_INT_WDE)){
+ ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
+ }
+ /* disable ADC end of group conversion interrupt */
+ if(0U != (adc_interrupt & ADC_INT_EOC)){
+ ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
+ }
+ /* disable ADC end of inserted group conversion interrupt */
+ if(0U != (adc_interrupt & ADC_INT_EOIC)){
+ ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c
new file mode 100644
index 0000000..66d961d
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c
@@ -0,0 +1,292 @@
+/*!
+ \file gd32f10x_bkp.c
+ \brief BKP driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_bkp.h"
+
+/* BKP register bits offset */
+#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U)
+
+/*!
+ \brief reset BKP registers
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_deinit(void)
+{
+ /* reset BKP domain register*/
+ rcu_bkp_reset_enable();
+ rcu_bkp_reset_disable();
+}
+
+/*!
+ \brief write BKP data register
+ \param[in] register_number: refer to bkp_data_register_enum
+ only one parameter can be selected which is shown as below:
+ \arg BKP_DATA_x(x = 0..41): bkp data register number x
+ \param[in] data: the data to be write in BKP data register
+ \param[out] none
+ \retval none
+*/
+void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
+{
+ if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
+ BKP_DATA10_41(register_number - 1U) = data;
+ }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
+ BKP_DATA0_9(register_number - 1U) = data;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief read BKP data register
+ \param[in] register_number: refer to bkp_data_register_enum
+ only one parameter can be selected which is shown as below:
+ \arg BKP_DATA_x(x = 0..41): bkp data register number x
+ \param[out] none
+ \retval data of BKP data register
+*/
+uint16_t bkp_data_read(bkp_data_register_enum register_number)
+{
+ uint16_t data = 0U;
+
+ /* get the data from the BKP data register */
+ if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
+ data = BKP_DATA10_41(register_number - 1U);
+ }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
+ data = BKP_DATA0_9(register_number - 1U);
+ }else{
+ /* illegal parameters */
+ }
+ return data;
+}
+
+/*!
+ \brief enable RTC clock calibration output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_rtc_calibration_output_enable(void)
+{
+ BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
+}
+
+/*!
+ \brief disable RTC clock calibration output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_rtc_calibration_output_disable(void)
+{
+ BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
+}
+
+/*!
+ \brief enable RTC alarm or second signal output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_rtc_signal_output_enable(void)
+{
+ BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
+}
+
+/*!
+ \brief disable RTC alarm or second signal output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_rtc_signal_output_disable(void)
+{
+ BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
+}
+
+/*!
+ \brief select RTC output
+ \param[in] outputsel: RTC output selection
+ only one parameter can be selected which is shown as below:
+ \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
+ \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
+ \param[out] none
+ \retval none
+*/
+void bkp_rtc_output_select(uint16_t outputsel)
+{
+ uint16_t ctl = 0U;
+
+ /* configure BKP_OCTL_ROSEL with outputsel */
+ ctl = BKP_OCTL;
+ ctl &= (uint16_t)~BKP_OCTL_ROSEL;
+ ctl |= outputsel;
+ BKP_OCTL = ctl;
+}
+
+/*!
+ \brief set RTC clock calibration value
+ \param[in] value: RTC clock calibration value
+ \arg 0x00 - 0x7F
+ \param[out] none
+ \retval none
+*/
+void bkp_rtc_calibration_value_set(uint8_t value)
+{
+ uint16_t ctl;
+
+ /* configure BKP_OCTL_RCCV with value */
+ ctl = BKP_OCTL;
+ ctl &= (uint16_t)~BKP_OCTL_RCCV;
+ ctl |= (uint16_t)OCTL_RCCV(value);
+ BKP_OCTL = ctl;
+}
+
+/*!
+ \brief enable tamper detection
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_tamper_detection_enable(void)
+{
+ BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
+}
+
+/*!
+ \brief disable tamper detection
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_tamper_detection_disable(void)
+{
+ BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
+}
+
+/*!
+ \brief set tamper pin active level
+ \param[in] level: tamper active level
+ only one parameter can be selected which is shown as below:
+ \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
+ \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
+ \param[out] none
+ \retval none
+*/
+void bkp_tamper_active_level_set(uint16_t level)
+{
+ uint16_t ctl = 0U;
+
+ /* configure BKP_TPCTL_TPAL with level */
+ ctl = BKP_TPCTL;
+ ctl &= (uint16_t)~BKP_TPCTL_TPAL;
+ ctl |= level;
+ BKP_TPCTL = ctl;
+}
+
+/*!
+ \brief enable tamper interrupt
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_interrupt_enable(void)
+{
+ BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
+}
+
+/*!
+ \brief disable tamper interrupt
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_interrupt_disable(void)
+{
+ BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
+}
+
+/*!
+ \brief get tamper flag state
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus bkp_flag_get(void)
+{
+ if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear tamper flag state
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_flag_clear(void)
+{
+ BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
+}
+
+/*!
+ \brief get tamper interrupt flag state
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus bkp_interrupt_flag_get(void)
+{
+ if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear tamper interrupt flag state
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void bkp_interrupt_flag_clear(void)
+{
+ BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_can.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_can.c
new file mode 100644
index 0000000..eea114f
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_can.c
@@ -0,0 +1,1048 @@
+/*!
+ \file gd32f10x_can.c
+ \brief CAN driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_can.h"
+
+#define CAN_ERROR_HANDLE(s) do{}while(1)
+
+#define RFO1_CLEAR_VAL ((uint32_t)0x00000000U) /*!< RFO1 clear value */
+#define RFF1_CLEAR_VAL ((uint32_t)0x00000018U) /*!< RFF1 clear value */
+
+/*!
+ \brief deinitialize CAN
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval none
+*/
+void can_deinit(uint32_t can_periph)
+{
+#ifdef GD32F10x_CL
+ if(CAN0 == can_periph){
+ rcu_periph_reset_enable(RCU_CAN0RST);
+ rcu_periph_reset_disable(RCU_CAN0RST);
+ }else{
+ rcu_periph_reset_enable(RCU_CAN1RST);
+ rcu_periph_reset_disable(RCU_CAN1RST);
+ }
+#else
+ if(CAN0 == can_periph){
+ rcu_periph_reset_enable(RCU_CAN0RST);
+ rcu_periph_reset_disable(RCU_CAN0RST);
+ }
+#endif
+}
+
+/*!
+ \brief initialize CAN parameter struct with a default value
+ \param[in] type: the type of CAN parameter struct
+ only one parameter can be selected which is shown as below:
+ \arg CAN_INIT_STRUCT: the CAN initial struct
+ \arg CAN_FILTER_STRUCT: the CAN filter struct
+ \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct
+ \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct
+ \param[in] p_struct: the pointer of the specific struct
+ \param[out] none
+ \retval none
+*/
+void can_struct_para_init(can_struct_type_enum type, void* p_struct)
+{
+ uint8_t i;
+
+ /* get type of the struct */
+ switch(type){
+ /* used for can_init() */
+ case CAN_INIT_STRUCT:
+ ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE;
+ ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE;
+ ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE;
+ ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU;
+ ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE;
+ ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ;
+ ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ;
+ ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ;
+ ((can_parameter_struct*)p_struct)->time_triggered = DISABLE;
+ ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE;
+ ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE;
+
+ break;
+ /* used for can_filter_init() */
+ case CAN_FILTER_STRUCT:
+ ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT;
+ ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE;
+ ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0;
+ ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U;
+ ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U;
+ ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U;
+ ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U;
+ ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK;
+ ((can_filter_parameter_struct*)p_struct)->filter_number = 0U;
+
+ break;
+ /* used for can_message_transmit() */
+ case CAN_TX_MESSAGE_STRUCT:
+ for(i = 0U; i < 8U; i++){
+ ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U;
+ }
+
+ ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u;
+ ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U;
+ ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD;
+ ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA;
+ ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U;
+
+ break;
+ /* used for can_message_receive() */
+ case CAN_RX_MESSAGE_STRUCT:
+ for(i = 0U; i < 8U; i++){
+ ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U;
+ }
+
+ ((can_receive_message_struct*)p_struct)->rx_dlen = 0U;
+ ((can_receive_message_struct*)p_struct)->rx_efid = 0U;
+ ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD;
+ ((can_receive_message_struct*)p_struct)->rx_fi = 0U;
+ ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA;
+ ((can_receive_message_struct*)p_struct)->rx_sfid = 0U;
+
+ break;
+
+ default:
+ CAN_ERROR_HANDLE("parameter is invalid \r\n");
+ }
+}
+
+/*!
+ \brief initialize CAN
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] can_parameter_init: parameters for CAN initializtion
+ \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE
+ \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4)
+ \arg time_segment_1: CAN_BT_BS1_xTQ(1..16)
+ \arg time_segment_2: CAN_BT_BS2_xTQ(1..8)
+ \arg time_triggered: ENABLE or DISABLE
+ \arg auto_bus_off_recovery: ENABLE or DISABLE
+ \arg auto_wake_up: ENABLE or DISABLE
+ \arg auto_retrans: ENABLE or DISABLE
+ \arg rec_fifo_overwrite: ENABLE or DISABLE
+ \arg trans_fifo_order: ENABLE or DISABLE
+ \arg prescaler: 0x0001 - 0x0400
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init)
+{
+ uint32_t timeout = CAN_TIMEOUT;
+ ErrStatus flag = ERROR;
+
+ /* disable sleep mode */
+ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
+ /* enable initialize mode */
+ CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
+ /* wait ACK */
+ while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
+ timeout--;
+ }
+ /* check initialize working success */
+ if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
+ flag = ERROR;
+ }else{
+ /* set the bit timing register */
+ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
+ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
+ BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
+ BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
+ BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
+
+ /* time trigger communication mode */
+ if(ENABLE == can_parameter_init->time_triggered){
+ CAN_CTL(can_periph) |= CAN_CTL_TTC;
+ }else{
+ CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
+ }
+ /* automatic bus-off managment */
+ if(ENABLE == can_parameter_init->auto_bus_off_recovery){
+ CAN_CTL(can_periph) |= CAN_CTL_ABOR;
+ }else{
+ CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
+ }
+ /* automatic wakeup mode */
+ if(ENABLE == can_parameter_init->auto_wake_up){
+ CAN_CTL(can_periph) |= CAN_CTL_AWU;
+ }else{
+ CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
+ }
+ /* automatic retransmission mode */
+ if(ENABLE == can_parameter_init->auto_retrans){
+ CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
+ }else{
+ CAN_CTL(can_periph) |= CAN_CTL_ARD;
+ }
+ /* receive fifo overwrite mode */
+ if(ENABLE == can_parameter_init->rec_fifo_overwrite){
+ CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
+ }else{
+ CAN_CTL(can_periph) |= CAN_CTL_RFOD;
+ }
+ /* transmit fifo order */
+ if(ENABLE == can_parameter_init->trans_fifo_order){
+ CAN_CTL(can_periph) |= CAN_CTL_TFO;
+ }else{
+ CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
+ }
+ /* disable initialize mode */
+ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
+ timeout = CAN_TIMEOUT;
+ /* wait the ACK */
+ while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
+ timeout--;
+ }
+ /* check exit initialize mode */
+ if(0U != timeout){
+ flag = SUCCESS;
+ }
+ }
+ return flag;
+}
+
+/*!
+ \brief initialize CAN filter
+ \param[in] can_filter_parameter_init: struct for CAN filter initialization
+ \arg filter_list_high: 0x0000 - 0xFFFF
+ \arg filter_list_low: 0x0000 - 0xFFFF
+ \arg filter_mask_high: 0x0000 - 0xFFFF
+ \arg filter_mask_low: 0x0000 - 0xFFFF
+ \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1
+ \arg filter_number: 0 - 27
+ \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST
+ \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT
+ \arg filter_enable: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
+{
+ uint32_t val = 0U;
+
+ val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
+ /* filter lock disable */
+ CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
+ /* disable filter */
+ CAN_FW(CAN0) &= ~(uint32_t)val;
+
+ /* filter 16 bits */
+ if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
+ /* set filter 16 bits */
+ CAN_FSCFG(CAN0) &= ~(uint32_t)val;
+ /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
+ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
+ FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
+ FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
+ /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
+ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
+ FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
+ FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
+ }
+ /* filter 32 bits */
+ if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
+ /* set filter 32 bits */
+ CAN_FSCFG(CAN0) |= (uint32_t)val;
+ /* 32 bits list or first 32 bits list */
+ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
+ FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
+ FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
+ /* 32 bits mask or second 32 bits list */
+ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
+ FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
+ FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
+ }
+
+ /* filter mode */
+ if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
+ /* mask mode */
+ CAN_FMCFG(CAN0) &= ~(uint32_t)val;
+ }else{
+ /* list mode */
+ CAN_FMCFG(CAN0) |= (uint32_t)val;
+ }
+
+ /* filter FIFO */
+ if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
+ /* FIFO0 */
+ CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
+ }else{
+ /* FIFO1 */
+ CAN_FAFIFO(CAN0) |= (uint32_t)val;
+ }
+
+ /* filter working */
+ if(ENABLE == can_filter_parameter_init->filter_enable){
+
+ CAN_FW(CAN0) |= (uint32_t)val;
+ }
+
+ /* filter lock enable */
+ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
+}
+
+/*!
+ \brief set CAN1 fliter start bank number
+ \param[in] start_bank: CAN1 start bank number
+ only one parameter can be selected which is shown as below:
+ \arg (1..27)
+ \param[out] none
+ \retval none
+*/
+void can1_filter_start_bank(uint8_t start_bank)
+{
+ /* filter lock disable */
+ CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
+ /* set CAN1 filter start number */
+ CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
+ CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
+ /* filter lock enaable */
+ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
+}
+
+/*!
+ \brief enable CAN debug freeze
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval none
+*/
+void can_debug_freeze_enable(uint32_t can_periph)
+{
+ /* set DFZ bit */
+ CAN_CTL(can_periph) |= CAN_CTL_DFZ;
+#ifdef GD32F10x_CL
+ if(CAN0 == can_periph){
+ dbg_periph_enable(DBG_CAN0_HOLD);
+ }else{
+ dbg_periph_enable(DBG_CAN1_HOLD);
+ }
+#else
+ if(CAN0 == can_periph){
+ dbg_periph_enable(DBG_CAN0_HOLD);
+ }
+#endif
+}
+
+/*!
+ \brief disable CAN debug freeze
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval none
+*/
+void can_debug_freeze_disable(uint32_t can_periph)
+{
+ /* set DFZ bit */
+ CAN_CTL(can_periph) &= ~CAN_CTL_DFZ;
+#ifdef GD32F10x_CL
+ if(CAN0 == can_periph){
+ dbg_periph_disable(DBG_CAN0_HOLD);
+ }else{
+ dbg_periph_disable(DBG_CAN1_HOLD);
+ }
+#else
+ if(CAN0 == can_periph){
+ dbg_periph_enable(DBG_CAN0_HOLD);
+ }
+#endif
+}
+
+/*!
+ \brief enable CAN time trigger mode
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval none
+*/
+void can_time_trigger_mode_enable(uint32_t can_periph)
+{
+ uint8_t mailbox_number;
+
+ /* enable the tcc mode */
+ CAN_CTL(can_periph) |= CAN_CTL_TTC;
+ /* enable time stamp */
+ for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){
+ CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
+ }
+}
+
+/*!
+ \brief disable CAN time trigger mode
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval none
+*/
+void can_time_trigger_mode_disable(uint32_t can_periph)
+{
+ uint8_t mailbox_number;
+
+ /* disable the TCC mode */
+ CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
+ /* reset TSEN bits */
+ for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){
+ CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
+ }
+}
+
+/*!
+ \brief transmit CAN message
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] transmit_message: struct for CAN transmit message
+ \arg tx_sfid: 0x00000000 - 0x000007FF
+ \arg tx_efid: 0x00000000 - 0x1FFFFFFF
+ \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
+ \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE
+ \arg tx_dlen: 0 - 8
+ \arg tx_data[]: 0x00 - 0xFF
+ \param[out] none
+ \retval mailbox_number
+*/
+uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message)
+{
+ uint8_t mailbox_number = CAN_MAILBOX0;
+
+ /* select one empty mailbox */
+ if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
+ mailbox_number = CAN_MAILBOX0;
+ }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
+ mailbox_number = CAN_MAILBOX1;
+ }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
+ mailbox_number = CAN_MAILBOX2;
+ }else{
+ mailbox_number = CAN_NOMAILBOX;
+ }
+ /* return no mailbox empty */
+ if(CAN_NOMAILBOX == mailbox_number){
+ return CAN_NOMAILBOX;
+ }
+
+ CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
+ if(CAN_FF_STANDARD == transmit_message->tx_ff){
+ /* set transmit mailbox standard identifier */
+ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
+ transmit_message->tx_ft);
+ }else{
+ /* set transmit mailbox extended identifier */
+ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
+ transmit_message->tx_ff | \
+ transmit_message->tx_ft);
+ }
+ /* set the data length */
+ CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC;
+ CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
+ /* set the data */
+ CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
+ TMDATA0_DB2(transmit_message->tx_data[2]) | \
+ TMDATA0_DB1(transmit_message->tx_data[1]) | \
+ TMDATA0_DB0(transmit_message->tx_data[0]);
+ CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
+ TMDATA1_DB6(transmit_message->tx_data[6]) | \
+ TMDATA1_DB5(transmit_message->tx_data[5]) | \
+ TMDATA1_DB4(transmit_message->tx_data[4]);
+ /* enable transmission */
+ CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
+
+ return mailbox_number;
+}
+
+/*!
+ \brief get CAN transmit state
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] mailbox_number
+ only one parameter can be selected which is shown as below:
+ \arg CAN_MAILBOX(x=0,1,2)
+ \param[out] none
+ \retval can_transmit_state_enum
+*/
+can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
+{
+ can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
+ uint32_t val = 0U;
+
+ /* check selected mailbox state */
+ switch(mailbox_number){
+ /* mailbox0 */
+ case CAN_MAILBOX0:
+ val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
+ break;
+ /* mailbox1 */
+ case CAN_MAILBOX1:
+ val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
+ break;
+ /* mailbox2 */
+ case CAN_MAILBOX2:
+ val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
+ break;
+ default:
+ val = CAN_TRANSMIT_FAILED;
+ break;
+ }
+
+ switch(val){
+ /* transmit pending */
+ case (CAN_STATE_PENDING):
+ state = CAN_TRANSMIT_PENDING;
+ break;
+ /* mailbox0 transmit succeeded */
+ case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
+ state = CAN_TRANSMIT_OK;
+ break;
+ /* mailbox1 transmit succeeded */
+ case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
+ state = CAN_TRANSMIT_OK;
+ break;
+ /* mailbox2 transmit succeeded */
+ case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
+ state = CAN_TRANSMIT_OK;
+ break;
+ /* transmit failed */
+ default:
+ state = CAN_TRANSMIT_FAILED;
+ break;
+ }
+ return state;
+}
+
+/*!
+ \brief stop CAN transmission
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] mailbox_number
+ only one parameter can be selected which is shown as below:
+ \arg CAN_MAILBOXx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
+{
+ if(CAN_MAILBOX0 == mailbox_number){
+ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
+ while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){
+ }
+ }else if(CAN_MAILBOX1 == mailbox_number){
+ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
+ while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){
+ }
+ }else if(CAN_MAILBOX2 == mailbox_number){
+ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
+ while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){
+ }
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief CAN receive message
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] fifo_number
+ \arg CAN_FIFOx(x=0,1)
+ \param[out] receive_message: struct for CAN receive message
+ \arg rx_sfid: 0x00000000 - 0x000007FF
+ \arg rx_efid: 0x00000000 - 0x1FFFFFFF
+ \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
+ \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE
+ \arg rx_dlen: 0 - 8
+ \arg rx_data[]: 0x00 - 0xFF
+ \arg rx_fi: 0 - 27
+ \retval none
+*/
+void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message)
+{
+ /* get the frame format */
+ receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
+ if(CAN_FF_STANDARD == receive_message->rx_ff){
+ /* get standard identifier */
+ receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
+ }else{
+ /* get extended identifier */
+ receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
+ }
+
+ /* get frame type */
+ receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));
+ /* filtering index */
+ receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
+ /* get recevie data length */
+ receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
+
+ /* receive data */
+ receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+ receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+ receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+ receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+ receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+ receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+ receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+ receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+
+ /* release FIFO */
+ if(CAN_FIFO0 == fifo_number){
+ CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
+ }else{
+ CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
+ }
+}
+
+/*!
+ \brief release FIFO0
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] fifo_number
+ only one parameter can be selected which is shown as below:
+ \arg CAN_FIFOx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
+{
+ if(CAN_FIFO0 == fifo_number){
+ CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
+ }else if(CAN_FIFO1 == fifo_number){
+ CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
+ }else{
+ /* illegal parameters */
+ CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n");
+ }
+}
+
+/*!
+ \brief CAN receive message length
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] fifo_number
+ only one parameter can be selected which is shown as below:
+ \arg CAN_FIFOx(x=0,1)
+ \param[out] none
+ \retval message length
+*/
+uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
+{
+ uint8_t val = 0U;
+
+ if(CAN_FIFO0 == fifo_number){
+ /* FIFO0 */
+ val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
+ }else if(CAN_FIFO1 == fifo_number){
+ /* FIFO1 */
+ val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
+ }else{
+ /* illegal parameters */
+ }
+ return val;
+}
+
+/*!
+ \brief set CAN working mode
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] can_working_mode
+ only one parameter can be selected which is shown as below:
+ \arg CAN_MODE_INITIALIZE
+ \arg CAN_MODE_NORMAL
+ \arg CAN_MODE_SLEEP
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
+{
+ ErrStatus flag = ERROR;
+ /* timeout for IWS or also for SLPWS bits */
+ uint32_t timeout = CAN_TIMEOUT;
+
+ if(CAN_MODE_INITIALIZE == working_mode){
+ /* disable sleep mode */
+ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
+ /* set initialize mode */
+ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
+ /* wait the acknowledge */
+ while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
+ timeout--;
+ }
+ if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
+ flag = ERROR;
+ }else{
+ flag = SUCCESS;
+ }
+ }else if(CAN_MODE_NORMAL == working_mode){
+ /* enter normal mode */
+ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
+ /* wait the acknowledge */
+ while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
+ timeout--;
+ }
+ if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
+ flag = ERROR;
+ }else{
+ flag = SUCCESS;
+ }
+ }else if(CAN_MODE_SLEEP == working_mode){
+ /* disable initialize mode */
+ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
+ /* set sleep mode */
+ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
+ /* wait the acknowledge */
+ while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
+ timeout--;
+ }
+ if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
+ flag = ERROR;
+ }else{
+ flag = SUCCESS;
+ }
+ }else{
+ flag = ERROR;
+ }
+ return flag;
+}
+
+/*!
+ \brief wake up CAN
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus can_wakeup(uint32_t can_periph)
+{
+ ErrStatus flag = ERROR;
+ uint32_t timeout = CAN_TIMEOUT;
+
+ /* wakeup */
+ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
+
+ while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
+ timeout--;
+ }
+ /* check state */
+ if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
+ flag = ERROR;
+ }else{
+ flag = SUCCESS;
+ }
+ return flag;
+}
+
+/*!
+ \brief get CAN error type
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval can_error_enum
+ \arg CAN_ERROR_NONE: no error
+ \arg CAN_ERROR_FILL: fill error
+ \arg CAN_ERROR_FORMATE: format error
+ \arg CAN_ERROR_ACK: ACK error
+ \arg CAN_ERROR_BITRECESSIVE: bit recessive
+ \arg CAN_ERROR_BITDOMINANTER: bit dominant error
+ \arg CAN_ERROR_CRC: CRC error
+ \arg CAN_ERROR_SOFTWARECFG: software configure
+*/
+can_error_enum can_error_get(uint32_t can_periph)
+{
+ can_error_enum error;
+ error = CAN_ERROR_NONE;
+
+ /* get error type */
+ error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph)));
+ return error;
+}
+
+/*!
+ \brief get CAN receive error number
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval error number
+*/
+uint8_t can_receive_error_number_get(uint32_t can_periph)
+{
+ uint8_t val;
+
+ /* get error count */
+ val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph)));
+ return val;
+}
+
+/*!
+ \brief get CAN transmit error number
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[out] none
+ \retval error number
+*/
+uint8_t can_transmit_error_number_get(uint32_t can_periph)
+{
+ uint8_t val;
+
+ val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph)));
+ return val;
+}
+
+/*!
+ \brief enable CAN interrupt
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] interrupt
+ one or more parameters can be selected which are shown as below:
+ \arg CAN_INT_TME: transmit mailbox empty interrupt enable
+ \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
+ \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable
+ \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
+ \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
+ \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable
+ \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
+ \arg CAN_INT_WERR: warning error interrupt enable
+ \arg CAN_INT_PERR: passive error interrupt enable
+ \arg CAN_INT_BO: bus-off interrupt enable
+ \arg CAN_INT_ERRN: error number interrupt enable
+ \arg CAN_INT_ERR: error interrupt enable
+ \arg CAN_INT_WAKEUP: wakeup interrupt enable
+ \arg CAN_INT_SLPW: sleep working interrupt enable
+ \param[out] none
+ \retval none
+*/
+void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
+{
+ CAN_INTEN(can_periph) |= interrupt;
+}
+
+/*!
+ \brief disable CAN interrupt
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] interrupt
+ one or more parameters can be selected which are shown as below:
+ \arg CAN_INT_TME: transmit mailbox empty interrupt enable
+ \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
+ \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable
+ \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
+ \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
+ \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable
+ \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
+ \arg CAN_INT_WERR: warning error interrupt enable
+ \arg CAN_INT_PERR: passive error interrupt enable
+ \arg CAN_INT_BO: bus-off interrupt enable
+ \arg CAN_INT_ERRN: error number interrupt enable
+ \arg CAN_INT_ERR: error interrupt enable
+ \arg CAN_INT_WAKEUP: wakeup interrupt enable
+ \arg CAN_INT_SLPW: sleep working interrupt enable
+ \param[out] none
+ \retval none
+*/
+void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
+{
+ CAN_INTEN(can_periph) &= ~interrupt;
+}
+
+/*!
+ \brief get CAN flag state
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] flag: CAN flags, refer to can_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg CAN_FLAG_RXL: RX level
+ \arg CAN_FLAG_LASTRX: last sample value of RX pin
+ \arg CAN_FLAG_RS: receiving state
+ \arg CAN_FLAG_TS: transmitting state
+ \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode
+ \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode
+ \arg CAN_FLAG_ERRIF: error flag
+ \arg CAN_FLAG_SLPWS: sleep working state
+ \arg CAN_FLAG_IWS: initial working state
+ \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO
+ \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO
+ \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO
+ \arg CAN_FLAG_TME2: transmit mailbox 2 empty
+ \arg CAN_FLAG_TME1: transmit mailbox 1 empty
+ \arg CAN_FLAG_TME0: transmit mailbox 0 empty
+ \arg CAN_FLAG_MTE2: mailbox 2 transmit error
+ \arg CAN_FLAG_MTE1: mailbox 1 transmit error
+ \arg CAN_FLAG_MTE0: mailbox 0 transmit error
+ \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost
+ \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost
+ \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost
+ \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error
+ \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error
+ \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error
+ \arg CAN_FLAG_MTF2: mailbox 2 transmit finished
+ \arg CAN_FLAG_MTF1: mailbox 1 transmit finished
+ \arg CAN_FLAG_MTF0: mailbox 0 transmit finished
+ \arg CAN_FLAG_RFO0: receive FIFO0 overfull
+ \arg CAN_FLAG_RFF0: receive FIFO0 full
+ \arg CAN_FLAG_RFO1: receive FIFO1 overfull
+ \arg CAN_FLAG_RFF1: receive FIFO1 full
+ \arg CAN_FLAG_BOERR: bus-off error
+ \arg CAN_FLAG_PERR: passive error
+ \arg CAN_FLAG_WERR: warning error
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
+{
+ /* get flag and interrupt enable state */
+ if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear CAN flag state
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] flag: CAN flags, refer to can_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode
+ \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode
+ \arg CAN_FLAG_ERRIF: error flag
+ \arg CAN_FLAG_MTE2: mailbox 2 transmit error
+ \arg CAN_FLAG_MTE1: mailbox 1 transmit error
+ \arg CAN_FLAG_MTE0: mailbox 0 transmit error
+ \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost
+ \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost
+ \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost
+ \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error
+ \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error
+ \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error
+ \arg CAN_FLAG_MTF2: mailbox 2 transmit finished
+ \arg CAN_FLAG_MTF1: mailbox 1 transmit finished
+ \arg CAN_FLAG_MTF0: mailbox 0 transmit finished
+ \arg CAN_FLAG_RFO0: receive FIFO0 overfull
+ \arg CAN_FLAG_RFF0: receive FIFO0 full
+ \arg CAN_FLAG_RFO1: receive FIFO1 overfull
+ \arg CAN_FLAG_RFF1: receive FIFO1 full
+ \param[out] none
+ \retval none
+*/
+void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
+{
+ if (flag == CAN_FLAG_RFO1){
+ CAN_REG_VAL(can_periph, flag) = RFO1_CLEAR_VAL;
+ } else if (flag == CAN_FLAG_RFF1){
+ CAN_REG_VAL(can_periph, flag) = RFF1_CLEAR_VAL;
+ } else {
+ CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
+ }
+}
+
+/*!
+ \brief get CAN interrupt flag state
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
+ \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
+ \arg CAN_INT_FLAG_ERRIF: error interrupt flag
+ \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
+ \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
+ \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
+ \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
+ \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
+ \arg CAN_INT_FLAG_RFL0: receive FIFO0 not empty interrupt flag
+ \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
+ \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
+ \arg CAN_INT_FLAG_RFL1: receive FIFO1 not empty interrupt flag
+ \arg CAN_INT_FLAG_ERRN: error number interrupt flag
+ \arg CAN_INT_FLAG_BOERR: bus-off error interrupt flag
+ \arg CAN_INT_FLAG_PERR: passive error interrupt flag
+ \arg CAN_INT_FLAG_WERR: warning error interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
+{
+ uint32_t ret1 = RESET;
+ uint32_t ret2 = RESET;
+
+ /* get the staus of interrupt flag */
+ if (flag == CAN_INT_FLAG_RFL0) {
+ ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0);
+ } else if (flag == CAN_INT_FLAG_RFL1) {
+ ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1);
+ } else if (flag == CAN_INT_FLAG_ERRN) {
+ ret1 = can_error_get(can_periph);
+ } else {
+ ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag));
+ }
+ /* get the staus of interrupt enale bit */
+ ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag));
+ if(ret1 && ret2){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear CAN interrupt flag state
+ \param[in] can_periph
+ \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL
+ \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
+ \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
+ \arg CAN_INT_FLAG_ERRIF: error interrupt flag
+ \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
+ \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
+ \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
+ \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
+ \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
+ \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
+ \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
+ \param[out] none
+ \retval none
+*/
+void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
+{
+ if (flag == CAN_INT_FLAG_RFO1){
+ CAN_REG_VALS(can_periph, flag) = RFO1_CLEAR_VAL;
+ } else if (flag == CAN_INT_FLAG_RFF1){
+ CAN_REG_VALS(can_periph, flag) = RFF1_CLEAR_VAL;
+ } else {
+ CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag));
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c
new file mode 100644
index 0000000..17fe26d
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c
@@ -0,0 +1,127 @@
+/*!
+ \file gd32f10x_crc.c
+ \brief CRC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_crc.h"
+
+#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
+#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
+
+/*!
+ \brief deinit CRC calculation unit
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void crc_deinit(void)
+{
+ CRC_DATA = CRC_DATA_RESET_VALUE;
+ CRC_FDATA = CRC_FDATA_RESET_VALUE;
+ CRC_CTL = (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+ \brief reset data register to the value of initializaiton data register
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void crc_data_register_reset(void)
+{
+ CRC_CTL |= (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+ \brief read the value of the data register
+ \param[in] none
+ \param[out] none
+ \retval 32-bit value of the data register
+*/
+uint32_t crc_data_register_read(void)
+{
+ uint32_t data;
+ data = CRC_DATA;
+ return (data);
+}
+
+/*!
+ \brief read the value of the free data register
+ \param[in] none
+ \param[out] none
+ \retval 8-bit value of the free data register
+*/
+uint8_t crc_free_data_register_read(void)
+{
+ uint8_t fdata;
+ fdata = (uint8_t)CRC_FDATA;
+ return (fdata);
+}
+
+/*!
+ \brief write data to the free data register
+ \param[in] free_data: specify 8-bit data
+ \param[out] none
+ \retval none
+*/
+void crc_free_data_register_write(uint8_t free_data)
+{
+ CRC_FDATA = (uint32_t)free_data;
+}
+
+/*!
+ \brief calculate the CRC value of a 32-bit data
+ \param[in] sdata: specified 32-bit data
+ \param[out] none
+ \retval 32-bit value calculated by CRC
+*/
+uint32_t crc_single_data_calculate(uint32_t sdata)
+{
+ CRC_DATA = sdata;
+ return (CRC_DATA);
+}
+
+/*!
+ \brief calculate the CRC value of an array of 32-bit values
+ \param[in] array: pointer to an array of 32-bit values
+ \param[in] size: size of the array
+ \param[out] none
+ \retval 32-bit value calculated by CRC
+*/
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
+{
+ uint32_t index;
+ for(index = 0U; index < size; index++){
+ CRC_DATA = array[index];
+ }
+ return (CRC_DATA);
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c
new file mode 100644
index 0000000..b636d54
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c
@@ -0,0 +1,540 @@
+/*!
+ \file gd32f10x_dac.c
+ \brief DAC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_dac.h"
+
+/* DAC register bit offset */
+#define OUT1_REG_OFFSET ((uint32_t)0x00000010U)
+#define DH_12BIT_OFFSET ((uint32_t)0x00000010U)
+#define DH_8BIT_OFFSET ((uint32_t)0x00000008U)
+
+/*!
+ \brief deinitialize DAC
+ \param[in] dac_periph: DACx(x=0)
+ \param[out] none
+ \retval none
+*/
+void dac_deinit(uint32_t dac_periph)
+{
+ switch(dac_periph){
+ case DAC0:
+ /* reset DAC0 */
+ rcu_periph_reset_enable(RCU_DACRST);
+ rcu_periph_reset_disable(RCU_DACRST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief enable DAC
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_enable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0;
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief disable DAC
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_disable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0);
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief enable DAC DMA function
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0;
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief disable DAC DMA function
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0);
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief enable DAC output buffer
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DBOFF0);
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DBOFF1);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief disable DAC output buffer
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DBOFF0;
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DBOFF1;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief get DAC output value
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval DAC output data: 0~4095
+*/
+uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
+{
+ uint16_t data = 0U;
+
+ if(DAC_OUT0 == dac_out){
+ /* store the DACx_OUT0 output value */
+ data = (uint16_t)DAC_OUT0_DO(dac_periph);
+ }else if(DAC_OUT1 == dac_out){
+ /* store the DACx_OUT1 output value */
+ data = (uint16_t)DAC_OUT1_DO(dac_periph);
+ }else{
+ /* illegal parameters */
+ }
+
+ return data;
+}
+
+/*!
+ \brief set DAC data holding register value
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[in] dac_align: DAC data alignment mode
+ only one parameter can be selected which is shown as below:
+ \arg DAC_ALIGN_12B_R: 12-bit right-aligned data
+ \arg DAC_ALIGN_12B_L: 12-bit left-aligned data
+ \arg DAC_ALIGN_8B_R: 8-bit right-aligned data
+ \param[in] data: data to be loaded(0~4095)
+ \param[out] none
+ \retval none
+*/
+void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data)
+{
+ /* DAC_OUT0 data alignment */
+ if(DAC_OUT0 == dac_out){
+ switch(dac_align){
+ /* 12-bit right-aligned data */
+ case DAC_ALIGN_12B_R:
+ DAC_OUT0_R12DH(dac_periph) = data;
+ break;
+ /* 12-bit left-aligned data */
+ case DAC_ALIGN_12B_L:
+ DAC_OUT0_L12DH(dac_periph) = data;
+ break;
+ /* 8-bit right-aligned data */
+ case DAC_ALIGN_8B_R:
+ DAC_OUT0_R8DH(dac_periph) = data;
+ break;
+ default:
+ break;
+ }
+ }else if(DAC_OUT1 == dac_out){
+ /* DAC_OUT1 data alignment */
+ switch(dac_align){
+ /* 12-bit right-aligned data */
+ case DAC_ALIGN_12B_R:
+ DAC_OUT1_R12DH(dac_periph) = data;
+ break;
+ /* 12-bit left-aligned data */
+ case DAC_ALIGN_12B_L:
+ DAC_OUT1_L12DH(dac_periph) = data;
+ break;
+ /* 8-bit right-aligned data */
+ case DAC_ALIGN_8B_R:
+ DAC_OUT1_R8DH(dac_periph) = data;
+ break;
+ default:
+ break;
+ }
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief enable DAC trigger
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0;
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief disable DAC trigger
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0);
+ }else if(DAC_OUT1 == dac_out){
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure DAC trigger source
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[in] triggersource: external trigger of DAC
+ only one parameter can be selected which is shown as below:
+ \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
+ \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO, only for GD32F10X_CL devices
+ \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO, only for GD32F10X_MD, GD32F10X_HD, GD32F10X_XD devices
+ \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
+ \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
+ \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
+ \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
+ \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
+ \arg DAC_TRIGGER_SOFTWARE: software trigger
+ \param[out] none
+ \retval none
+*/
+void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource)
+{
+ if(DAC_OUT0 == dac_out){
+ /* configure DACx_OUT0 trigger source */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~(DAC_CTL0_DTSEL0));
+ DAC_CTL0(dac_periph) |= triggersource;
+ }else if(DAC_OUT1 == dac_out){
+ /* configure DACx_OUT1 trigger source */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~(DAC_CTL0_DTSEL1));
+ DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief enable DAC software trigger
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \retval none
+*/
+void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
+{
+ if(DAC_OUT0 == dac_out){
+ DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0;
+ }else if(DAC_OUT1 == dac_out){
+ DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure DAC wave mode
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[in] wave_mode: DAC wave mode
+ only one parameter can be selected which is shown as below:
+ \arg DAC_WAVE_DISABLE: wave mode disable
+ \arg DAC_WAVE_MODE_LFSR: LFSR noise mode
+ \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
+ \param[out] none
+ \retval none
+*/
+void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode)
+{
+ if(DAC_OUT0 == dac_out){
+ /* configure DACx_OUT0 wave mode */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0);
+ DAC_CTL0(dac_periph) |= wave_mode;
+ }else if(DAC_OUT1 == dac_out){
+ /* configure DACx_OUT1 wave mode */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1);
+ DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure DAC LFSR noise mode
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[in] unmask_bits: LFSR noise unmask bits
+ only one parameter can be selected which is shown as below:
+ \arg DAC_LFSR_BIT0: unmask the LFSR bit0
+ \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
+ \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
+ \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
+ \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
+ \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
+ \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
+ \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
+ \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
+ \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
+ \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
+ \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
+ \param[out] none
+ \retval none
+*/
+void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits)
+{
+ if(DAC_OUT0 == dac_out){
+ /* configure DACx_OUT0 LFSR noise mode */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
+ DAC_CTL0(dac_periph) |= unmask_bits;
+ }else if(DAC_OUT1 == dac_out){
+ /* configure DACx_OUT1 LFSR noise mode */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
+ DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure DAC triangle noise mode
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_out: DAC_OUTx(x=0,1)
+ \param[in] amplitude: the amplitude of the triangle
+ only one parameter can be selected which is shown as below:
+ \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
+ \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
+ \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
+ \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
+ \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
+ \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
+ \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
+ \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
+ \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
+ \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
+ \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
+ \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
+ \param[out] none
+ \retval none
+*/
+void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude)
+{
+ if(DAC_OUT0 == dac_out){
+ /* configure DACx_OUT0 triangle noise mode */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
+ DAC_CTL0(dac_periph) |= amplitude;
+ }else if(DAC_OUT1 == dac_out){
+ /* configure DACx_OUT1 triangle noise mode */
+ DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
+ DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief enable DAC concurrent mode
+ \param[in] dac_periph: DACx(x=0)
+ \param[out] none
+ \retval none
+*/
+void dac_concurrent_enable(uint32_t dac_periph)
+{
+ uint32_t ctl = 0U;
+
+ ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
+ DAC_CTL0(dac_periph) |= (uint32_t)ctl;
+}
+
+/*!
+ \brief disable DAC concurrent mode
+ \param[in] dac_periph: DACx(x=0)
+ \param[out] none
+ \retval none
+*/
+void dac_concurrent_disable(uint32_t dac_periph)
+{
+ uint32_t ctl = 0U;
+
+ ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
+ DAC_CTL0(dac_periph) &= (uint32_t)(~ctl);
+}
+
+/*!
+ \brief enable DAC concurrent software trigger
+ \param[in] dac_periph: DACx(x=0)
+ \param[out] none
+ \retval none
+*/
+void dac_concurrent_software_trigger_enable(uint32_t dac_periph)
+{
+ uint32_t swt = 0U;
+
+ swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
+ DAC_SWT(dac_periph) |= (uint32_t)swt;
+}
+
+/*!
+ \brief enable DAC concurrent buffer function
+ \param[in] dac_periph: DACx(x=0)
+ \param[out] none
+ \retval none
+*/
+void dac_concurrent_output_buffer_enable(uint32_t dac_periph)
+{
+ uint32_t ctl = 0U;
+
+ ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
+ DAC_CTL0(dac_periph) &= (uint32_t)(~ctl);
+}
+
+/*!
+ \brief disable DAC concurrent buffer function
+ \param[in] dac_periph: DACx(x=0)
+ \param[out] none
+ \retval none
+*/
+void dac_concurrent_output_buffer_disable(uint32_t dac_periph)
+{
+ uint32_t ctl = 0U;
+
+ ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
+ DAC_CTL0(dac_periph) |= (uint32_t)ctl;
+}
+
+/*!
+ \brief set DAC concurrent mode data holding register value
+ \param[in] dac_periph: DACx(x=0)
+ \param[in] dac_align: DAC data alignment mode
+ only one parameter can be selected which is shown as below:
+ \arg DAC_ALIGN_12B_R: 12-bit right-aligned data
+ \arg DAC_ALIGN_12B_L: 12-bit left-aligned data
+ \arg DAC_ALIGN_8B_R: 8-bit right-aligned data
+ \param[in] data0: data to be loaded(0~4095)
+ \param[in] data1: data to be loaded(0~4095)
+ \param[out] none
+ \retval none
+*/
+void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1)
+{
+ uint32_t data = 0U;
+
+ switch(dac_align){
+ /* 12-bit right-aligned data */
+ case DAC_ALIGN_12B_R:
+ data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
+ DACC_R12DH(dac_periph) = (uint32_t)data;
+ break;
+ /* 12-bit left-aligned data */
+ case DAC_ALIGN_12B_L:
+ data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
+ DACC_L12DH(dac_periph) = (uint32_t)data;
+ break;
+ /* 8-bit right-aligned data */
+ case DAC_ALIGN_8B_R:
+ data = (uint32_t)(((uint32_t)data1 << DH_8BIT_OFFSET) | data0);
+ DACC_R8DH(dac_periph) = (uint32_t)data;
+ break;
+ default:
+ break;
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c
new file mode 100644
index 0000000..5b236d3
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c
@@ -0,0 +1,149 @@
+/*!
+ \file gd32f10x_dbg.c
+ \brief DBG driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_dbg.h"
+
+/*!
+ \brief read DBG_ID code register
+ \param[in] none
+ \param[out] none
+ \retval DBG_ID code
+*/
+uint32_t dbg_id_get(void)
+{
+ return DBG_ID;
+}
+
+/*!
+ \brief enable low power behavior when the mcu is in debug mode
+ \param[in] dbg_low_power:
+ one or more parameters can be selected which are shown as below:
+ \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
+ \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
+ \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
+ \param[out] none
+ \retval none
+*/
+void dbg_low_power_enable(uint32_t dbg_low_power)
+{
+ DBG_CTL |= dbg_low_power;
+}
+
+/*!
+ \brief disable low power behavior when the mcu is in debug mode
+ \param[in] dbg_low_power:
+ one or more parameters can be selected which are shown as below:
+ \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
+ \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
+ \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
+ \param[out] none
+ \retval none
+*/
+void dbg_low_power_disable(uint32_t dbg_low_power)
+{
+ DBG_CTL &= ~dbg_low_power;
+}
+
+/*!
+ \brief enable peripheral behavior when the mcu is in debug mode
+ \param[in] dbg_periph: refer to dbg_periph_enum
+ one or more parameters can be selected which are shown as below:
+ \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+ \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+ \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
+ \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+ \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
+ \param[out] none
+ \retval none
+*/
+void dbg_periph_enable(dbg_periph_enum dbg_periph)
+{
+ DBG_CTL |= (uint32_t)dbg_periph;
+}
+
+/*!
+ \brief disable peripheral behavior when the mcu is in debug mode
+ \param[in] dbg_periph: refer to dbg_periph_enum
+ one or more parameters can be selected which are shown as below:
+ \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+ \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+ \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
+ \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+ \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted
+ \param[out] none
+ \retval none
+*/
+void dbg_periph_disable(dbg_periph_enum dbg_periph)
+{
+ DBG_CTL &= ~(uint32_t)dbg_periph;
+}
+
+/*!
+ \brief enable trace pin assignment
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void dbg_trace_pin_enable(void)
+{
+ DBG_CTL |= DBG_CTL_TRACE_IOEN;
+}
+
+/*!
+ \brief disable trace pin assignment
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void dbg_trace_pin_disable(void)
+{
+ DBG_CTL &= ~DBG_CTL_TRACE_IOEN;
+}
+
+/*!
+ \brief trace pin mode selection
+ \param[in] trace_mode:
+ only one parameter can be selected which is shown as below:
+ \arg TRACE_MODE_ASYNC: trace pin used for async mode
+ \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
+ \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
+ \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
+ \param[out] none
+ \retval none
+*/
+void dbg_trace_pin_mode_set(uint32_t trace_mode)
+{
+ DBG_CTL &= ~DBG_CTL_TRACE_MODE;
+ DBG_CTL |= trace_mode;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c
new file mode 100644
index 0000000..8219744
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c
@@ -0,0 +1,733 @@
+/*!
+ \file gd32f10x_dma.c
+ \brief DMA driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_dma.h"
+
+#define DMA_WRONG_HANDLE while(1){}
+
+ /* check whether peripheral matches channels or not */
+static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
+
+/*!
+ \brief deinitialize DMA a channel registers
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel is deinitialized
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ /* disable DMA a channel */
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
+ /* reset DMA channel registers */
+ DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
+ DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
+ DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
+ DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
+ DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
+}
+
+/*!
+ \brief initialize the parameters of DMA struct with the default values
+ \param[in] init_struct: the initialization data needed to initialize DMA channel
+ \param[out] none
+ \retval none
+*/
+void dma_struct_para_init(dma_parameter_struct* init_struct)
+{
+ /* set the DMA struct with the default values */
+ init_struct->periph_addr = 0U;
+ init_struct->periph_width = 0U;
+ init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE;
+ init_struct->memory_addr = 0U;
+ init_struct->memory_width = 0U;
+ init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE;
+ init_struct->number = 0U;
+ init_struct->direction = DMA_PERIPHERAL_TO_MEMORY;
+ init_struct->priority = DMA_PRIORITY_LOW;
+}
+
+/*!
+ \brief initialize DMA channel
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel is initialized
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] init_struct: the data needed to initialize DMA channel
+ periph_addr: peripheral base address
+ periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
+ periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
+ memory_addr: memory base address
+ memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
+ memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
+ direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
+ number: the number of remaining data to be transferred by the DMA
+ priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
+ \param[out] none
+ \retval none
+*/
+void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct)
+{
+ uint32_t ctl;
+
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ /* configure peripheral base address */
+ DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
+
+ /* configure memory base address */
+ DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr;
+
+ /* configure the number of remaining data to be transferred */
+ DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
+
+ /* configure peripheral transfer width,memory transfer width, */
+ ctl = DMA_CHCTL(dma_periph, channelx);
+ ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
+ ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
+ DMA_CHCTL(dma_periph, channelx) = ctl;
+
+ /* configure peripheral increasing mode */
+ if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
+ }else{
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
+ }
+
+ /* configure memory increasing mode */
+ if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
+ }else{
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
+ }
+
+ /* configure the direction of data transfer */
+ if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
+ }else{
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
+ }
+}
+
+/*!
+ \brief enable DMA circulation mode
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
+}
+
+/*!
+ \brief disable DMA circulation mode
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
+}
+
+/*!
+ \brief enable memory to memory mode
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
+}
+
+/*!
+ \brief disable memory to memory mode
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
+}
+
+/*!
+ \brief enable DMA channel
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
+}
+
+/*!
+ \brief disable DMA channel
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
+}
+
+/*!
+ \brief set DMA peripheral base address
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to set peripheral base address
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] address: peripheral base address
+ \param[out] none
+ \retval none
+*/
+void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHPADDR(dma_periph, channelx) = address;
+}
+
+/*!
+ \brief set DMA memory base address
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to set memory base address
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] address: memory base address
+ \param[out] none
+ \retval none
+*/
+void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHMADDR(dma_periph, channelx) = address;
+}
+
+/*!
+ \brief set the number of remaining data to be transferred by the DMA
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to set number
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] number: the number of remaining data to be transferred by the DMA
+ \arg 0x0000-0xFFFF
+ \param[out] none
+ \retval none
+*/
+void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
+}
+
+/*!
+ \brief get the number of remaining data to be transferred by the DMA
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to set number
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval uint32_t: the number of remaining data to be transferred by the DMA
+*/
+uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ return (uint32_t)DMA_CHCNT(dma_periph, channelx);
+}
+
+/*!
+ \brief configure priority level of DMA channel
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] priority: priority Level of this channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA_PRIORITY_LOW: low priority
+ \arg DMA_PRIORITY_MEDIUM: medium priority
+ \arg DMA_PRIORITY_HIGH: high priority
+ \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
+ \param[out] none
+ \retval none
+*/
+void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
+{
+ uint32_t ctl;
+
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ /* acquire DMA_CHxCTL register */
+ ctl = DMA_CHCTL(dma_periph, channelx);
+ /* assign regiser */
+ ctl &= ~DMA_CHXCTL_PRIO;
+ ctl |= priority;
+ DMA_CHCTL(dma_periph, channelx) = ctl;
+}
+
+/*!
+ \brief configure transfer data size of memory
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] mwidth: transfer data width of memory
+ only one parameter can be selected which is shown as below:
+ \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
+ \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
+ \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
+ \param[out] none
+ \retval none
+*/
+void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
+{
+ uint32_t ctl;
+
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ /* acquire DMA_CHxCTL register */
+ ctl = DMA_CHCTL(dma_periph, channelx);
+ /* assign regiser */
+ ctl &= ~DMA_CHXCTL_MWIDTH;
+ ctl |= mwidth;
+ DMA_CHCTL(dma_periph, channelx) = ctl;
+}
+
+/*!
+ \brief configure transfer data size of peripheral
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] pwidth: transfer data width of peripheral
+ only one parameter can be selected which is shown as below:
+ \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
+ \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
+ \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
+ \param[out] none
+ \retval none
+*/
+void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
+{
+ uint32_t ctl;
+
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ /* acquire DMA_CHxCTL register */
+ ctl = DMA_CHCTL(dma_periph, channelx);
+ /* assign regiser */
+ ctl &= ~DMA_CHXCTL_PWIDTH;
+ ctl |= pwidth;
+ DMA_CHCTL(dma_periph, channelx) = ctl;
+}
+
+/*!
+ \brief enable next address increasement algorithm of memory
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
+}
+
+/*!
+ \brief disable next address increasement algorithm of memory
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
+}
+
+/*!
+ \brief enable next address increasement algorithm of peripheral
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
+}
+
+/*!
+ \brief disable next address increasement algorithm of peripheral
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[out] none
+ \retval none
+*/
+void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
+}
+
+/*!
+ \brief configure the direction of data transfer on the channel
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] direction: specify the direction of data transfer
+ only one parameter can be selected which is shown as below:
+ \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
+ \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
+ \param[out] none
+ \retval none
+*/
+void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ if(DMA_PERIPHERAL_TO_MEMORY == direction){
+ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
+ } else {
+ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
+ }
+}
+
+/*!
+ \brief check DMA flag is set or not
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to get flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_FLAG_G: global interrupt flag of channel
+ \arg DMA_FLAG_FTF: full transfer finish flag of channel
+ \arg DMA_FLAG_HTF: half transfer finish flag of channel
+ \arg DMA_FLAG_ERR: error flag of channel
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+ FlagStatus reval;
+
+ /* check whether the flag is set or not */
+ if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
+ reval = SET;
+ }else{
+ reval = RESET;
+ }
+
+ return reval;
+}
+
+/*!
+ \brief clear the flag of a DMA channel
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to clear flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_FLAG_G: global interrupt flag of channel
+ \arg DMA_FLAG_FTF: full transfer finish flag of channel
+ \arg DMA_FLAG_HTF: half transfer finish flag of channel
+ \arg DMA_FLAG_ERR: error flag of channel
+ \param[out] none
+ \retval none
+*/
+void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+ DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+ \brief check DMA flag and interrupt enable bit is set or not
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to get flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_ERR: error interrupt flag of channel
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+ uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
+
+ switch(flag){
+ case DMA_INT_FLAG_FTF:
+ /* check whether the full transfer finish interrupt flag is set and enabled */
+ interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
+ interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
+ break;
+ case DMA_INT_FLAG_HTF:
+ /* check whether the half transfer finish interrupt flag is set and enabled */
+ interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
+ interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
+ break;
+ case DMA_INT_FLAG_ERR:
+ /* check whether the error interrupt flag is set and enabled */
+ interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
+ interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
+ break;
+ default:
+ DMA_WRONG_HANDLE
+ }
+
+ /* when the interrupt flag is set and enabled, return SET */
+ if(interrupt_flag && interrupt_enable){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear DMA a channel flag
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel to clear flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_INT_FLAG_G: global interrupt flag of channel
+ \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_ERR: error interrupt flag of channel
+ \param[out] none
+ \retval none
+*/
+void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+ DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+ \brief enable DMA interrupt
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] source: specify which interrupt to enbale
+ one or more parameters can be selected which are shown as below
+ \arg DMA_INT_FTF: channel full transfer finish interrupt
+ \arg DMA_INT_HTF: channel half transfer finish interrupt
+ \arg DMA_INT_ERR: channel error interrupt
+ \param[out] none
+ \retval none
+*/
+void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) |= source;
+}
+
+/*!
+ \brief disable DMA interrupt
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+ \param[in] source: specify which interrupt to disbale
+ one or more parameters can be selected which are shown as below
+ \arg DMA_INT_FTF: channel full transfer finish interrupt
+ \arg DMA_INT_HTF: channel half transfer finish interrupt
+ \arg DMA_INT_ERR: channel error interrupt
+ \param[out] none
+ \retval none
+*/
+void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
+{
+ if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+ DMA_WRONG_HANDLE
+ }
+
+ DMA_CHCTL(dma_periph, channelx) &= ~source;
+}
+
+/*!
+ \brief check whether peripheral and channels match
+ \param[in] dma_periph: DMAx(x=0,1)
+ \arg DMAx(x=0,1)
+ \param[in] channelx: specify which DMA channel
+ only one parameter can be selected which is shown as below:
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
+{
+ ErrStatus val = SUCCESS;
+
+ if(DMA1 == dma_periph){
+ /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */
+ if(channelx > DMA_CH4){
+ val = ERROR;
+ }
+ }
+
+ return val;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c
new file mode 100644
index 0000000..c0cdc33
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c
@@ -0,0 +1,3081 @@
+/*!
+ \file gd32f10x_enet.c
+ \brief ENET driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_enet.h"
+
+#ifdef GD32F10X_CL
+
+#if defined (__CC_ARM) /*!< ARM compiler */
+__align(4)
+enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */
+__align(4)
+enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */
+__align(4)
+uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */
+__align(4)
+uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */
+
+#elif defined ( __ICCARM__ ) /*!< IAR compiler */
+#pragma data_alignment=4
+enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */
+#pragma data_alignment=4
+enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */
+#pragma data_alignment=4
+uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */
+#pragma data_alignment=4
+uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */
+
+#elif defined (__GNUC__) /* GNU Compiler */
+enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */
+enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */
+uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */
+uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */
+
+#endif /* __CC_ARM */
+
+/* global transmit and receive descriptors pointers */
+enet_descriptors_struct *dma_current_txdesc;
+enet_descriptors_struct *dma_current_rxdesc;
+
+/* structure pointer of ptp descriptor for normal mode */
+enet_descriptors_struct *dma_current_ptp_txdesc = NULL;
+enet_descriptors_struct *dma_current_ptp_rxdesc = NULL;
+
+/* init structure parameters for ENET initialization */
+static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+static uint32_t enet_unknow_err = 0U;
+
+/* array of register offset for debug information get */
+static const uint16_t enet_reg_tab[] = {
+0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C,
+0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C,
+
+0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4,
+
+0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720,
+
+0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C,
+0x1050, 0x1054};
+
+
+/*!
+ \brief deinitialize the ENET, and reset structure parameters for ENET initialization
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_ENETRST);
+ rcu_periph_reset_disable(RCU_ENETRST);
+ enet_initpara_reset();
+}
+
+/*!
+ \brief configure the parameters which are usually less cared for initialization
+ note -- this function must be called before enet_init(), otherwise
+ configuration will be no effect
+ \param[in] option: different function option, which is related to several parameters,
+ only one parameter can be selected which is shown as below, refer to enet_option_enum
+ \arg FORWARD_OPTION: choose to configure the frame forward related parameters
+ \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters
+ \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters
+ \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters
+ \arg STORE_OPTION: choose to configure the store forward mode related parameters
+ \arg DMA_OPTION: choose to configure the DMA descriptor related parameters
+ \arg VLAN_OPTION: choose to configure vlan related parameters
+ \arg FLOWCTL_OPTION: choose to configure flow control related parameters
+ \arg HASHH_OPTION: choose to configure hash high
+ \arg HASHL_OPTION: choose to configure hash low
+ \arg FILTER_OPTION: choose to configure frame filter related parameters
+ \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters
+ \arg TIMER_OPTION: choose to configure time counter related parameters
+ \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters
+ \param[in] para: the related parameters according to the option
+ all the related parameters should be configured which are shown as below
+ FORWARD_OPTION related parameters:
+ - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ;
+ - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ;
+ - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE .
+ DMABUS_OPTION related parameters:
+ - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ;
+ - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ;
+ DMA_MAXBURST_OPTION related parameters:
+ - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/
+ ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/
+ ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/
+ ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/
+ ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ;
+ - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/
+ ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/
+ ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/
+ ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/
+ ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ;
+ - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ;
+ DMA_ARBITRATION_OPTION related parameters:
+ - ENET_ARBITRATION_RXPRIORTX / ENET_ARBITRATION_RXTX_1_1
+ / ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1
+ / ENET_ARBITRATION_RXTX_4_1.
+ STORE_OPTION related parameters:
+ - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ;
+ - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ;
+ - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/
+ ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ;
+ - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/
+ ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/
+ ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/
+ ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES .
+ DMA_OPTION related parameters:
+ - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ;
+ - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE .
+ VLAN_OPTION related parameters:
+ - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ;
+ - MAC_VLT_VLTI(regval) .
+ FLOWCTL_OPTION related parameters:
+ - MAC_FCTL_PTM(regval) ;
+ - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ;
+ - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/
+ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ;
+ - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ;
+ - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ;
+ - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE ;
+ - ENET_ACTIVE_THRESHOLD_256BYTES/ ENET_ACTIVE_THRESHOLD_512BYTES ;
+ - ENET_ACTIVE_THRESHOLD_768BYTES/ ENET_ACTIVE_THRESHOLD_1024BYTES ;
+ - ENET_ACTIVE_THRESHOLD_1280BYTES/ ENET_ACTIVE_THRESHOLD_1536BYTES ;
+ - ENET_ACTIVE_THRESHOLD_1792BYTES ;
+ - ENET_DEACTIVE_THRESHOLD_256BYTES/ ENET_DEACTIVE_THRESHOLD_512BYTES ;
+ - ENET_DEACTIVE_THRESHOLD_768BYTES/ ENET_DEACTIVE_THRESHOLD_1024BYTES ;
+ - ENET_DEACTIVE_THRESHOLD_1280BYTES/ ENET_DEACTIVE_THRESHOLD_1536BYTES ;
+ - ENET_DEACTIVE_THRESHOLD_1792BYTES .
+ HASHH_OPTION related parameters:
+ - 0x0~0xFFFF FFFFU
+ HASHL_OPTION related parameters:
+ - 0x0~0xFFFF FFFFU
+ FILTER_OPTION related parameters:
+ - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/
+ ENET_SRC_FILTER_DISABLE ;
+ - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ;
+ - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/
+ ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ;
+ - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/
+ ENET_UNICAST_FILTER_PERFECT ;
+ - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/
+ ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED .
+ HALFDUPLEX_OPTION related parameters:
+ - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ;
+ - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ;
+ - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ;
+ - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/
+ ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ;
+ - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE .
+ TIMER_OPTION related parameters:
+ - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ;
+ - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ;
+ INTERFRAMEGAP_OPTION related parameters:
+ - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/
+ ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/
+ ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/
+ ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT .
+ \param[out] none
+ \retval none
+*/
+void enet_initpara_config(enet_option_enum option, uint32_t para)
+{
+ switch(option){
+ case FORWARD_OPTION:
+ /* choose to configure forward_frame, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;
+ enet_initpara.forward_frame = para;
+ break;
+ case DMABUS_OPTION:
+ /* choose to configure dmabus_mode, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;
+ enet_initpara.dmabus_mode = para;
+ break;
+ case DMA_MAXBURST_OPTION:
+ /* choose to configure dma_maxburst, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;
+ enet_initpara.dma_maxburst = para;
+ break;
+ case DMA_ARBITRATION_OPTION:
+ /* choose to configure dma_arbitration, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;
+ enet_initpara.dma_arbitration = para;
+ break;
+ case STORE_OPTION:
+ /* choose to configure store_forward_mode, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)STORE_OPTION;
+ enet_initpara.store_forward_mode = para;
+ break;
+ case DMA_OPTION:
+ /* choose to configure dma_function, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)DMA_OPTION;
+ enet_initpara.dma_function = para;
+ break;
+ case VLAN_OPTION:
+ /* choose to configure vlan_config, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;
+ enet_initpara.vlan_config = para;
+ break;
+ case FLOWCTL_OPTION:
+ /* choose to configure flow_control, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;
+ enet_initpara.flow_control = para;
+ break;
+ case HASHH_OPTION:
+ /* choose to configure hashtable_high, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;
+ enet_initpara.hashtable_high = para;
+ break;
+ case HASHL_OPTION:
+ /* choose to configure hashtable_low, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;
+ enet_initpara.hashtable_low = para;
+ break;
+ case FILTER_OPTION:
+ /* choose to configure framesfilter_mode, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;
+ enet_initpara.framesfilter_mode = para;
+ break;
+ case HALFDUPLEX_OPTION:
+ /* choose to configure halfduplex_param, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;
+ enet_initpara.halfduplex_param = para;
+ break;
+ case TIMER_OPTION:
+ /* choose to configure timer_config, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;
+ enet_initpara.timer_config = para;
+ break;
+ case INTERFRAMEGAP_OPTION:
+ /* choose to configure interframegap, and save the configuration parameters */
+ enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;
+ enet_initpara.interframegap = para;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief initialize ENET peripheral with generally concerned parameters and the less cared
+ parameters
+ \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected
+ which is shown as below, refer to enet_mediamode_enum
+ \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation
+ \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex
+ \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex
+ \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex
+ \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex
+ \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII
+ \param[in] checksum: IP frame checksum offload function, only one parameter can be selected
+ which is shown as below, refer to enet_mediamode_enum
+ \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function
+ \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function
+ \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame
+ with only payload error but no other errors will not be dropped
+ \param[in] recept: frame filter function, only one parameter can be selected
+ which is shown as below, refer to enet_frmrecept_enum
+ \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled
+ \arg ENET_RECEIVEALL: all received frame are forwarded to application
+ \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames
+ \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept)
+{
+ uint32_t reg_value=0U, reg_temp = 0U, temp = 0U;
+ uint32_t media_temp = 0U;
+ uint32_t timeout = 0U;
+ uint16_t phy_value = 0U;
+ ErrStatus phy_state= ERROR, enet_state = ERROR;
+
+ /* PHY interface configuration, configure SMI clock and reset PHY chip */
+ if(ERROR == enet_phy_config()){
+ _ENET_DELAY_(PHY_RESETDELAY);
+ if(ERROR == enet_phy_config()){
+ return enet_state;
+ }
+ }
+ /* initialize ENET peripheral with generally concerned parameters */
+ enet_default_init();
+
+ /* 1st, configure mediamode */
+ media_temp = (uint32_t)mediamode;
+ /* if is PHY auto negotiation */
+ if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){
+ /* wait for PHY_LINKED_STATUS bit be set */
+ do{
+ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
+ phy_value &= PHY_LINKED_STATUS;
+ timeout++;
+ }while((RESET == phy_value) && (timeout < PHY_READ_TO));
+ /* return ERROR due to timeout */
+ if(PHY_READ_TO == timeout){
+ return enet_state;
+ }
+ /* reset timeout counter */
+ timeout = 0U;
+
+ /* enable auto-negotiation */
+ phy_value = PHY_AUTONEGOTIATION;
+ phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
+ if(!phy_state){
+ /* return ERROR due to write timeout */
+ return enet_state;
+ }
+
+ /* wait for the PHY_AUTONEGO_COMPLETE bit be set */
+ do{
+ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value);
+ phy_value &= PHY_AUTONEGO_COMPLETE;
+ timeout++;
+ }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO));
+ /* return ERROR due to timeout */
+ if(PHY_READ_TO == timeout){
+ return enet_state;
+ }
+ /* reset timeout counter */
+ timeout = 0U;
+
+ /* read the result of the auto-negotiation */
+ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value);
+ /* configure the duplex mode of MAC following the auto-negotiation result */
+ if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){
+ media_temp = ENET_MODE_FULLDUPLEX;
+ }else{
+ media_temp = ENET_MODE_HALFDUPLEX;
+ }
+ /* configure the communication speed of MAC following the auto-negotiation result */
+ if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){
+ media_temp |= ENET_SPEEDMODE_10M;
+ }else{
+ media_temp |= ENET_SPEEDMODE_100M;
+ }
+ }else{
+ phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3);
+ phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1);
+ phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value);
+ if(!phy_state){
+ /* return ERROR due to write timeout */
+ return enet_state;
+ }
+ /* PHY configuration need some time */
+ _ENET_DELAY_(PHY_CONFIGDELAY);
+ }
+ /* after configuring the PHY, use mediamode to configure registers */
+ reg_value = ENET_MAC_CFG;
+ /* configure ENET_MAC_CFG register */
+ reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM));
+ reg_value |= media_temp;
+ ENET_MAC_CFG = reg_value;
+
+
+ /* 2st, configure checksum */
+ if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){
+ ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE;
+
+ reg_value = ENET_DMA_CTL;
+ /* configure ENET_DMA_CTL register */
+ reg_value &= ~ENET_DMA_CTL_DTCERFD;
+ reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD);
+ ENET_DMA_CTL = reg_value;
+ }
+
+ /* 3rd, configure recept */
+ ENET_MAC_FRMF |= (uint32_t)recept;
+
+ /* 4th, configure different function options */
+ /* configure forward_frame related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){
+ reg_temp = enet_initpara.forward_frame;
+
+ reg_value = ENET_MAC_CFG;
+ temp = reg_temp;
+ /* configure ENET_MAC_CFG register */
+ reg_value &= (~ENET_MAC_CFG_APCD);
+ temp &= ENET_MAC_CFG_APCD;
+ reg_value |= temp;
+ ENET_MAC_CFG = reg_value;
+
+ reg_value = ENET_DMA_CTL;
+ temp = reg_temp;
+ /* configure ENET_DMA_CTL register */
+ reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF));
+ temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2);
+ reg_value |= (temp >> 2);
+ ENET_DMA_CTL = reg_value;
+ }
+
+ /* configure dmabus_mode related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){
+ temp = enet_initpara.dmabus_mode;
+
+ reg_value = ENET_DMA_BCTL;
+ /* configure ENET_DMA_BCTL register */
+ reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \
+ |ENET_DMA_BCTL_FPBL);
+ reg_value |= temp;
+ ENET_DMA_BCTL = reg_value;
+ }
+
+ /* configure dma_maxburst related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){
+ temp = enet_initpara.dma_maxburst;
+
+ reg_value = ENET_DMA_BCTL;
+ /* configure ENET_DMA_BCTL register */
+ reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP);
+ reg_value |= temp;
+ ENET_DMA_BCTL = reg_value;
+ }
+
+ /* configure dma_arbitration related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){
+ temp = enet_initpara.dma_arbitration;
+
+ reg_value = ENET_DMA_BCTL;
+ /* configure ENET_DMA_BCTL register */
+ reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB);
+ reg_value |= temp;
+ ENET_DMA_BCTL = reg_value;
+ }
+
+ /* configure store_forward_mode related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){
+ temp = enet_initpara.store_forward_mode;
+
+ reg_value = ENET_DMA_CTL;
+ /* configure ENET_DMA_CTL register */
+ reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC);
+ reg_value |= temp;
+ ENET_DMA_CTL = reg_value;
+ }
+
+ /* configure dma_function related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){
+ reg_temp = enet_initpara.dma_function;
+
+ reg_value = ENET_DMA_CTL;
+ /* configure ENET_DMA_CTL register */
+ reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF));
+ reg_value |= reg_temp;
+ ENET_DMA_CTL = reg_value;
+ }
+
+ /* configure vlan_config related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){
+ reg_temp = enet_initpara.vlan_config;
+
+ reg_value = ENET_MAC_VLT;
+ /* configure ENET_MAC_VLT register */
+ reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC);
+ reg_value |= reg_temp;
+ ENET_MAC_VLT = reg_value;
+ }
+
+ /* configure flow_control related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){
+ reg_temp = enet_initpara.flow_control;
+
+ reg_value = ENET_MAC_FCTL;
+ temp = reg_temp;
+ /* configure ENET_MAC_FCTL register */
+ reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
+ | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
+ temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \
+ | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN);
+ reg_value |= temp;
+ ENET_MAC_FCTL = reg_value;
+
+ reg_value = ENET_MAC_FCTH;
+ temp = reg_temp;
+ /* configure ENET_MAC_FCTH register */
+ reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD);
+ temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8);
+ reg_value |= (temp >> 8);
+ ENET_MAC_FCTH = reg_value;
+ }
+
+ /* configure hashtable_high related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){
+ ENET_MAC_HLH = enet_initpara.hashtable_high;
+ }
+
+ /* configure hashtable_low related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){
+ ENET_MAC_HLL = enet_initpara.hashtable_low;
+ }
+
+ /* configure framesfilter_mode related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){
+ reg_temp = enet_initpara.framesfilter_mode;
+
+ reg_value = ENET_MAC_FRMF;
+ /* configure ENET_MAC_FRMF register */
+ reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \
+ | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \
+ | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM);
+ reg_value |= reg_temp;
+ ENET_MAC_FRMF = reg_value;
+ }
+
+ /* configure halfduplex_param related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){
+ reg_temp = enet_initpara.halfduplex_param;
+
+ reg_value = ENET_MAC_CFG;
+ /* configure ENET_MAC_CFG register */
+ reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \
+ | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC);
+ reg_value |= reg_temp;
+ ENET_MAC_CFG = reg_value;
+ }
+
+ /* configure timer_config related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){
+ reg_temp = enet_initpara.timer_config;
+
+ reg_value = ENET_MAC_CFG;
+ /* configure ENET_MAC_CFG register */
+ reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD);
+ reg_value |= reg_temp;
+ ENET_MAC_CFG = reg_value;
+ }
+
+ /* configure interframegap related registers */
+ if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){
+ reg_temp = enet_initpara.interframegap;
+
+ reg_value = ENET_MAC_CFG;
+ /* configure ENET_MAC_CFG register */
+ reg_value &= ~ENET_MAC_CFG_IGBS;
+ reg_value |= reg_temp;
+ ENET_MAC_CFG = reg_value;
+ }
+
+ enet_state = SUCCESS;
+ return enet_state;
+}
+
+/*!
+ \brief reset all core internal registers located in CLK_TX and CLK_RX
+ \param[in] none
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_software_reset(void)
+{
+ uint32_t timeout = 0U;
+ ErrStatus enet_state = ERROR;
+ uint32_t dma_flag;
+
+ /* reset all core internal registers located in CLK_TX and CLK_RX */
+ ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
+
+ /* wait for reset operation complete */
+ do{
+ dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
+ timeout++;
+ }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
+
+ /* reset operation complete */
+ if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){
+ enet_state = SUCCESS;
+ }
+
+ return enet_state;
+}
+
+/*!
+ \brief check receive frame valid and return frame size
+ \param[in] none
+ \param[out] none
+ \retval size of received frame: 0x0 - 0x3FFF
+*/
+uint32_t enet_rxframe_size_get(void)
+{
+ uint32_t size = 0U;
+ uint32_t status;
+
+ /* get rdes0 information of current RxDMA descriptor */
+ status = dma_current_rxdesc->status;
+
+ /* if the desciptor is owned by DMA */
+ if((uint32_t)RESET != (status & ENET_RDES0_DAV)){
+ return 0U;
+ }
+
+ /* if has any error, or the frame uses two or more descriptors */
+ if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) ||
+ (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) ||
+ (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){
+ /* drop current receive frame */
+ enet_rxframe_drop();
+
+ return 1U;
+ }
+
+ /* if is an ethernet-type frame, and IP frame payload error occurred */
+ if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) &&
+ (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){
+ /* drop current receive frame */
+ enet_rxframe_drop();
+
+ return 1U;
+ }
+
+ /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */
+ if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) &&
+ (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) &&
+ (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) &&
+ (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){
+ /* get the size of the received data including CRC */
+ size = GET_RDES0_FRML(status);
+ /* substract the CRC size */
+ size = size - 4U;
+ }else{
+ enet_unknow_err++;
+ enet_rxframe_drop();
+
+ return 1U;
+ }
+
+ /* return packet size */
+ return size;
+}
+
+/*!
+ \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode
+ \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_DMA_TX: DMA Tx descriptors
+ \arg ENET_DMA_RX: DMA Rx descriptors
+ \param[out] none
+ \retval none
+*/
+void enet_descriptors_chain_init(enet_dmadirection_enum direction)
+{
+ uint32_t num = 0U, count = 0U, maxsize = 0U;
+ uint32_t desc_status = 0U, desc_bufsize = 0U;
+ enet_descriptors_struct *desc, *desc_tab;
+ uint8_t *buf;
+
+ /* if want to initialize DMA Tx descriptors */
+ if (ENET_DMA_TX == direction){
+ /* save a copy of the DMA Tx descriptors */
+ desc_tab = txdesc_tab;
+ buf = &tx_buff[0][0];
+ count = ENET_TXBUF_NUM;
+ maxsize = ENET_TXBUF_SIZE;
+
+ /* select chain mode */
+ desc_status = ENET_TDES0_TCHM;
+
+ /* configure DMA Tx descriptor table address register */
+ ENET_DMA_TDTADDR = (uint32_t)desc_tab;
+ dma_current_txdesc = desc_tab;
+ }else{
+ /* if want to initialize DMA Rx descriptors */
+ /* save a copy of the DMA Rx descriptors */
+ desc_tab = rxdesc_tab;
+ buf = &rx_buff[0][0];
+ count = ENET_RXBUF_NUM;
+ maxsize = ENET_RXBUF_SIZE;
+
+ /* enable receiving */
+ desc_status = ENET_RDES0_DAV;
+ /* select receive chained mode and set buffer1 size */
+ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
+
+ /* configure DMA Rx descriptor table address register */
+ ENET_DMA_RDTADDR = (uint32_t)desc_tab;
+ dma_current_rxdesc = desc_tab;
+ }
+ dma_current_ptp_rxdesc = NULL;
+ dma_current_ptp_txdesc = NULL;
+
+ /* configure each descriptor */
+ for(num=0U; num < count; num++){
+ /* get the pointer to the next descriptor of the descriptor table */
+ desc = desc_tab + num;
+
+ /* configure descriptors */
+ desc->status = desc_status;
+ desc->control_buffer_size = desc_bufsize;
+ desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
+
+ /* if is not the last descriptor */
+ if(num < (count - 1U)){
+ /* configure the next descriptor address */
+ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
+ }else{
+ /* when it is the last descriptor, the next descriptor address
+ equals to first descriptor address in descriptor table */
+ desc->buffer2_next_desc_addr = (uint32_t) desc_tab;
+ }
+ }
+}
+
+/*!
+ \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode
+ \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_DMA_TX: DMA Tx descriptors
+ \arg ENET_DMA_RX: DMA Rx descriptors
+ \param[out] none
+ \retval none
+*/
+void enet_descriptors_ring_init(enet_dmadirection_enum direction)
+{
+ uint32_t num = 0U, count = 0U, maxsize = 0U;
+ uint32_t desc_status = 0U, desc_bufsize = 0U;
+ enet_descriptors_struct *desc;
+ enet_descriptors_struct *desc_tab;
+ uint8_t *buf;
+
+ /* configure descriptor skip length */
+ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
+ ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
+
+ /* if want to initialize DMA Tx descriptors */
+ if (ENET_DMA_TX == direction){
+ /* save a copy of the DMA Tx descriptors */
+ desc_tab = txdesc_tab;
+ buf = &tx_buff[0][0];
+ count = ENET_TXBUF_NUM;
+ maxsize = ENET_TXBUF_SIZE;
+
+ /* configure DMA Tx descriptor table address register */
+ ENET_DMA_TDTADDR = (uint32_t)desc_tab;
+ dma_current_txdesc = desc_tab;
+ }else{
+ /* if want to initialize DMA Rx descriptors */
+ /* save a copy of the DMA Rx descriptors */
+ desc_tab = rxdesc_tab;
+ buf = &rx_buff[0][0];
+ count = ENET_RXBUF_NUM;
+ maxsize = ENET_RXBUF_SIZE;
+
+ /* enable receiving */
+ desc_status = ENET_RDES0_DAV;
+ /* set buffer1 size */
+ desc_bufsize = ENET_RXBUF_SIZE;
+
+ /* configure DMA Rx descriptor table address register */
+ ENET_DMA_RDTADDR = (uint32_t)desc_tab;
+ dma_current_rxdesc = desc_tab;
+ }
+ dma_current_ptp_rxdesc = NULL;
+ dma_current_ptp_txdesc = NULL;
+
+ /* configure each descriptor */
+ for(num=0U; num < count; num++){
+ /* get the pointer to the next descriptor of the descriptor table */
+ desc = desc_tab + num;
+
+ /* configure descriptors */
+ desc->status = desc_status;
+ desc->control_buffer_size = desc_bufsize;
+ desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
+
+ /* when it is the last descriptor */
+ if(num == (count - 1U)){
+ if (ENET_DMA_TX == direction){
+ /* configure transmit end of ring mode */
+ desc->status |= ENET_TDES0_TERM;
+ }else{
+ /* configure receive end of ring mode */
+ desc->control_buffer_size |= ENET_RDES1_RERM;
+ }
+ }
+ }
+}
+
+/*!
+ \brief handle current received frame data to application buffer
+ \param[in] bufsize: the size of buffer which is the parameter in function
+ \param[out] buffer: pointer to the received frame data
+ note -- if the input is NULL, user should copy data in application by himself
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize)
+{
+ uint32_t offset = 0U, size = 0U;
+
+ /* the descriptor is busy due to own by the DMA */
+ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
+ return ERROR;
+ }
+
+
+ /* if buffer pointer is null, indicates that users has copied data in application */
+ if(NULL != buffer){
+ /* if no error occurs, and the frame uses only one descriptor */
+ if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
+ (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
+ (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
+ /* get the frame length except CRC */
+ size = GET_RDES0_FRML(dma_current_rxdesc->status);
+ size = size - 4U;
+
+ /* to avoid situation that the frame size exceeds the buffer length */
+ if(size > bufsize){
+ return ERROR;
+ }
+
+ /* copy data from Rx buffer to application buffer */
+ for(offset = 0U; offsetbuffer1_addr) + offset));
+ }
+
+ }else{
+ /* return ERROR */
+ return ERROR;
+ }
+ }
+ /* enable reception, descriptor is owned by DMA */
+ dma_current_rxdesc->status = ENET_RDES0_DAV;
+
+ /* check Rx buffer unavailable flag status */
+ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
+ /* clear RBU flag */
+ ENET_DMA_STAT = ENET_DMA_STAT_RBU;
+ /* resume DMA reception by writing to the RPEN register*/
+ ENET_DMA_RPEN = 0U;
+ }
+
+ /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
+ /* chained mode */
+ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
+ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
+ }else{
+ /* ring mode */
+ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
+ /* if is the last descriptor in table, the next descriptor is the table header */
+ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
+ }else{
+ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
+ dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
+ }
+ }
+
+ return SUCCESS;
+}
+
+/*!
+ \brief handle application buffer data to transmit it
+ \param[in] buffer: pointer to the frame data to be transmitted,
+ note -- if the input is NULL, user should handle the data in application by himself
+ \param[in] length: the length of frame data to be transmitted
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length)
+{
+ uint32_t offset = 0U;
+ uint32_t dma_tbu_flag, dma_tu_flag;
+
+ /* the descriptor is busy due to own by the DMA */
+ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
+ return ERROR;
+ }
+
+ /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
+ if(length > ENET_MAX_FRAME_SIZE){
+ return ERROR;
+ }
+
+ /* if buffer pointer is null, indicates that users has handled data in application */
+ if(NULL != buffer){
+ /* copy frame data from application buffer to Tx buffer */
+ for(offset = 0U; offset < length; offset++){
+ (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
+ }
+ }
+
+ /* set the frame length */
+ dma_current_txdesc->control_buffer_size = length;
+ /* set the segment of frame, frame is transmitted in one descriptor */
+ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
+ /* enable the DMA transmission */
+ dma_current_txdesc->status |= ENET_TDES0_DAV;
+
+ /* check Tx buffer unavailable flag status */
+ dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
+ dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
+
+ if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
+ /* clear TBU and TU flag */
+ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
+ /* resume DMA transmission by writing to the TPEN register*/
+ ENET_DMA_TPEN = 0U;
+ }
+
+ /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/
+ /* chained mode */
+ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
+ dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr);
+ }else{
+ /* ring mode */
+ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
+ /* if is the last descriptor in table, the next descriptor is the table header */
+ dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
+ }else{
+ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
+ dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)));
+ }
+ }
+
+ return SUCCESS;
+}
+
+/*!
+ \brief configure the transmit IP frame checksum offload calculation and insertion
+ \param[in] desc: the descriptor pointer which users want to configure
+ \param[in] checksum: IP frame checksum configuration
+ only one parameter can be selected which is shown as below
+ \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled
+ \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled
+ \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header
+ \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated
+ \param[out] none
+ \retval none
+*/
+void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum)
+{
+ desc->status &= ~ENET_TDES0_CM;
+ desc->status |= checksum;
+}
+
+/*!
+ \brief ENET Tx and Rx function enable (include MAC and DMA module)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_enable(void)
+{
+ enet_tx_enable();
+ enet_rx_enable();
+}
+
+/*!
+ \brief ENET Tx and Rx function disable (include MAC and DMA module)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_disable(void)
+{
+ enet_tx_disable();
+ enet_rx_disable();
+}
+
+/*!
+ \brief configure MAC address
+ \param[in] mac_addr: select which MAC address will be set,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_ADDRESS0: set MAC address 0 filter
+ \arg ENET_MAC_ADDRESS1: set MAC address 1 filter
+ \arg ENET_MAC_ADDRESS2: set MAC address 2 filter
+ \arg ENET_MAC_ADDRESS3: set MAC address 3 filter
+ \param[in] paddr: the buffer pointer which stores the MAC address
+ (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa})
+ \param[out] none
+ \retval none
+*/
+void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[])
+{
+ REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr);
+ REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr);
+}
+
+/*!
+ \brief get MAC address
+ \param[in] mac_addr: select which MAC address will be get,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_ADDRESS0: get MAC address 0 filter
+ \arg ENET_MAC_ADDRESS1: get MAC address 1 filter
+ \arg ENET_MAC_ADDRESS2: get MAC address 2 filter
+ \arg ENET_MAC_ADDRESS3: get MAC address 3 filter
+ \param[out] paddr: the buffer pointer which is stored the MAC address
+ (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa})
+ \retval none
+*/
+void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[])
+{
+ paddr[0] = ENET_GET_MACADDR(mac_addr, 0U);
+ paddr[1] = ENET_GET_MACADDR(mac_addr, 1U);
+ paddr[2] = ENET_GET_MACADDR(mac_addr, 2U);
+ paddr[3] = ENET_GET_MACADDR(mac_addr, 3U);
+ paddr[4] = ENET_GET_MACADDR(mac_addr, 4U);
+ paddr[5] = ENET_GET_MACADDR(mac_addr, 5U);
+}
+
+/*!
+ \brief get the ENET MAC/MSC/PTP/DMA status flag
+ \param[in] enet_flag: ENET status flag, refer to enet_flag_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_FLAG_MPKR: magic packet received flag
+ \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag
+ \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag
+ \arg ENET_MAC_FLAG_WUM: WUM status flag
+ \arg ENET_MAC_FLAG_MSC: MSC status flag
+ \arg ENET_MAC_FLAG_MSCR: MSC receive status flag
+ \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag
+ \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag
+ \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag
+ \arg ENET_PTP_FLAG_TTM: target time match flag
+ \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag
+ \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag
+ \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag
+ \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag
+ \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag
+ \arg ENET_MSC_FLAG_TGF: transmitted good frames flag
+ \arg ENET_DMA_FLAG_TS: transmit status flag
+ \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag
+ \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag
+ \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag
+ \arg ENET_DMA_FLAG_RO: receive overflow status flag
+ \arg ENET_DMA_FLAG_TU: transmit underflow status flag
+ \arg ENET_DMA_FLAG_RS: receive status flag
+ \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag
+ \arg ENET_DMA_FLAG_RPS: receive process stopped status flag
+ \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag
+ \arg ENET_DMA_FLAG_ET: early transmit status flag
+ \arg ENET_DMA_FLAG_FBE: fatal bus error status flag
+ \arg ENET_DMA_FLAG_ER: early receive status flag
+ \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag
+ \arg ENET_DMA_FLAG_NI: normal interrupt summary flag
+ \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag
+ \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag
+ \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag
+ \arg ENET_DMA_FLAG_MSC: MSC status flag
+ \arg ENET_DMA_FLAG_WUM: WUM status flag
+ \arg ENET_DMA_FLAG_TST: timestamp trigger status flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus enet_flag_get(enet_flag_enum enet_flag)
+{
+ if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear the ENET DMA status flag
+ \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum
+ only one parameter can be selected which is shown as below
+ \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear
+ \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear
+ \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear
+ \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear
+ \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear
+ \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear
+ \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear
+ \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear
+ \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear
+ \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear
+ \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear
+ \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear
+ \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear
+ \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear
+ \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear
+ \param[out] none
+ \retval none
+*/
+void enet_flag_clear(enet_flag_clear_enum enet_flag)
+{
+ /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
+ ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag));
+}
+
+/*!
+ \brief enable ENET MAC/MSC/DMA interrupt
+ \param[in] enet_int: ENET interrupt,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_INT_WUMIM: WUM interrupt mask
+ \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask
+ \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask
+ \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask
+ \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask
+ \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask
+ \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask
+ \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask
+ \arg ENET_DMA_INT_TIE: transmit interrupt enable
+ \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable
+ \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable
+ \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable
+ \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable
+ \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable
+ \arg ENET_DMA_INT_RIE: receive interrupt enable
+ \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable
+ \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable
+ \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable
+ \arg ENET_DMA_INT_ETIE: early transmit interrupt enable
+ \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable
+ \arg ENET_DMA_INT_ERIE: early receive interrupt enable
+ \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable
+ \arg ENET_DMA_INT_NIE: normal interrupt summary enable
+ \param[out] none
+ \retval none
+*/
+void enet_interrupt_enable(enet_int_enum enet_int)
+{
+ if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
+ /* ENET_DMA_INTEN register interrupt */
+ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
+ }else{
+ /* other INTMSK register interrupt */
+ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
+ }
+}
+
+/*!
+ \brief disable ENET MAC/MSC/DMA interrupt
+ \param[in] enet_int: ENET interrupt,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_INT_WUMIM: WUM interrupt mask
+ \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask
+ \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask
+ \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask
+ \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask
+ \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask
+ \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask
+ \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask
+ \arg ENET_DMA_INT_TIE: transmit interrupt enable
+ \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable
+ \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable
+ \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable
+ \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable
+ \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable
+ \arg ENET_DMA_INT_RIE: receive interrupt enable
+ \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable
+ \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable
+ \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable
+ \arg ENET_DMA_INT_ETIE: early transmit interrupt enable
+ \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable
+ \arg ENET_DMA_INT_ERIE: early receive interrupt enable
+ \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable
+ \arg ENET_DMA_INT_NIE: normal interrupt summary enable
+ \param[out] none
+ \retval none
+*/
+void enet_interrupt_disable(enet_int_enum enet_int)
+{
+ if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){
+ /* ENET_DMA_INTEN register interrupt */
+ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int));
+ }else{
+ /* other INTMSK register interrupt */
+ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int));
+ }
+}
+
+/*!
+ \brief get ENET MAC/MSC/DMA interrupt flag
+ \param[in] int_flag: ENET interrupt flag,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_INT_FLAG_WUM: WUM status flag
+ \arg ENET_MAC_INT_FLAG_MSC: MSC status flag
+ \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag
+ \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag
+ \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag
+ \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag
+ \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag
+ \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag
+ \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag
+ \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag
+ \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag
+ \arg ENET_DMA_INT_FLAG_TS: transmit status flag
+ \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag
+ \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag
+ \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag
+ \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag
+ \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag
+ \arg ENET_DMA_INT_FLAG_RS: receive status flag
+ \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag
+ \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag
+ \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag
+ \arg ENET_DMA_INT_FLAG_ET: early transmit status flag
+ \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag
+ \arg ENET_DMA_INT_FLAG_ER: early receive status flag
+ \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag
+ \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag
+ \arg ENET_DMA_INT_FLAG_MSC: MSC status flag
+ \arg ENET_DMA_INT_FLAG_WUM: WUM status flag
+ \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag)
+{
+ if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear ENET DMA interrupt flag
+ \param[in] int_flag_clear: clear ENET interrupt flag,
+ only one parameter can be selected which is shown as below
+ \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag
+ \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag
+ \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag
+ \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag
+ \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag
+ \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag
+ \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag
+ \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag
+ \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag
+ \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag
+ \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag
+ \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag
+ \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag
+ \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag
+ \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag
+ \param[out] none
+ \retval none
+*/
+void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear)
+{
+ /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */
+ ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear));
+}
+
+/*!
+ \brief ENET Tx function enable (include MAC and DMA module)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_tx_enable(void)
+{
+ ENET_MAC_CFG |= ENET_MAC_CFG_TEN;
+ enet_txfifo_flush();
+ ENET_DMA_CTL |= ENET_DMA_CTL_STE;
+}
+
+/*!
+ \brief ENET Tx function disable (include MAC and DMA module)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_tx_disable(void)
+{
+ ENET_DMA_CTL &= ~ENET_DMA_CTL_STE;
+ enet_txfifo_flush();
+ ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN;
+}
+
+/*!
+ \brief ENET Rx function enable (include MAC and DMA module)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_rx_enable(void)
+{
+ ENET_MAC_CFG |= ENET_MAC_CFG_REN;
+ ENET_DMA_CTL |= ENET_DMA_CTL_SRE;
+}
+
+/*!
+ \brief ENET Rx function disable (include MAC and DMA module)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_rx_disable(void)
+{
+ ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE;
+ ENET_MAC_CFG &= ~ENET_MAC_CFG_REN;
+}
+
+/*!
+ \brief put registers value into the application buffer
+ \param[in] type: register type which will be get, refer to enet_registers_type_enum,
+ only one parameter can be selected which is shown as below
+ \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH
+ \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT
+ \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL
+ \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR
+ \param[in] num: the number of registers that the user want to get
+ \param[out] preg: the application buffer pointer for storing the register value
+ \retval none
+*/
+void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num)
+{
+ uint32_t offset = 0U, max = 0U, limit = 0U;
+
+ offset = (uint32_t)type;
+ max = (uint32_t)type + num;
+ limit = sizeof(enet_reg_tab)/sizeof(uint16_t);
+
+ /* prevent element in this array is out of range */
+ if(max > limit){
+ max = limit;
+ }
+
+ for(; offset < max; offset++){
+ /* get value of the corresponding register */
+ *preg = REG32((ENET) + enet_reg_tab[offset]);
+ preg++;
+ }
+}
+
+/*!
+ \brief enable the MAC address filter
+ \param[in] mac_addr: select which MAC address will be enable
+ \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter
+ \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter
+ \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter
+ \param[out] none
+ \retval none
+*/
+void enet_address_filter_enable(enet_macaddress_enum mac_addr)
+{
+ REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE;
+}
+
+/*!
+ \brief disable the MAC address filter
+ \param[in] mac_addr: select which MAC address will be disable,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter
+ \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter
+ \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter
+ \param[out] none
+ \retval none
+*/
+void enet_address_filter_disable(enet_macaddress_enum mac_addr)
+{
+ REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE;
+}
+
+/*!
+ \brief configure the MAC address filter
+ \param[in] mac_addr: select which MAC address will be configured,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter
+ \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter
+ \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter
+ \param[in] addr_mask: select which MAC address bytes will be mask,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits
+ \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits
+ \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits
+ \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits
+ \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits
+ \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits
+ \param[in] filter_type: select which MAC address filter type will be selected,
+ only one parameter can be selected which is shown as below
+ \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame
+ \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame
+ \param[out] none
+ \retval none
+*/
+void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type)
+{
+ uint32_t reg;
+
+ /* get the address filter register value which is to be configured */
+ reg = REG32(ENET_ADDRH_BASE + mac_addr);
+
+ /* clear and configure the address filter register */
+ reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF);
+ reg |= (addr_mask | filter_type);
+ REG32(ENET_ADDRH_BASE + mac_addr) = reg;
+}
+
+/*!
+ \brief PHY interface configuration (configure SMI clock and reset PHY chip)
+ \param[in] none
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_phy_config(void)
+{
+ uint32_t ahbclk;
+ uint32_t reg;
+ uint16_t phy_value;
+ ErrStatus enet_state = ERROR;
+
+ /* clear the previous MDC clock */
+ reg = ENET_MAC_PHY_CTL;
+ reg &= ~ENET_MAC_PHY_CTL_CLR;
+
+ /* get the HCLK frequency */
+ ahbclk = rcu_clock_freq_get(CK_AHB);
+
+ /* configure MDC clock according to HCLK frequency range */
+ if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){
+ reg |= ENET_MDC_HCLK_DIV16;
+ }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){
+ reg |= ENET_MDC_HCLK_DIV26;
+ }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){
+ reg |= ENET_MDC_HCLK_DIV42;
+ }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){
+ reg |= ENET_MDC_HCLK_DIV62;
+ }else{
+ return enet_state;
+ }
+ ENET_MAC_PHY_CTL = reg;
+
+ /* reset PHY */
+ phy_value = PHY_RESET;
+ if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
+ return enet_state;
+ }
+ /* PHY reset need some time */
+ _ENET_DELAY_(ENET_DELAY_TO);
+
+ /* check whether PHY reset is complete */
+ if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){
+ return enet_state;
+ }
+
+ /* PHY reset complete */
+ if(RESET == (phy_value & PHY_RESET)){
+ enet_state = SUCCESS;
+ }
+
+ return enet_state;
+}
+
+/*!
+ \brief write to / read from a PHY register
+ \param[in] direction: only one parameter can be selected which is shown as below
+ \arg ENET_PHY_WRITE: write data to phy register
+ \arg ENET_PHY_READ: read data from phy register
+ \param[in] phy_address: 0x0 - 0x1F
+ \param[in] phy_reg: 0x0 - 0x1F
+ \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction
+ \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue)
+{
+ uint32_t reg, phy_flag;
+ uint32_t timeout = 0U;
+ ErrStatus enet_state = ERROR;
+
+ /* configure ENET_MAC_PHY_CTL with write/read operation */
+ reg = ENET_MAC_PHY_CTL;
+ reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA);
+ reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB);
+
+ /* if do the write operation, write value to the register */
+ if(ENET_PHY_WRITE == direction){
+ ENET_MAC_PHY_DATA = *pvalue;
+ }
+
+ /* do PHY write/read operation, and wait the operation complete */
+ ENET_MAC_PHY_CTL = reg;
+ do{
+ phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
+ timeout++;
+ }
+ while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
+
+ /* write/read operation complete */
+ if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){
+ enet_state = SUCCESS;
+ }
+
+ /* if do the read operation, get value from the register */
+ if(ENET_PHY_READ == direction){
+ *pvalue = (uint16_t)ENET_MAC_PHY_DATA;
+ }
+
+ return enet_state;
+}
+
+/*!
+ \brief enable the loopback function of PHY chip
+ \param[in] none
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus enet_phyloopback_enable(void)
+{
+ uint16_t temp_phy = 0U;
+ ErrStatus phy_state = ERROR;
+
+ /* get the PHY configuration to update it */
+ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
+
+ /* enable the PHY loopback mode */
+ temp_phy |= PHY_LOOPBACK;
+
+ /* update the PHY control register with the new configuration */
+ phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
+
+ return phy_state;
+}
+
+/*!
+ \brief disable the loopback function of PHY chip
+ \param[in] none
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus enet_phyloopback_disable(void)
+{
+ uint16_t temp_phy = 0U;
+ ErrStatus phy_state = ERROR;
+
+ /* get the PHY configuration to update it */
+ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
+
+ /* disable the PHY loopback mode */
+ temp_phy &= (uint16_t)~PHY_LOOPBACK;
+
+ /* update the PHY control register with the new configuration */
+ phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy);
+
+ return phy_state;
+}
+
+/*!
+ \brief enable ENET forward feature
+ \param[in] feature: the feature of ENET forward mode,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames
+ \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory
+ \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames
+ \param[out] none
+ \retval none
+*/
+void enet_forward_feature_enable(uint32_t feature)
+{
+ uint32_t mask;
+
+ mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
+ ENET_MAC_CFG |= mask;
+
+ mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
+ ENET_DMA_CTL |= (mask >> 2);
+}
+
+/*!
+ \brief disable ENET forward feature
+ \param[in] feature: the feature of ENET forward mode,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames
+ \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory
+ \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames
+ \param[out] none
+ \retval none
+*/
+void enet_forward_feature_disable(uint32_t feature)
+{
+ uint32_t mask;
+
+ mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES)));
+ ENET_MAC_CFG &= ~mask;
+
+ mask = (feature & (~(ENET_AUTO_PADCRC_DROP)));
+ ENET_DMA_CTL &= ~(mask >> 2);
+}
+
+/*!
+ \brief enable ENET filter feature
+ \param[in] feature: the feature of ENET filter mode,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_SRC_FILTER: filter source address function
+ \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function
+ \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function
+ \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function
+ \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function
+ \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function
+ \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function
+ \param[out] none
+ \retval none
+*/
+void enet_filter_feature_enable(uint32_t feature)
+{
+ ENET_MAC_FRMF |= feature;
+}
+
+/*!
+ \brief disable ENET filter feature
+ \param[in] feature: the feature of ENET filter mode,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_SRC_FILTER: filter source address function
+ \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function
+ \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function
+ \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function
+ \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function
+ \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function
+ \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function
+ \param[out] none
+ \retval none
+*/
+void enet_filter_feature_disable(uint32_t feature)
+{
+ ENET_MAC_FRMF &= ~feature;
+}
+
+/*!
+ \brief generate the pause frame, ENET will send pause frame after enable transmit flow control
+ this function only use in full-dulex mode
+ \param[in] none
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus enet_pauseframe_generate(void)
+{
+ ErrStatus enet_state =ERROR;
+ uint32_t temp = 0U;
+
+ /* in full-duplex mode, must make sure this bit is 0 before writing register */
+ temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA;
+ if(RESET == temp){
+ ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA;
+ enet_state = SUCCESS;
+ }
+ return enet_state;
+}
+
+/*!
+ \brief configure the pause frame detect type
+ \param[in] detect: pause frame detect type,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also
+ use the MAC0 address to detecting pause frame
+ \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified
+ in IEEE802.3 can be detected
+ \param[out] none
+ \retval none
+*/
+void enet_pauseframe_detect_config(uint32_t detect)
+{
+ ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT;
+ ENET_MAC_FCTL |= detect;
+}
+
+/*!
+ \brief configure the pause frame parameters
+ \param[in] pausetime: pause time in transmit pause control frame
+ \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically,
+ this value must make sure to be less than configured pause time, only one parameter can be
+ selected which is shown as below
+ \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times
+ \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times
+ \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times
+ \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times
+ \param[out] none
+ \retval none
+*/
+void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold)
+{
+ ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS);
+ ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold);
+}
+
+/*!
+ \brief configure the threshold of the flow control(deactive and active threshold)
+ \param[in] deactive: the threshold of the deactive flow control, this value
+ should always be less than active flow control value, only one
+ parameter can be selected which is shown as below
+ \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes
+ \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes
+ \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes
+ \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes
+ \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes
+ \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes
+ \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes
+ \param[in] active: the threshold of the active flow control, only one parameter
+ can be selected which is shown as below
+ \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes
+ \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes
+ \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes
+ \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes
+ \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes
+ \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes
+ \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes
+ \param[out] none
+ \retval none
+*/
+void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active)
+{
+ ENET_MAC_FCTH = ((deactive | active) >> 8);
+}
+
+/*!
+ \brief enable ENET flow control feature
+ \param[in] feature: the feature of ENET flow control mode
+ one or more parameters can be selected which are shown as below
+ \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function
+ \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC
+ \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it
+ \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode)
+ \param[out] none
+ \retval none
+*/
+void enet_flowcontrol_feature_enable(uint32_t feature)
+{
+ if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
+ ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE;
+ }
+ feature &= ~ENET_ZERO_QUANTA_PAUSE;
+ ENET_MAC_FCTL |= feature;
+}
+
+/*!
+ \brief disable ENET flow control feature
+ \param[in] feature: the feature of ENET flow control mode
+ one or more parameters can be selected which are shown as below
+ \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function
+ \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC
+ \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it
+ \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode)
+ \param[out] none
+ \retval none
+*/
+void enet_flowcontrol_feature_disable(uint32_t feature)
+{
+ if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){
+ ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE;
+ }
+ feature &= ~ENET_ZERO_QUANTA_PAUSE;
+ ENET_MAC_FCTL &= ~feature;
+}
+
+/*!
+ \brief get the dma transmit/receive process state
+ \param[in] direction: choose the direction of dma process which users want to check,
+ refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
+ \arg ENET_DMA_TX: dma transmit process
+ \arg ENET_DMA_RX: dma receive process
+ \param[out] none
+ \retval state of dma process, the value range shows below:
+ ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING,
+ ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING,
+ ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING,
+ ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING
+*/
+uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction)
+{
+ uint32_t reval;
+ reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction);
+ return reval;
+}
+
+/*!
+ \brief poll the DMA transmission/reception enable by writing any value to the
+ ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception
+ \param[in] direction: choose the direction of DMA process which users want to resume,
+ refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below
+ \arg ENET_DMA_TX: DMA transmit process
+ \arg ENET_DMA_RX: DMA receive process
+ \param[out] none
+ \retval none
+*/
+void enet_dmaprocess_resume(enet_dmadirection_enum direction)
+{
+ if(ENET_DMA_TX == direction){
+ ENET_DMA_TPEN = 0U;
+ }else{
+ ENET_DMA_RPEN = 0U;
+ }
+}
+
+/*!
+ \brief check and recover the Rx process
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_rxprocess_check_recovery(void)
+{
+ uint32_t status;
+
+ /* get DAV information of current RxDMA descriptor */
+ status = dma_current_rxdesc->status;
+ status &= ENET_RDES0_DAV;
+
+ /* if current descriptor is owned by DMA, but the descriptor address mismatches with
+ receive descriptor address pointer updated by RxDMA controller */
+ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) &&
+ (ENET_RDES0_DAV == status)){
+ dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR;
+ }
+}
+
+/*!
+ \brief flush the ENET transmit FIFO, and wait until the flush operation completes
+ \param[in] none
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus enet_txfifo_flush(void)
+{
+ uint32_t flush_state;
+ uint32_t timeout = 0U;
+ ErrStatus enet_state = ERROR;
+
+ /* set the FTF bit for flushing transmit FIFO */
+ ENET_DMA_CTL |= ENET_DMA_CTL_FTF;
+ /* wait until the flush operation completes */
+ do{
+ flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF;
+ timeout++;
+ }while((RESET != flush_state) && (timeout < ENET_DELAY_TO));
+ /* return ERROR due to timeout */
+ if(RESET == flush_state){
+ enet_state = SUCCESS;
+ }
+
+ return enet_state;
+}
+
+/*!
+ \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table
+ \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table
+ \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by
+ the RxDMA controller
+ \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller
+ \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table
+ \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by
+ the TxDMA controller
+ \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller
+ \param[out] none
+ \retval address value
+*/
+uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get)
+{
+ uint32_t reval = 0U;
+
+ reval = REG32((ENET) +(uint32_t)addr_get);
+ return reval;
+}
+
+/*!
+ \brief get the Tx or Rx descriptor information
+ \param[in] desc: the descriptor pointer which users want to get information
+ \param[in] info_get: the descriptor information type which is selected,
+ only one parameter can be selected which is shown as below
+ \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size
+ \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size
+ \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer
+ \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted
+ \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame
+ \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame
+ \param[out] none
+ \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter
+*/
+uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get)
+{
+ uint32_t reval = 0xFFFFFFFFU;
+
+ switch(info_get){
+ case RXDESC_BUFFER_1_SIZE:
+ reval = GET_RDES1_RB1S(desc->control_buffer_size);
+ break;
+ case RXDESC_BUFFER_2_SIZE:
+ reval = GET_RDES1_RB2S(desc->control_buffer_size);
+ break;
+ case RXDESC_FRAME_LENGTH:
+ reval = GET_RDES0_FRML(desc->status);
+ if(reval > 4U){
+ reval = reval - 4U;
+ }else{
+ reval = 0U;
+ }
+ break;
+ case RXDESC_BUFFER_1_ADDR:
+ reval = desc->buffer1_addr;
+ break;
+ case TXDESC_BUFFER_1_ADDR:
+ reval = desc->buffer1_addr;
+ break;
+ case TXDESC_COLLISION_COUNT:
+ reval = GET_TDES0_COCNT(desc->status);
+ break;
+ default:
+ break;
+ }
+ return reval;
+}
+
+/*!
+ \brief get the number of missed frames during receiving
+ \param[in] none
+ \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO
+ \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller
+ \retval none
+*/
+void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop)
+{
+ uint32_t temp_counter = 0U;
+
+ temp_counter = ENET_DMA_MFBOCNT;
+ *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter);
+ *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter);
+}
+
+/*!
+ \brief get the bit flag of ENET DMA descriptor
+ \param[in] desc: the descriptor pointer which users want to get flag
+ \param[in] desc_flag: the bit flag of ENET DMA descriptor,
+ only one parameter can be selected which is shown as below
+ \arg ENET_TDES0_DB: deferred
+ \arg ENET_TDES0_UFE: underflow error
+ \arg ENET_TDES0_EXD: excessive deferral
+ \arg ENET_TDES0_VFRM: VLAN frame
+ \arg ENET_TDES0_ECO: excessive collision
+ \arg ENET_TDES0_LCO: late collision
+ \arg ENET_TDES0_NCA: no carrier
+ \arg ENET_TDES0_LCA: loss of carrier
+ \arg ENET_TDES0_IPPE: IP payload error
+ \arg ENET_TDES0_FRMF: frame flushed
+ \arg ENET_TDES0_JT: jabber timeout
+ \arg ENET_TDES0_ES: error summary
+ \arg ENET_TDES0_IPHE: IP header error
+ \arg ENET_TDES0_TTMSS: transmit timestamp status
+ \arg ENET_TDES0_TCHM: the second address chained mode
+ \arg ENET_TDES0_TERM: transmit end of ring mode
+ \arg ENET_TDES0_TTSEN: transmit timestamp function enable
+ \arg ENET_TDES0_DPAD: disable adding pad
+ \arg ENET_TDES0_DCRC: disable CRC
+ \arg ENET_TDES0_FSG: first segment
+ \arg ENET_TDES0_LSG: last segment
+ \arg ENET_TDES0_INTC: interrupt on completion
+ \arg ENET_TDES0_DAV: DAV bit
+
+ \arg ENET_RDES0_PCERR: payload checksum error
+ \arg ENET_RDES0_CERR: CRC error
+ \arg ENET_RDES0_DBERR: dribble bit error
+ \arg ENET_RDES0_RERR: receive error
+ \arg ENET_RDES0_RWDT: receive watchdog timeout
+ \arg ENET_RDES0_FRMT: frame type
+ \arg ENET_RDES0_LCO: late collision
+ \arg ENET_RDES0_IPHERR: IP frame header error
+ \arg ENET_RDES0_LDES: last descriptor
+ \arg ENET_RDES0_FDES: first descriptor
+ \arg ENET_RDES0_VTAG: VLAN tag
+ \arg ENET_RDES0_OERR: overflow error
+ \arg ENET_RDES0_LERR: length error
+ \arg ENET_RDES0_SAFF: SA filter fail
+ \arg ENET_RDES0_DERR: descriptor error
+ \arg ENET_RDES0_ERRS: error summary
+ \arg ENET_RDES0_DAFF: destination address filter fail
+ \arg ENET_RDES0_DAV: descriptor available
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag)
+{
+ FlagStatus enet_flag = RESET;
+
+ if ((uint32_t)RESET != (desc->status & desc_flag)){
+ enet_flag = SET;
+ }
+
+ return enet_flag;
+}
+
+/*!
+ \brief set the bit flag of ENET DMA descriptor
+ \param[in] desc: the descriptor pointer which users want to set flag
+ \param[in] desc_flag: the bit flag of ENET DMA descriptor,
+ only one parameter can be selected which is shown as below
+ \arg ENET_TDES0_VFRM: VLAN frame
+ \arg ENET_TDES0_FRMF: frame flushed
+ \arg ENET_TDES0_TCHM: the second address chained mode
+ \arg ENET_TDES0_TERM: transmit end of ring mode
+ \arg ENET_TDES0_TTSEN: transmit timestamp function enable
+ \arg ENET_TDES0_DPAD: disable adding pad
+ \arg ENET_TDES0_DCRC: disable CRC
+ \arg ENET_TDES0_FSG: first segment
+ \arg ENET_TDES0_LSG: last segment
+ \arg ENET_TDES0_INTC: interrupt on completion
+ \arg ENET_TDES0_DAV: DAV bit
+ \arg ENET_RDES0_DAV: descriptor available
+ \param[out] none
+ \retval none
+*/
+void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag)
+{
+ desc->status |= desc_flag;
+}
+
+/*!
+ \brief clear the bit flag of ENET DMA descriptor
+ \param[in] desc: the descriptor pointer which users want to clear flag
+ \param[in] desc_flag: the bit flag of ENET DMA descriptor,
+ only one parameter can be selected which is shown as below
+ \arg ENET_TDES0_VFRM: VLAN frame
+ \arg ENET_TDES0_FRMF: frame flushed
+ \arg ENET_TDES0_TCHM: the second address chained mode
+ \arg ENET_TDES0_TERM: transmit end of ring mode
+ \arg ENET_TDES0_TTSEN: transmit timestamp function enable
+ \arg ENET_TDES0_DPAD: disable adding pad
+ \arg ENET_TDES0_DCRC: disable CRC
+ \arg ENET_TDES0_FSG: first segment
+ \arg ENET_TDES0_LSG: last segment
+ \arg ENET_TDES0_INTC: interrupt on completion
+ \arg ENET_TDES0_DAV: DAV bit
+ \arg ENET_RDES0_DAV: descriptor available
+ \param[out] none
+ \retval none
+*/
+void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag)
+{
+ desc->status &= ~desc_flag;
+}
+
+/*!
+ \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set
+ \param[in] desc: the descriptor pointer which users want to configure
+ \param[out] none
+ \retval none
+*/
+void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc)
+{
+ desc->control_buffer_size &= ~ENET_RDES1_DINTC;
+}
+
+/*!
+ \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set
+ \param[in] desc: the descriptor pointer which users want to configure
+ \param[out] none
+ \retval none
+*/
+void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc)
+{
+ desc->control_buffer_size |= ENET_RDES1_DINTC;
+}
+
+/*!
+ \brief drop current receive frame
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_rxframe_drop(void)
+{
+ /* enable reception, descriptor is owned by DMA */
+ dma_current_rxdesc->status = ENET_RDES0_DAV;
+
+ /* chained mode */
+ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
+ if(NULL != dma_current_ptp_rxdesc){
+ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
+ /* if it is the last ptp descriptor */
+ if(0U != dma_current_ptp_rxdesc->status){
+ /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
+ dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
+ }else{
+ /* ponter to the next ptp descriptor */
+ dma_current_ptp_rxdesc++;
+ }
+ }else{
+ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr);
+ }
+
+ }else{
+ /* ring mode */
+ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
+ /* if is the last descriptor in table, the next descriptor is the table header */
+ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
+ if(NULL != dma_current_ptp_rxdesc){
+ dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
+ }
+ }else{
+ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
+ dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
+ if(NULL != dma_current_ptp_rxdesc){
+ dma_current_ptp_rxdesc++;
+ }
+ }
+ }
+}
+
+/*!
+ \brief enable DMA feature
+ \param[in] feature: the feature of DMA mode,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function
+ \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function
+ \param[out] none
+ \retval none
+*/
+void enet_dma_feature_enable(uint32_t feature)
+{
+ ENET_DMA_CTL |= feature;
+}
+
+/*!
+ \brief disable DMA feature
+ \param[in] feature: the feature of DMA mode,
+ one or more parameters can be selected which are shown as below
+ \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function
+ \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function
+ \param[out] none
+ \retval none
+*/
+void enet_dma_feature_disable(uint32_t feature)
+{
+ ENET_DMA_CTL &= ~feature;
+}
+
+/*!
+ \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function
+ \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_DMA_TX: DMA Tx descriptors
+ \arg ENET_DMA_RX: DMA Rx descriptors
+ \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
+{
+ uint32_t num = 0U, count = 0U, maxsize = 0U;
+ uint32_t desc_status = 0U, desc_bufsize = 0U;
+ enet_descriptors_struct *desc, *desc_tab;
+ uint8_t *buf;
+
+ /* if want to initialize DMA Tx descriptors */
+ if (ENET_DMA_TX == direction){
+ /* save a copy of the DMA Tx descriptors */
+ desc_tab = txdesc_tab;
+ buf = &tx_buff[0][0];
+ count = ENET_TXBUF_NUM;
+ maxsize = ENET_TXBUF_SIZE;
+
+ /* select chain mode, and enable transmit timestamp function */
+ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN;
+
+ /* configure DMA Tx descriptor table address register */
+ ENET_DMA_TDTADDR = (uint32_t)desc_tab;
+ dma_current_txdesc = desc_tab;
+ dma_current_ptp_txdesc = desc_ptptab;
+ }else{
+ /* if want to initialize DMA Rx descriptors */
+ /* save a copy of the DMA Rx descriptors */
+ desc_tab = rxdesc_tab;
+ buf = &rx_buff[0][0];
+ count = ENET_RXBUF_NUM;
+ maxsize = ENET_RXBUF_SIZE;
+
+ /* enable receiving */
+ desc_status = ENET_RDES0_DAV;
+ /* select receive chained mode and set buffer1 size */
+ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE;
+
+ /* configure DMA Rx descriptor table address register */
+ ENET_DMA_RDTADDR = (uint32_t)desc_tab;
+ dma_current_rxdesc = desc_tab;
+ dma_current_ptp_rxdesc = desc_ptptab;
+ }
+
+ /* configure each descriptor */
+ for(num = 0U; num < count; num++){
+ /* get the pointer to the next descriptor of the descriptor table */
+ desc = desc_tab + num;
+
+ /* configure descriptors */
+ desc->status = desc_status;
+ desc->control_buffer_size = desc_bufsize;
+ desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
+
+ /* if is not the last descriptor */
+ if(num < (count - 1U)){
+ /* configure the next descriptor address */
+ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U);
+ }else{
+ /* when it is the last descriptor, the next descriptor address
+ equals to first descriptor address in descriptor table */
+ desc->buffer2_next_desc_addr = (uint32_t)desc_tab;
+ }
+ /* set desc_ptptab equal to desc_tab */
+ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
+ (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
+ }
+ /* when it is the last ptp descriptor, preserve the first descriptor
+ address of desc_ptptab in ptp descriptor status */
+ (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
+}
+
+/*!
+ \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function
+ \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_DMA_TX: DMA Tx descriptors
+ \arg ENET_DMA_RX: DMA Rx descriptors
+ \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab)
+{
+ uint32_t num = 0U, count = 0U, maxsize = 0U;
+ uint32_t desc_status = 0U, desc_bufsize = 0U;
+ enet_descriptors_struct *desc, *desc_tab;
+ uint8_t *buf;
+
+ /* configure descriptor skip length */
+ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL;
+ ENET_DMA_BCTL |= DMA_BCTL_DPSL(0);
+
+ /* if want to initialize DMA Tx descriptors */
+ if (ENET_DMA_TX == direction){
+ /* save a copy of the DMA Tx descriptors */
+ desc_tab = txdesc_tab;
+ buf = &tx_buff[0][0];
+ count = ENET_TXBUF_NUM;
+ maxsize = ENET_TXBUF_SIZE;
+
+ /* select ring mode, and enable transmit timestamp function */
+ desc_status = ENET_TDES0_TTSEN;
+
+ /* configure DMA Tx descriptor table address register */
+ ENET_DMA_TDTADDR = (uint32_t)desc_tab;
+ dma_current_txdesc = desc_tab;
+ dma_current_ptp_txdesc = desc_ptptab;
+ }else{
+ /* if want to initialize DMA Rx descriptors */
+ /* save a copy of the DMA Rx descriptors */
+ desc_tab = rxdesc_tab;
+ buf = &rx_buff[0][0];
+ count = ENET_RXBUF_NUM;
+ maxsize = ENET_RXBUF_SIZE;
+
+ /* enable receiving */
+ desc_status = ENET_RDES0_DAV;
+ /* select receive ring mode and set buffer1 size */
+ desc_bufsize = (uint32_t)ENET_RXBUF_SIZE;
+
+ /* configure DMA Rx descriptor table address register */
+ ENET_DMA_RDTADDR = (uint32_t)desc_tab;
+ dma_current_rxdesc = desc_tab;
+ dma_current_ptp_rxdesc = desc_ptptab;
+ }
+
+ /* configure each descriptor */
+ for(num = 0U; num < count; num++){
+ /* get the pointer to the next descriptor of the descriptor table */
+ desc = desc_tab + num;
+
+ /* configure descriptors */
+ desc->status = desc_status;
+ desc->control_buffer_size = desc_bufsize;
+ desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]);
+
+ /* when it is the last descriptor */
+ if(num == (count - 1U)){
+ if (ENET_DMA_TX == direction){
+ /* configure transmit end of ring mode */
+ desc->status |= ENET_TDES0_TERM;
+ }else{
+ /* configure receive end of ring mode */
+ desc->control_buffer_size |= ENET_RDES1_RERM;
+ }
+ }
+ /* set desc_ptptab equal to desc_tab */
+ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr;
+ (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr;
+ }
+ /* when it is the last ptp descriptor, preserve the first descriptor
+ address of desc_ptptab in ptp descriptor status */
+ (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab;
+}
+
+/*!
+ \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode
+ \param[in] bufsize: the size of buffer which is the parameter in function
+ \param[out] timestamp: pointer to the table which stores the timestamp high and low
+ \param[out] buffer: pointer to the application buffer
+ note -- if the input is NULL, user should copy data in application by himself
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[])
+{
+ uint32_t offset = 0U, size = 0U;
+
+ /* the descriptor is busy due to own by the DMA */
+ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){
+ return ERROR;
+ }
+
+ /* if buffer pointer is null, indicates that users has copied data in application */
+ if(NULL != buffer){
+ /* if no error occurs, and the frame uses only one descriptor */
+ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) &&
+ ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) &&
+ ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){
+
+ /* get the frame length except CRC */
+ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U;
+
+ /* to avoid situation that the frame size exceeds the buffer length */
+ if(size > bufsize){
+ return ERROR;
+ }
+
+ /* copy data from Rx buffer to application buffer */
+ for(offset = 0U; offset < size; offset++){
+ (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset));
+ }
+
+ }else{
+ return ERROR;
+ }
+ }
+ /* copy timestamp value from Rx descriptor to application array */
+ timestamp[0] = dma_current_rxdesc->buffer1_addr;
+ timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr;
+
+ dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ;
+ dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr;
+
+ /* enable reception, descriptor is owned by DMA */
+ dma_current_rxdesc->status = ENET_RDES0_DAV;
+
+ /* check Rx buffer unavailable flag status */
+ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){
+ /* clear RBU flag */
+ ENET_DMA_STAT = ENET_DMA_STAT_RBU;
+ /* resume DMA reception by writing to the RPEN register*/
+ ENET_DMA_RPEN = 0U;
+ }
+
+
+ /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */
+ /* chained mode */
+ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){
+ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr);
+ /* if it is the last ptp descriptor */
+ if(0U != dma_current_ptp_rxdesc->status){
+ /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
+ dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
+ }else{
+ /* ponter to the next ptp descriptor */
+ dma_current_ptp_rxdesc++;
+ }
+ }else{
+ /* ring mode */
+ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){
+ /* if is the last descriptor in table, the next descriptor is the table header */
+ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR);
+ /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table,
+ use the same table with RxDMA descriptor */
+ dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status);
+ }else{
+ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
+ dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
+ dma_current_ptp_rxdesc ++;
+ }
+ }
+
+ return SUCCESS;
+}
+
+/*!
+ \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode
+ \param[in] buffer: pointer on the application buffer
+ note -- if the input is NULL, user should copy data in application by himself
+ \param[in] length: the length of frame data to be transmitted
+ \param[out] timestamp: pointer to the table which stores the timestamp high and low
+ note -- if the input is NULL, timestamp is ignored
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[])
+{
+ uint32_t offset = 0U, timeout = 0U;
+ uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag;
+
+ /* the descriptor is busy due to own by the DMA */
+ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){
+ return ERROR;
+ }
+
+ /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */
+ if(length > ENET_MAX_FRAME_SIZE){
+ return ERROR;
+ }
+
+ /* if buffer pointer is null, indicates that users has handled data in application */
+ if(NULL != buffer){
+ /* copy frame data from application buffer to Tx buffer */
+ for(offset = 0U; offset < length; offset++){
+ (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset));
+ }
+ }
+ /* set the frame length */
+ dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF);
+ /* set the segment of frame, frame is transmitted in one descriptor */
+ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG;
+ /* enable the DMA transmission */
+ dma_current_txdesc->status |= ENET_TDES0_DAV;
+
+ /* check Tx buffer unavailable flag status */
+ dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU);
+ dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU);
+
+ if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){
+ /* clear TBU and TU flag */
+ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag);
+ /* resume DMA transmission by writing to the TPEN register*/
+ ENET_DMA_TPEN = 0U;
+ }
+
+ /* if timestamp pointer is null, indicates that users don't care timestamp in application */
+ if(NULL != timestamp){
+ /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */
+ do{
+ tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS);
+ timeout++;
+ }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO));
+
+ /* return ERROR due to timeout */
+ if(ENET_DELAY_TO == timeout){
+ return ERROR;
+ }
+
+ /* clear the ENET_TDES0_TTMSS flag */
+ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS;
+ /* get the timestamp value of the transmit frame */
+ timestamp[0] = dma_current_txdesc->buffer1_addr;
+ timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr;
+ }
+ dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ;
+ dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr;
+
+ /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */
+ /* chained mode */
+ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){
+ dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr);
+ /* if it is the last ptp descriptor */
+ if(0U != dma_current_ptp_txdesc->status){
+ /* pointer back to the first ptp descriptor address in the desc_ptptab list address */
+ dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
+ }else{
+ /* ponter to the next ptp descriptor */
+ dma_current_ptp_txdesc++;
+ }
+ }else{
+ /* ring mode */
+ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){
+ /* if is the last descriptor in table, the next descriptor is the table header */
+ dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR);
+ /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table,
+ use the same table with TxDMA descriptor */
+ dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status);
+ }else{
+ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */
+ dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL));
+ dma_current_ptp_txdesc ++;
+ }
+ }
+ return SUCCESS;
+}
+
+/*!
+ \brief wakeup frame filter register pointer reset
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_wum_filter_register_pointer_reset(void)
+{
+ ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR;
+}
+
+/*!
+ \brief set the remote wakeup frame registers
+ \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total)
+ \param[out] none
+ \retval none
+*/
+void enet_wum_filter_config(uint32_t pdata[])
+{
+ uint32_t num = 0U;
+
+ /* configure ENET_MAC_RWFF register */
+ for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){
+ ENET_MAC_RWFF = pdata[num];
+ }
+}
+
+/*!
+ \brief enable wakeup management features
+ \param[in] feature: one or more parameters can be selected which are shown as below
+ \arg ENET_WUM_POWER_DOWN: power down mode
+ \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception
+ \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception
+ \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame
+ \param[out] none
+ \retval none
+*/
+void enet_wum_feature_enable(uint32_t feature)
+{
+ ENET_MAC_WUM |= feature;
+}
+
+/*!
+ \brief disable wakeup management features
+ \param[in] feature: one or more parameters can be selected which are shown as below
+ \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception
+ \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception
+ \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame
+ \param[out] none
+ \retval none
+*/
+void enet_wum_feature_disable(uint32_t feature)
+{
+ ENET_MAC_WUM &= (~feature);
+}
+
+/*!
+ \brief reset the MAC statistics counters
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_msc_counters_reset(void)
+{
+ /* reset all counters */
+ ENET_MSC_CTL |= ENET_MSC_CTL_CTR;
+}
+
+/*!
+ \brief enable the MAC statistics counter features
+ \param[in] feature: one or more parameters can be selected which are shown as below
+ \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover
+ \arg ENET_MSC_RESET_ON_READ: reset on read
+ \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze
+ \param[out] none
+ \retval none
+*/
+void enet_msc_feature_enable(uint32_t feature)
+{
+ ENET_MSC_CTL |= feature;
+}
+
+/*!
+ \brief disable the MAC statistics counter features
+ \param[in] feature: one or more parameters can be selected which are shown as below
+ \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover
+ \arg ENET_MSC_RESET_ON_READ: reset on read
+ \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze
+ \param[out] none
+ \retval none
+*/
+void enet_msc_feature_disable(uint32_t feature)
+{
+ ENET_MSC_CTL &= (~feature);
+}
+
+/*!
+ \brief get MAC statistics counter
+ \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum,
+ only one parameter can be selected which is shown as below
+ \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter
+ \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter
+ \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter
+ \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter
+ \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter
+ \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter
+ \param[out] none
+ \retval the MSC counter value
+*/
+uint32_t enet_msc_counters_get(enet_msc_counter_enum counter)
+{
+ uint32_t reval;
+
+ reval = REG32((ENET + (uint32_t)counter));
+
+ return reval;
+}
+
+/*!
+ \brief change subsecond to nanosecond
+ \param[in] subsecond: subsecond value
+ \param[out] none
+ \retval the nanosecond value
+*/
+uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond)
+{
+ uint64_t val = subsecond * 1000000000Ull;
+ val >>= 31;
+ return (uint32_t)val;
+}
+
+/*!
+ \brief change nanosecond to subsecond
+ \param[in] nanosecond: nanosecond value
+ \param[out] none
+ \retval the subsecond value
+*/
+uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond)
+{
+ uint64_t val = nanosecond * 0x80000000Ull;
+ val /= 1000000000U;
+ return (uint32_t)val;
+}
+
+/*!
+ \brief enable the PTP features
+ \param[in] feature: the feature of ENET PTP mode
+ one or more parameters can be selected which are shown as below
+ \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames
+ \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_feature_enable(uint32_t feature)
+{
+ ENET_PTP_TSCTL |= feature;
+}
+
+/*!
+ \brief disable the PTP features
+ \param[in] feature: the feature of ENET PTP mode
+ one or more parameters can be selected which are shown as below
+ \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames
+ \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_feature_disable(uint32_t feature)
+{
+ ENET_PTP_TSCTL &= ~feature;
+}
+
+/*!
+ \brief configure the PTP timestamp function
+ \param[in] func: only one parameter can be selected which is shown as below
+ \arg ENET_PTP_ADDEND_UPDATE: addend register update
+ \arg ENET_PTP_SYSTIME_UPDATE: timestamp update
+ \arg ENET_PTP_SYSTIME_INIT: timestamp initialize
+ \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating
+ \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+
+ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func)
+{
+ uint32_t temp_config = 0U, temp_state = 0U;
+ uint32_t timeout = 0U;
+ ErrStatus enet_state = SUCCESS;
+
+ switch(func){
+ case ENET_PTP_ADDEND_UPDATE:
+ /* this bit must be read as zero before application set it */
+ do{
+ temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU;
+ timeout++;
+ }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
+ /* return ERROR due to timeout */
+ if(ENET_DELAY_TO == timeout){
+ enet_state = ERROR;
+ }else{
+ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU;
+ }
+ break;
+ case ENET_PTP_SYSTIME_UPDATE:
+ /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */
+ do{
+ temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI);
+ timeout++;
+ }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
+ /* return ERROR due to timeout */
+ if(ENET_DELAY_TO == timeout){
+ enet_state = ERROR;
+ }else{
+ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU;
+ }
+ break;
+ case ENET_PTP_SYSTIME_INIT:
+ /* this bit must be read as zero before application set it */
+ do{
+ temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI;
+ timeout++;
+ }while((RESET != temp_state) && (timeout < ENET_DELAY_TO));
+ /* return ERROR due to timeout */
+ if(ENET_DELAY_TO == timeout){
+ enet_state = ERROR;
+ }else{
+ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI;
+ }
+ break;
+ default:
+ temp_config = (uint32_t)func & (~BIT(31));
+ if(RESET != ((uint32_t)func & BIT(31))){
+ ENET_PTP_TSCTL |= temp_config;
+ }else{
+ ENET_PTP_TSCTL &= ~temp_config;
+ }
+ break;
+ }
+
+ return enet_state;
+}
+
+/*!
+ \brief configure system time subsecond increment value
+ \param[in] subsecond: the value will be added to the subsecond value of system time,
+ this value must be between 0 and 0xFF
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_subsecond_increment_config(uint32_t subsecond)
+{
+ ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond);
+}
+
+/*!
+ \brief adjusting the clock frequency only in fine update mode
+ \param[in] add: the value will be added to the accumulator register to achieve time synchronization
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_timestamp_addend_config(uint32_t add)
+{
+ ENET_PTP_TSADDEND = add;
+}
+
+/*!
+ \brief initialize or add/subtract to second of the system time
+ \param[in] sign: timestamp update positive or negative sign,
+ only one parameter can be selected which is shown as below
+ \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time
+ \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time
+ \param[in] second: initializing or adding/subtracting to second of the system time
+ \param[in] subsecond: the current subsecond of the system time
+ with 0.46 ns accuracy if required accuracy is 20 ns
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond)
+{
+ ENET_PTP_TSUH = second;
+ ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond);
+}
+
+/*!
+ \brief configure the expected target time
+ \param[in] second: the expected target second time
+ \param[in] nanosecond: the expected target nanosecond time (signed)
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond)
+{
+ ENET_PTP_ETH = second;
+ ENET_PTP_ETL = nanosecond;
+}
+
+/*!
+ \brief get the current system time
+ \param[in] none
+ \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains
+ parameters of PTP system time
+ members of the structure and the member values are shown as below:
+ second: 0x0 - 0xFFFF FFFF
+ nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31
+ sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
+ \retval none
+*/
+void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct)
+{
+ uint32_t temp_sec = 0U, temp_subs = 0U;
+
+ /* get the value of sysytem time registers */
+ temp_sec = (uint32_t)ENET_PTP_TSH;
+ temp_subs = (uint32_t)ENET_PTP_TSL;
+
+ /* get sysytem time and construct the enet_ptp_systime_struct structure */
+ systime_struct->second = temp_sec;
+ systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs);
+ systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond);
+ systime_struct->sign = GET_PTP_TSL_STS(temp_subs);
+}
+
+/*!
+ \brief configure and start PTP timestamp counter
+ \param[in] updatemethod: method for updating
+ \arg ENET_PTP_FINEMODE: fine correction method
+ \arg ENET_PTP_COARSEMODE: coarse correction method
+ \param[in] init_sec: second value for initializing system time
+ \param[in] init_subsec: subsecond value for initializing system time
+ \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used)
+ \param[in] accuracy_cfg: the value to be added to the subsecond value of system time
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg)
+{
+ /* mask the timestamp trigger interrupt */
+ enet_interrupt_disable(ENET_MAC_INT_TMSTIM);
+
+ /* enable timestamp */
+ enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP);
+
+ /* configure system time subsecond increment based on the PTP clock frequency */
+ enet_ptp_subsecond_increment_config(accuracy_cfg);
+
+ if(ENET_PTP_FINEMODE == updatemethod){
+ /* fine correction method: configure the timestamp addend, then update */
+ enet_ptp_timestamp_addend_config(carry_cfg);
+ enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
+ /* wait until update is completed */
+ while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){
+ }
+ }
+
+ /* choose the fine correction method */
+ enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod);
+
+ /* initialize the system time */
+ enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec);
+ enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
+}
+
+/*!
+ \brief adjust frequency in fine method by configure addend register
+ \param[in] carry_cfg: the value to be added to the accumulator register
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg)
+{
+ /* re-configure the timestamp addend, then update */
+ enet_ptp_timestamp_addend_config((uint32_t)carry_cfg);
+ enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
+}
+
+/*!
+ \brief update system time in coarse method
+ \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains
+ parameters of PTP system time
+ members of the structure and the member values are shown as below:
+ second: 0x0 - 0xFFFF FFFF
+ nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31
+ sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct)
+{
+ uint32_t subsecond_val;
+ uint32_t carry_cfg;
+
+ subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
+
+ /* save the carry_cfg value */
+ carry_cfg = ENET_PTP_TSADDEND_TMSA;
+
+ /* update the system time */
+ enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
+ enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE);
+
+ /* wait until the update is completed */
+ while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){
+ }
+
+ /* write back the carry_cfg value, then update */
+ enet_ptp_timestamp_addend_config(carry_cfg);
+ enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE);
+}
+
+/*!
+ \brief set system time in fine method
+ \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains
+ parameters of PTP system time
+ members of the structure and the member values are shown as below:
+ second: 0x0 - 0xFFFF FFFF
+ nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31
+ sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE
+ \param[out] none
+ \retval none
+*/
+void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct)
+{
+ uint32_t subsecond_val;
+
+ subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond);
+
+ /* initialize the system time */
+ enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val);
+ enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT);
+
+ /* wait until the system time initialzation finished */
+ while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){
+ }
+}
+
+/*!
+ \brief get the ptp flag status
+ \param[in] flag: ptp flag status to be checked
+ \arg ENET_PTP_ADDEND_UPDATE: addend register update
+ \arg ENET_PTP_SYSTIME_UPDATE: timestamp update
+ \arg ENET_PTP_SYSTIME_INIT: timestamp initialize
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus enet_ptp_flag_get(uint32_t flag)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){
+ bitstatus = SET;
+ }
+
+ return bitstatus;
+}
+
+/*!
+ \brief reset the ENET initpara struct, call it before using enet_initpara_config()
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void enet_initpara_reset(void)
+{
+ enet_initpara.option_enable = 0U;
+ enet_initpara.forward_frame = 0U;
+ enet_initpara.dmabus_mode = 0U;
+ enet_initpara.dma_maxburst = 0U;
+ enet_initpara.dma_arbitration = 0U;
+ enet_initpara.store_forward_mode = 0U;
+ enet_initpara.dma_function = 0U;
+ enet_initpara.vlan_config = 0U;
+ enet_initpara.flow_control = 0U;
+ enet_initpara.hashtable_high = 0U;
+ enet_initpara.hashtable_low = 0U;
+ enet_initpara.framesfilter_mode = 0U;
+ enet_initpara.halfduplex_param = 0U;
+ enet_initpara.timer_config = 0U;
+ enet_initpara.interframegap = 0U;
+}
+
+/*!
+ \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init()
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void enet_default_init(void)
+{
+ uint32_t reg_value = 0U;
+
+ /* MAC */
+ /* configure ENET_MAC_CFG register */
+ reg_value = ENET_MAC_CFG;
+ reg_value &= MAC_CFG_MASK;
+ reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \
+ | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \
+ | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \
+ | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \
+ | ENET_DEFERRALCHECK_DISABLE \
+ | ENET_AUTO_PADCRC_DROP_DISABLE \
+ | ENET_CHECKSUMOFFLOAD_DISABLE;
+ ENET_MAC_CFG = reg_value;
+
+ /* configure ENET_MAC_FRMF register */
+ ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \
+ |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \
+ |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \
+ |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE;
+
+ /* configure ENET_MAC_HLH, ENET_MAC_HLL register */
+ ENET_MAC_HLH = 0x0U;
+
+ ENET_MAC_HLL = 0x0U;
+
+ /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */
+ reg_value = ENET_MAC_FCTL;
+ reg_value &= MAC_FCTL_MASK;
+ reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \
+ |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \
+ |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE;
+ ENET_MAC_FCTL = reg_value;
+
+ /* configure ENET_MAC_VLT register */
+ ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0);
+
+ /* DMA */
+ /* configure ENET_DMA_CTL register */
+ reg_value = ENET_DMA_CTL;
+ reg_value &= DMA_CTL_MASK;
+ reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \
+ |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \
+ |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \
+ |ENET_SECONDFRAME_OPT_DISABLE;
+ ENET_DMA_CTL = reg_value;
+
+ /* configure ENET_DMA_BCTL register */
+ reg_value = ENET_DMA_BCTL;
+ reg_value &= DMA_BCTL_MASK;
+ reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \
+ |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \
+ |ENET_FIXED_BURST_ENABLE;
+ ENET_DMA_BCTL = reg_value;
+}
+
+#ifndef USE_DELAY
+/*!
+ \brief insert a delay time
+ \param[in] ncount: specifies the delay time length
+ \param[out] none
+ \param[out] none
+*/
+static void enet_delay(uint32_t ncount)
+{
+ __IO uint32_t delay_time = 0U;
+
+ for(delay_time = ncount; delay_time != 0U; delay_time--){
+ }
+}
+#endif /* USE_DELAY */
+
+#endif /* GD32F10X_CL */
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c
new file mode 100644
index 0000000..cbc9e8a
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c
@@ -0,0 +1,642 @@
+/*!
+ \file gd32f10x_exmc.c
+ \brief EXMC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_exmc.h"
+
+/* EXMC bank0 register reset value */
+#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU)
+#define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U)
+#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
+#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU)
+
+/* EXMC bank1/2 register reset mask*/
+#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U)
+#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U)
+#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
+#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
+
+/* EXMC bank3 register reset mask*/
+#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U)
+#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U)
+#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
+#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
+#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU)
+
+/* EXMC register bit offset */
+#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
+#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U)
+#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U)
+#define SNCTL_WREN_OFFSET ((uint32_t)12U)
+#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
+#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U)
+#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
+
+#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
+#define SNTCFG_DSET_OFFSET ((uint32_t)8U)
+#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
+
+#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U)
+#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U)
+#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U)
+
+#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U)
+#define NPCTL_ECCEN_OFFSET ((uint32_t)6U)
+
+#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U)
+#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U)
+#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U)
+
+#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U)
+#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U)
+#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U)
+
+#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U)
+#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U)
+#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U)
+
+#define INTEN_INTS_OFFSET ((uint32_t)3U)
+
+/*!
+ \brief deinitialize EXMC NOR/SRAM region
+ \param[in] norsram_region: select the region of bank0
+ \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
+ \param[out] none
+ \retval none
+*/
+void exmc_norsram_deinit(uint32_t norsram_region)
+{
+ /* reset the registers */
+ if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
+ EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
+ }else{
+ EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET;
+ }
+
+ EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
+ EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET;
+}
+
+/*!
+ \brief initialize EXMC NOR/SRAM region
+ \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
+ norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3
+ write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE
+ extended_mode: ENABLE or DISABLE
+ asyn_wait: ENABLE or DISABLE
+ nwait_signal: ENABLE or DISABLE
+ memory_write: ENABLE or DISABLE
+ nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING
+ wrap_burst_mode: ENABLE or DISABLE
+ nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
+ burst_mode: ENABLE or DISABLE
+ databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
+ memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
+ address_data_mux: ENABLE or DISABLE
+ read_write_timing: struct exmc_norsram_timing_parameter_struct set the time
+ write_timing: struct exmc_norsram_timing_parameter_struct set the time
+ \param[out] none
+ \retval none
+*/
+void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
+{
+ uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U;
+
+ /* get the register value */
+ snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
+
+ /* clear relative bits */
+ snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
+ EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN |
+ EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR |
+ EXMC_SNCTL_NRMUX ));
+
+ snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
+ exmc_norsram_init_struct->memory_type |
+ exmc_norsram_init_struct->databus_width |
+ (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
+ exmc_norsram_init_struct->nwait_polarity |
+ (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
+ exmc_norsram_init_struct->nwait_config |
+ (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
+ (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
+ (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
+ (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
+ exmc_norsram_init_struct->write_mode;
+
+ sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
+ (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
+ (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
+ (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )|
+ exmc_norsram_init_struct->read_write_timing->syn_clk_division |
+ exmc_norsram_init_struct->read_write_timing->syn_data_latency |
+ exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
+
+ /* nor flash access enable */
+ if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
+ snctl |= (uint32_t)EXMC_SNCTL_NREN;
+ }
+
+ /* extended mode configure */
+ if(ENABLE == exmc_norsram_init_struct->extended_mode){
+ snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) |
+ (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)|
+ (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) |
+ exmc_norsram_init_struct->write_timing->asyn_access_mode);
+ }else{
+ snwtcfg = BANK0_SNWTCFG_RESET;
+ }
+
+ /* configure the registers */
+ EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
+ EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
+ EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg;
+}
+
+/*!
+ \brief initialize the struct exmc_norsram_parameter_struct
+ \param[in] none
+ \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer
+ \retval none
+*/
+void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
+{
+ /* configure the structure with default value */
+ exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
+ exmc_norsram_init_struct->address_data_mux = ENABLE;
+ exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
+ exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B;
+ exmc_norsram_init_struct->burst_mode = DISABLE;
+ exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
+ exmc_norsram_init_struct->wrap_burst_mode = DISABLE;
+ exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
+ exmc_norsram_init_struct->memory_write = ENABLE;
+ exmc_norsram_init_struct->nwait_signal = ENABLE;
+ exmc_norsram_init_struct->extended_mode = DISABLE;
+ exmc_norsram_init_struct->asyn_wait = DISABLE;
+ exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE;
+
+ /* read/write timing configure */
+ exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
+ exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
+ exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
+ exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
+ exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK;
+ exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
+ exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
+
+ /* write timing configure, when extended mode is used */
+ exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
+ exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
+ exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
+ exmc_norsram_init_struct->write_timing->bus_latency = 0xFU;
+ exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
+}
+
+/*!
+ \brief enable EXMC NOR/PSRAM bank region
+ \param[in] norsram_region: specifie the region of NOR/PSRAM bank
+ \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
+ \param[out] none
+ \retval none
+*/
+void exmc_norsram_enable(uint32_t norsram_region)
+{
+ EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
+}
+
+/*!
+ \brief disable EXMC NOR/PSRAM bank region
+ \param[in] norsram_region: specifie the region of NOR/PSRAM Bank
+ \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
+ \param[out] none
+ \retval none
+*/
+void exmc_norsram_disable(uint32_t norsram_region)
+{
+ EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
+}
+
+/*!
+ \brief deinitialize EXMC NAND bank
+ \param[in] nand_bank: select the bank of NAND
+ \arg EXMC_BANKx_NAND(x=1..2)
+ \param[out] none
+ \retval none
+*/
+void exmc_nand_deinit(uint32_t nand_bank)
+{
+ /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */
+ EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET;
+ EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET;
+ EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET;
+ EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET;
+}
+
+/*!
+ \brief initialize EXMC NAND bank
+ \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter
+ nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND
+ ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096
+ atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16
+ ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16
+ ecc_logic: ENABLE or DISABLE
+ databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B
+ wait_feature: ENABLE or DISABLE
+ common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
+ attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
+ \param[out] none
+ \retval none
+*/
+void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
+{
+ uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U;
+
+ npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)|
+ EXMC_NPCTL_NDTP |
+ exmc_nand_init_struct->databus_width |
+ (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)|
+ exmc_nand_init_struct->ecc_size |
+ exmc_nand_init_struct->ctr_latency |
+ exmc_nand_init_struct->atr_latency;
+
+ npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) |
+ (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
+ ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
+ (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
+
+ npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
+ (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
+ ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) |
+ (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
+
+ /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
+ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
+ EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
+ EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
+}
+
+/*!
+ \brief initialize the struct exmc_nand_init_struct
+ \param[in] none
+ \param[out] the initialized struct exmc_nand_init_struct pointer
+ \retval none
+*/
+void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
+{
+ /* configure the structure with default value */
+ exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND;
+ exmc_nand_init_struct->wait_feature = DISABLE;
+ exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B;
+ exmc_nand_init_struct->ecc_logic = DISABLE;
+ exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES;
+ exmc_nand_init_struct->ctr_latency = 0x0U;
+ exmc_nand_init_struct->atr_latency = 0x0U;
+ exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU;
+ exmc_nand_init_struct->common_space_timing->waittime = 0xFCU;
+ exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU;
+ exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU;
+ exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU;
+ exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU;
+ exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU;
+ exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
+}
+
+/*!
+ \brief enable NAND bank
+ \param[in] nand_bank: specifie the NAND bank
+ \arg EXMC_BANKx_NAND(x=1,2)
+ \param[out] none
+ \retval none
+*/
+void exmc_nand_enable(uint32_t nand_bank)
+{
+ EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN;
+}
+
+/*!
+ \brief disable NAND bank
+ \param[in] nand_bank: specifie the NAND bank
+ \arg EXMC_BANKx_NAND(x=1,2)
+ \param[out] none
+ \retval none
+*/
+void exmc_nand_disable(uint32_t nand_bank)
+{
+ EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN;
+}
+
+/*!
+ \brief enable or disable the EXMC NAND ECC function
+ \param[in] nand_bank: specifie the NAND bank
+ \arg EXMC_BANKx_NAND(x=1,2)
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue)
+{
+ if (ENABLE == newvalue){
+ /* enable the selected NAND bank ECC function */
+ EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN;
+ }else{
+ /* disable the selected NAND bank ECC function */
+ EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN;
+ }
+}
+
+/*!
+ \brief get the EXMC ECC value
+ \param[in] nand_bank: specifie the NAND bank
+ \arg EXMC_BANKx_NAND(x=1,2)
+ \param[out] none
+ \retval the error correction code(ECC) value
+*/
+uint32_t exmc_ecc_get(uint32_t nand_bank)
+{
+ return (EXMC_NECC(nand_bank));
+}
+
+/*!
+ \brief deinitialize EXMC PC card bank
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void exmc_pccard_deinit(void)
+{
+ /* EXMC_BANK3_PCCARD */
+ EXMC_NPCTL3 = BANK3_NPCTL_RESET;
+ EXMC_NPINTEN3 = BANK3_NPINTEN_RESET;
+ EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET;
+ EXMC_NPATCFG3 = BANK3_NPATCFG_RESET;
+ EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET;
+}
+
+/*!
+ \brief initialize EXMC PC card bank
+ \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter
+ atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16
+ ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16
+ wait_feature: ENABLE or DISABLE
+ common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
+ attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
+ io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time
+ \param[out] none
+ \retval none
+*/
+void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
+{
+ /* configure the EXMC bank3 PC card control register */
+ EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
+ EXMC_NAND_DATABUS_WIDTH_16B |
+ exmc_pccard_init_struct->ctr_latency |
+ exmc_pccard_init_struct->atr_latency ;
+
+ /* configure the EXMC bank3 PC card common space timing configuration register */
+ EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) |
+ (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
+ ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
+ (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
+
+ /* configure the EXMC bank3 PC card attribute space timing configuration register */
+ EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
+ (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
+ ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )|
+ (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
+
+ /* configure the EXMC bank3 PC card io space timing configuration register */
+ EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) |
+ (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) |
+ ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )|
+ ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ );
+}
+
+/*!
+ \brief initialize the struct exmc_pccard_parameter_struct
+ \param[in] none
+ \param[out] the initialized struct exmc_pccard_parameter_struct pointer
+ \retval none
+*/
+void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
+{
+ /* configure the structure with default value */
+ exmc_pccard_init_struct->wait_feature = DISABLE;
+ exmc_pccard_init_struct->ctr_latency = 0x0U;
+ exmc_pccard_init_struct->atr_latency = 0x0U;
+ exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU;
+ exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU;
+ exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU;
+ exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU;
+ exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU;
+ exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU;
+ exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU;
+ exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
+ exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU;
+ exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU;
+ exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU;
+ exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU;
+}
+
+/*!
+ \brief enable PC Card Bank
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void exmc_pccard_enable(void)
+{
+ EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN;
+}
+
+/*!
+ \brief disable PC Card Bank
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void exmc_pccard_disable(void)
+{
+ EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN;
+}
+
+/*!
+ \brief enable EXMC interrupt
+ \param[in] bank: specifies the NAND bank, PC card bank
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_BANK1_NAND: the NAND bank1
+ \arg EXMC_BANK2_NAND: the NAND bank2
+ \arg EXMC_BANK3_PCCARD: the PC card bank
+ \param[in] interrupt_source: specify get which interrupt flag
+ one or more parameters can be selected which is shown as below:
+ \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
+ \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
+ \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
+ \param[out] none
+ \retval none
+*/
+void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source)
+{
+ /* NAND bank1, bank2 or PC card bank3 */
+ EXMC_NPINTEN(bank) |= interrupt_source;
+}
+
+/*!
+ \brief disable EXMC interrupt
+ \param[in] bank: specifies the NAND bank, PC card bank
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_BANK1_NAND: the NAND bank1
+ \arg EXMC_BANK2_NAND: the NAND bank2
+ \arg EXMC_BANK3_PCCARD: the PC card bank
+ \param[in] interrupt_source: specify get which interrupt flag
+ one or more parameters can be selected which is shown as below:
+ \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
+ \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
+ \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
+ \param[out] none
+ \retval none
+*/
+void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source)
+{
+ /* NAND bank1,bank2 or PC card bank3 */
+ EXMC_NPINTEN(bank) &= ~interrupt_source;
+}
+
+/*!
+ \brief check EXMC flag is set or not
+ \param[in] bank: specifies the NAND bank, PC card bank
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_BANK1_NAND: the NAND bank1
+ \arg EXMC_BANK2_NAND: the NAND bank2
+ \arg EXMC_BANK3_PCCARD: the PC Card bank
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
+ \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
+ \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
+ \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag)
+{
+ uint32_t status = 0x00000000U;
+
+ /* NAND bank1,bank2 or PC card bank3 */
+ status = EXMC_NPINTEN(bank);
+
+ if ((status & flag) != (uint32_t)flag ){
+ /* flag is reset */
+ return RESET;
+ }else{
+ /* flag is set */
+ return SET;
+ }
+}
+
+/*!
+ \brief clear EXMC flag
+ \param[in] bank: specifie the NAND bank, PCCARD bank
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_BANK1_NAND: the NAND bank1
+ \arg EXMC_BANK2_NAND: the NAND bank2
+ \arg EXMC_BANK3_PCCARD: the PC card bank
+ \param[in] flag: specify get which flag
+ one or more parameters can be selected which is shown as below:
+ \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
+ \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
+ \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
+ \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
+ \param[out] none
+ \retval none
+*/
+void exmc_flag_clear(uint32_t bank, uint32_t flag)
+{
+ /* NAND bank1,bank2 or PC card bank3 */
+ EXMC_NPINTEN(bank) &= ~flag;
+}
+
+/*!
+ \brief check EXMC interrupt flag is set or not
+ \param[in] bank: specifies the NAND bank, PC card bank
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_BANK1_NAND: the NAND bank1
+ \arg EXMC_BANK2_NAND: the NAND bank2
+ \arg EXMC_BANK3_PCCARD: the PC card bank
+ \param[in] interrupt_source: specify get which interrupt flag
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
+ \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
+ \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source)
+{
+ uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U;
+
+ /* NAND bank1,bank2 or PC card bank3 */
+ status = EXMC_NPINTEN(bank);
+ interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET));
+
+ interrupt_enable = (status & interrupt_source);
+
+ if ((interrupt_enable) && (interrupt_state)){
+ /* interrupt flag is set */
+ return SET;
+ }else{
+ /* interrupt flag is reset */
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear EXMC interrupt flag
+ \param[in] bank: specifies the NAND bank, PC card bank
+ only one parameter can be selected which is shown as below:
+ \arg EXMC_BANK1_NAND: the NAND bank1
+ \arg EXMC_BANK2_NAND: the NAND bank2
+ \arg EXMC_BANK3_PCCARD: the PC card bank
+ \param[in] interrupt_source: specify get which interrupt flag
+ one or more parameters can be selected which is shown as below:
+ \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge
+ \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level
+ \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge
+ \param[out] none
+ \retval none
+*/
+void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source)
+{
+ /* NAND bank1, bank2 or PC card bank3 */
+ EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET);
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c
new file mode 100644
index 0000000..7084e96
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c
@@ -0,0 +1,249 @@
+/*!
+ \file gd32f10x_exti.c
+ \brief EXTI driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_exti.h"
+
+#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U)
+
+/*!
+ \brief deinitialize the EXTI
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void exti_deinit(void)
+{
+ /* reset the value of all the EXTI registers */
+ EXTI_INTEN = EXTI_REG_RESET_VALUE;
+ EXTI_EVEN = EXTI_REG_RESET_VALUE;
+ EXTI_RTEN = EXTI_REG_RESET_VALUE;
+ EXTI_FTEN = EXTI_REG_RESET_VALUE;
+ EXTI_SWIEV = EXTI_REG_RESET_VALUE;
+}
+
+/*!
+ \brief initialize the EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[in] mode: interrupt or event mode, refer to exti_mode_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_INTERRUPT: interrupt mode
+ \arg EXTI_EVENT: event mode
+ \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_TRIG_RISING: rising edge trigger
+ \arg EXTI_TRIG_FALLING: falling trigger
+ \arg EXTI_TRIG_BOTH: rising and falling trigger
+ \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger
+ \param[out] none
+ \retval none
+*/
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
+{
+ /* reset the EXTI line x */
+ EXTI_INTEN &= ~(uint32_t)linex;
+ EXTI_EVEN &= ~(uint32_t)linex;
+ EXTI_RTEN &= ~(uint32_t)linex;
+ EXTI_FTEN &= ~(uint32_t)linex;
+
+ /* set the EXTI mode and enable the interrupts or events from EXTI line x */
+ switch(mode) {
+ case EXTI_INTERRUPT:
+ EXTI_INTEN |= (uint32_t)linex;
+ break;
+ case EXTI_EVENT:
+ EXTI_EVEN |= (uint32_t)linex;
+ break;
+ default:
+ break;
+ }
+
+ /* set the EXTI trigger type */
+ switch(trig_type) {
+ case EXTI_TRIG_RISING:
+ EXTI_RTEN |= (uint32_t)linex;
+ EXTI_FTEN &= ~(uint32_t)linex;
+ break;
+ case EXTI_TRIG_FALLING:
+ EXTI_RTEN &= ~(uint32_t)linex;
+ EXTI_FTEN |= (uint32_t)linex;
+ break;
+ case EXTI_TRIG_BOTH:
+ EXTI_RTEN |= (uint32_t)linex;
+ EXTI_FTEN |= (uint32_t)linex;
+ break;
+ case EXTI_TRIG_NONE:
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief enable the interrupts from EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_interrupt_enable(exti_line_enum linex)
+{
+ EXTI_INTEN |= (uint32_t)linex;
+}
+
+/*!
+ \brief disable the interrupts from EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_interrupt_disable(exti_line_enum linex)
+{
+ EXTI_INTEN &= ~(uint32_t)linex;
+}
+
+/*!
+ \brief enable the events from EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_event_enable(exti_line_enum linex)
+{
+ EXTI_EVEN |= (uint32_t)linex;
+}
+
+/*!
+ \brief disable the events from EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_event_disable(exti_line_enum linex)
+{
+ EXTI_EVEN &= ~(uint32_t)linex;
+}
+
+/*!
+ \brief enable the software interrupt event from EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_software_interrupt_enable(exti_line_enum linex)
+{
+ EXTI_SWIEV |= (uint32_t)linex;
+}
+
+/*!
+ \brief disable the software interrupt event from EXTI line x
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_software_interrupt_disable(exti_line_enum linex)
+{
+ EXTI_SWIEV &= ~(uint32_t)linex;
+}
+
+/*!
+ \brief get EXTI line x interrupt pending flag
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval FlagStatus: status of flag (RESET or SET)
+*/
+FlagStatus exti_flag_get(exti_line_enum linex)
+{
+ if(RESET != (EXTI_PD & (uint32_t)linex)) {
+ return SET;
+ } else {
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear EXTI line x interrupt pending flag
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_flag_clear(exti_line_enum linex)
+{
+ EXTI_PD = (uint32_t)linex;
+}
+
+/*!
+ \brief get EXTI line x interrupt pending flag
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval FlagStatus: status of flag (RESET or SET)
+*/
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
+{
+ if(RESET != (EXTI_PD & (uint32_t)linex)) {
+ return SET;
+ } else {
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear EXTI line x interrupt pending flag
+ \param[in] linex: EXTI line number, refer to exti_line_enum
+ only one parameter can be selected which is shown as below:
+ \arg EXTI_x (x=0..19): EXTI line x
+ \param[out] none
+ \retval none
+*/
+void exti_interrupt_flag_clear(exti_line_enum linex)
+{
+ EXTI_PD = (uint32_t)linex;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c
new file mode 100644
index 0000000..77be676
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c
@@ -0,0 +1,967 @@
+/*!
+ \file gd32f10x_fmc.c
+ \brief FMC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_fmc.h"
+
+/*!
+ \brief set the wait state counter value
+ \param[in] wscnt��wait state counter value
+ \arg WS_WSCNT_0: FMC 0 wait state
+ \arg WS_WSCNT_1: FMC 1 wait state
+ \arg WS_WSCNT_2: FMC 2 wait state
+ \param[out] none
+ \retval none
+*/
+void fmc_wscnt_set(uint32_t wscnt)
+{
+ uint32_t reg;
+
+ reg = FMC_WS;
+ /* set the wait state counter value */
+ reg &= ~FMC_WS_WSCNT;
+ FMC_WS = (reg | wscnt);
+}
+
+/*!
+ \brief unlock the main FMC operation
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fmc_unlock(void)
+{
+ if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
+ /* write the FMC unlock key */
+ FMC_KEY0 = UNLOCK_KEY0;
+ FMC_KEY0 = UNLOCK_KEY1;
+ }
+
+ if(FMC_BANK0_SIZE < FMC_SIZE){
+ /* write the FMC unlock key */
+ if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){
+ FMC_KEY1 = UNLOCK_KEY0;
+ FMC_KEY1 = UNLOCK_KEY1;
+ }
+ }
+}
+
+/*!
+ \brief unlock the FMC bank0 operation
+ this function can be used for all GD32F10x devices.
+ for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0.
+ for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fmc_bank0_unlock(void)
+{
+ if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
+ /* write the FMC unlock key */
+ FMC_KEY0 = UNLOCK_KEY0;
+ FMC_KEY0 = UNLOCK_KEY1;
+ }
+}
+
+/*!
+ \brief unlock the FMC bank1 operation
+ this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB.
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fmc_bank1_unlock(void)
+{
+ if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){
+ /* write the FMC unlock key */
+ FMC_KEY1 = UNLOCK_KEY0;
+ FMC_KEY1 = UNLOCK_KEY1;
+ }
+}
+
+/*!
+ \brief lock the main FMC operation
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fmc_lock(void)
+{
+ /* set the LK bit */
+ FMC_CTL0 |= FMC_CTL0_LK;
+
+ if(FMC_BANK0_SIZE < FMC_SIZE){
+ /* set the LK bit */
+ FMC_CTL1 |= FMC_CTL1_LK;
+ }
+}
+
+/*!
+ \brief lock the FMC bank0 operation
+ this function can be used for all GD32F10X devices.
+ for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0.
+ for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function.
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fmc_bank0_lock(void)
+{
+ /* set the LK bit*/
+ FMC_CTL0 |= FMC_CTL0_LK;
+}
+
+/*!
+ \brief lock the FMC bank1 operation
+ this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB.
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fmc_bank1_lock(void)
+{
+ /* set the LK bit*/
+ FMC_CTL1 |= FMC_CTL1_LK;
+}
+
+/*!
+ \brief erase page
+ \param[in] page_address: the page address to be erased.
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_page_erase(uint32_t page_address)
+{
+ fmc_state_enum fmc_state;
+
+ if(FMC_BANK0_SIZE < FMC_SIZE){
+ if(FMC_BANK0_END_ADDRESS > page_address){
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* if the last operation is completed, start page erase */
+ if(FMC_READY == fmc_state){
+ FMC_CTL0 |= FMC_CTL0_PER;
+ FMC_ADDR0 = page_address;
+ FMC_CTL0 |= FMC_CTL0_START;
+ __nop();
+ __nop();
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PER bit */
+ FMC_CTL0 &= ~FMC_CTL0_PER;
+ }
+ }else{
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ /* if the last operation is completed, start page erase */
+ if(FMC_READY == fmc_state){
+ FMC_CTL1 |= FMC_CTL1_PER;
+ FMC_ADDR1 = page_address;
+ if(FMC_OBSTAT & FMC_OBSTAT_SPC){
+ FMC_ADDR0 = page_address;
+ }
+ FMC_CTL1 |= FMC_CTL1_START;
+ __nop();
+ __nop();
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PER bit */
+ FMC_CTL1 &= ~FMC_CTL1_PER;
+ }
+ }
+ }else{
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* if the last operation is completed, start page erase */
+ if(FMC_READY == fmc_state){
+ FMC_CTL0 |= FMC_CTL0_PER;
+ FMC_ADDR0 = page_address;
+ FMC_CTL0 |= FMC_CTL0_START;
+ __nop();
+ __nop();
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PER bit */
+ FMC_CTL0 &= ~FMC_CTL0_PER;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief erase whole chip
+ \param[in] none
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_mass_erase(void)
+{
+ fmc_state_enum fmc_state;
+ if(FMC_BANK0_SIZE < FMC_SIZE){
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ if(FMC_READY == fmc_state){
+ /* start whole chip erase */
+ FMC_CTL0 |= FMC_CTL0_MER;
+ FMC_CTL0 |= FMC_CTL0_START;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the MER bit */
+ FMC_CTL0 &= ~FMC_CTL0_MER;
+ }
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ if(FMC_READY == fmc_state){
+ /* start whole chip erase */
+ FMC_CTL1 |= FMC_CTL1_MER;
+ FMC_CTL1 |= FMC_CTL1_START;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the MER bit */
+ FMC_CTL1 &= ~FMC_CTL1_MER;
+ }
+ }else{
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* start whole chip erase */
+ FMC_CTL0 |= FMC_CTL0_MER;
+ FMC_CTL0 |= FMC_CTL0_START;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the MER bit */
+ FMC_CTL0 &= ~FMC_CTL0_MER;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief erase bank0
+ \param[in] none
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_bank0_erase(void)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* start FMC bank0 erase */
+ FMC_CTL0 |= FMC_CTL0_MER;
+ FMC_CTL0 |= FMC_CTL0_START;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the MER bit */
+ FMC_CTL0 &= ~FMC_CTL0_MER;
+ }
+ /* return the fmc state */
+ return fmc_state;
+}
+
+/*!
+ \brief erase bank1
+ \param[in] none
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_bank1_erase(void)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* start FMC bank1 erase */
+ FMC_CTL1 |= FMC_CTL1_MER;
+ FMC_CTL1 |= FMC_CTL1_START;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the MER bit */
+ FMC_CTL1 &= ~FMC_CTL1_MER;
+ }
+ /* return the fmc state */
+ return fmc_state;
+}
+
+/*!
+ \brief program a word at the corresponding address
+ \param[in] address: address to program
+ \param[in] data: word to program
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+ if(FMC_BANK0_SIZE < FMC_SIZE){
+ if(FMC_BANK0_END_ADDRESS > address){
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the PG bit to start program */
+ FMC_CTL0 |= FMC_CTL0_PG;
+ REG32(address) = data;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PG bit */
+ FMC_CTL0 &= ~FMC_CTL0_PG;
+ }
+ }else{
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the PG bit to start program */
+ FMC_CTL1 |= FMC_CTL1_PG;
+ REG32(address) = data;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PG bit */
+ FMC_CTL1 &= ~FMC_CTL1_PG;
+ }
+ }
+ }else{
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the PG bit to start program */
+ FMC_CTL0 |= FMC_CTL0_PG;
+ REG32(address) = data;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PG bit */
+ FMC_CTL0 &= ~FMC_CTL0_PG;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief program a half word at the corresponding address
+ \param[in] address: address to program
+ \param[in] data: halfword to program
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+ if(FMC_BANK0_SIZE < FMC_SIZE){
+ if(FMC_BANK0_END_ADDRESS > address){
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the PG bit to start program */
+ FMC_CTL0 |= FMC_CTL0_PG;
+ REG16(address) = data;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PG bit */
+ FMC_CTL0 &= ~FMC_CTL0_PG;
+ }
+ }else{
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the PG bit to start program */
+ FMC_CTL1 |= FMC_CTL1_PG;
+ REG16(address) = data;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PG bit */
+ FMC_CTL1 &= ~FMC_CTL1_PG;
+ }
+ }
+ }else{
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the PG bit to start program */
+ FMC_CTL0 |= FMC_CTL0_PG;
+ REG16(address) = data;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ /* reset the PG bit */
+ FMC_CTL0 &= ~FMC_CTL0_PG;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief unlock the option byte operation
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void ob_unlock(void)
+{
+ if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
+ /* write the FMC key */
+ FMC_OBKEY = UNLOCK_KEY0;
+ FMC_OBKEY = UNLOCK_KEY1;
+ }
+
+ /* wait until OBWEN bit is set by hardware */
+ while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
+ }
+}
+
+/*!
+ \brief lock the option byte operation
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void ob_lock(void)
+{
+ /* reset the OBWEN bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBWEN;
+}
+
+/*!
+ \brief erase the FMC option byte
+ unlock the FMC_CTL0 and option byte before calling this function
+ \param[in] none
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum ob_erase(void)
+{
+ uint16_t temp_spc = FMC_NSPC;
+
+ fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ /* check the option byte security protection value */
+ if(RESET != ob_spc_get()){
+ temp_spc = FMC_USPC;
+ }
+
+ if(FMC_READY == fmc_state){
+
+ /* start erase the option byte */
+ FMC_CTL0 |= FMC_CTL0_OBER;
+ FMC_CTL0 |= FMC_CTL0_START;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* reset the OBER bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBER;
+ /* set the OBPG bit */
+ FMC_CTL0 |= FMC_CTL0_OBPG;
+ /* no security protection */
+ OB_SPC = (uint16_t)temp_spc;
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBPG bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBPG;
+ }
+ }else{
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBPG bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBPG;
+ }
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief enable write protection
+ \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if
+ you want to protect the corresponding pages. meanwhile, sector
+ macro could used to set specific sector write protected.
+ one or more parameters can be selected which are shown as below:
+ \arg OB_WPx(x = 0..31): write protect specify sector
+ \arg OB_WP_ALL: write protect all sector
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
+{
+ uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
+
+ fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ ob_wp = (uint32_t)(~ob_wp);
+ temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0);
+ temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U);
+ temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
+ temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
+
+ if(FMC_READY == fmc_state){
+
+ /* set the OBPG bit*/
+ FMC_CTL0 |= FMC_CTL0_OBPG;
+
+ if(0xFFU != temp_wp0){
+ OB_WP0 = temp_wp0;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ }
+ if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
+ OB_WP1 = temp_wp1;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ }
+ if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
+ OB_WP2 = temp_wp2;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ }
+ if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
+ OB_WP3 = temp_wp3;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+ }
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBPG bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBPG;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief configure security protection
+ \param[in] ob_spc: specify security protection
+ only one parameter can be selected which is shown as below:
+ \arg FMC_NSPC: no security protection
+ \arg FMC_USPC: under security protection
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
+{
+ fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ FMC_CTL0 |= FMC_CTL0_OBER;
+ FMC_CTL0 |= FMC_CTL0_START;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* reset the OBER bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBER;
+
+ /* start the option byte program */
+ FMC_CTL0 |= FMC_CTL0_OBPG;
+
+ OB_SPC = (uint16_t)ob_spc;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBPG bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBPG;
+ }
+ }else{
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBER bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBER;
+ }
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief program the FMC user option byte
+ \param[in] ob_fwdgt: option byte watchdog value
+ \arg OB_FWDGT_SW: software free watchdog
+ \arg OB_FWDGT_HW: hardware free watchdog
+ \param[in] ob_deepsleep: option byte deepsleep reset value
+ \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
+ \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
+ \param[in] ob_stdby:option byte standby reset value
+ \arg OB_STDBY_NRST: no reset when entering standby mode
+ \arg OB_STDBY_RST: generate a reset instead of entering standby mode
+ \param[in] ob_boot: specifies the option byte boot bank value
+ \arg OB_BOOT_B0: boot from bank0
+ \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+ uint8_t temp;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the OBPG bit*/
+ FMC_CTL0 |= FMC_CTL0_OBPG;
+
+ temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
+ OB_USER = (uint16_t)temp;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBPG bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBPG;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief program option bytes data
+ \param[in] address: the option bytes address to be programmed
+ \param[in] data: the byte to be programmed
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
+{
+ fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_READY == fmc_state){
+ /* set the OBPG bit */
+ FMC_CTL0 |= FMC_CTL0_OBPG;
+ REG16(address) = data;
+
+ /* wait for the FMC ready */
+ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
+
+ if(FMC_TOERR != fmc_state){
+ /* reset the OBPG bit */
+ FMC_CTL0 &= ~FMC_CTL0_OBPG;
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief get the FMC user option byte
+ \param[in] none
+ \param[out] none
+ \retval the FMC user option byte values
+*/
+uint8_t ob_user_get(void)
+{
+ /* return the FMC user option byte value */
+ return (uint8_t)(FMC_OBSTAT >> 2U);
+}
+
+/*!
+ \brief get OB_DATA in register FMC_OBSTAT
+ \param[in] none
+ \param[out] none
+ \retval ob_data
+*/
+uint16_t ob_data_get(void)
+{
+ return (uint16_t)(FMC_OBSTAT >> 10U);
+}
+
+/*!
+ \brief get the FMC option byte write protection
+ \param[in] none
+ \param[out] none
+ \retval the FMC write protection option byte value
+*/
+uint32_t ob_write_protection_get(void)
+{
+ /* return the FMC write protection option byte value */
+ return FMC_WP;
+}
+
+/*!
+ \brief get the FMC option byte security protection
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus ob_spc_get(void)
+{
+ FlagStatus spc_state = RESET;
+
+ if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
+ spc_state = SET;
+ }else{
+ spc_state = RESET;
+ }
+ return spc_state;
+}
+
+/*!
+ \brief enable FMC interrupt
+ \param[in] interrupt: the FMC interrupt source
+ only one parameter can be selected which is shown as below:
+ \arg FMC_INT_BANK0_END: enable FMC end of program interrupt
+ \arg FMC_INT_BANK0_ERR: enable FMC error interrupt
+ \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
+ \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
+ \param[out] none
+ \retval none
+*/
+void fmc_interrupt_enable(uint32_t interrupt)
+{
+ FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
+}
+
+/*!
+ \brief disable FMC interrupt
+ \param[in] interrupt: the FMC interrupt source
+ only one parameter can be selected which is shown as below:
+ \arg FMC_INT_BANK0_END: enable FMC end of program interrupt
+ \arg FMC_INT_BANK0_ERR: enable FMC error interrupt
+ \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
+ \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
+ \param[out] none
+ \retval none
+*/
+void fmc_interrupt_disable(uint32_t interrupt)
+{
+ FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
+}
+
+/*!
+ \brief check flag is set or not
+ \param[in] flag: check FMC flag
+ only one parameter can be selected which is shown as below:
+ \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit
+ \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
+ \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
+ \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
+ \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit
+ \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit
+ \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
+ \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
+ \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus fmc_flag_get(uint32_t flag)
+{
+ if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear the FMC flag
+ \param[in] flag: clear FMC flag
+ only one parameter can be selected which is shown as below:
+ \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
+ \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
+ \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
+ \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
+ \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
+ \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
+ \param[out] none
+ \retval none
+*/
+void fmc_flag_clear(uint32_t flag)
+{
+ FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag));
+}
+
+/*!
+ \brief get FMC interrupt flag state
+ \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
+ \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
+{
+ uint32_t ret1 = RESET;
+ uint32_t ret2 = RESET;
+
+ if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
+ /* get the staus of interrupt flag */
+ ret1 = (uint32_t)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
+ /* get the staus of interrupt enale bit */
+ ret2 = (uint32_t)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
+ }else{
+ /* get the staus of interrupt flag */
+ ret1 = (uint32_t)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
+ /* get the staus of interrupt enale bit */
+ ret2 = (uint32_t)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag)));
+ }
+
+ if(ret1 && ret2){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear FMC interrupt flag state
+ \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
+ \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
+ \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
+ \param[out] none
+ \retval none
+*/
+void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
+{
+ FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
+}
+
+/*!
+ \brief get the FMC bank0 state
+ \param[in] none
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_bank0_state_get(void)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+
+ if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
+ fmc_state = FMC_BUSY;
+ }else{
+ if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
+ fmc_state = FMC_WPERR;
+ }else{
+ if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
+ fmc_state = FMC_PGERR;
+ }
+ }
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief get the FMC bank1 state
+ \param[in] none
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_bank1_state_get(void)
+{
+ fmc_state_enum fmc_state = FMC_READY;
+
+ if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){
+ fmc_state = FMC_BUSY;
+ }else{
+ if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){
+ fmc_state = FMC_WPERR;
+ }else{
+ if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){
+ fmc_state = FMC_PGERR;
+ }
+ }
+ }
+
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief check whether FMC bank0 is ready or not
+ \param[in] timeout: count of loop
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
+{
+ fmc_state_enum fmc_state = FMC_BUSY;
+
+ /* wait for FMC ready */
+ do{
+ /* get FMC state */
+ fmc_state = fmc_bank0_state_get();
+ timeout--;
+ }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
+
+ if(FMC_BUSY == fmc_state){
+ fmc_state = FMC_TOERR;
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
+
+/*!
+ \brief check whether FMC bank1 is ready or not
+ \param[in] timeout: count of loop
+ \param[out] none
+ \retval state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
+{
+ fmc_state_enum fmc_state = FMC_BUSY;
+
+ /* wait for FMC ready */
+ do{
+ /* get FMC state */
+ fmc_state = fmc_bank1_state_get();
+ timeout--;
+ }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
+
+ if(FMC_BUSY == fmc_state){
+ fmc_state = FMC_TOERR;
+ }
+ /* return the FMC state */
+ return fmc_state;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c
new file mode 100644
index 0000000..1de2d06
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c
@@ -0,0 +1,211 @@
+/*!
+ \file gd32f10x_fwdgt.c
+ \brief FWDGT driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_fwdgt.h"
+
+/*!
+ \brief enable write access to FWDGT_PSC and FWDGT_RLD
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_write_enable(void)
+{
+ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+}
+
+/*!
+ \brief disable write access to FWDGT_PSC and FWDGT_RLD
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_write_disable(void)
+{
+ FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
+}
+
+/*!
+ \brief start the free watchdog timer counter
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_enable(void)
+{
+ FWDGT_CTL = FWDGT_KEY_ENABLE;
+}
+
+/*!
+ \brief configure the free watchdog timer counter prescaler value
+ \param[in] prescaler_value: specify prescaler value
+ only one parameter can be selected which is shown as below:
+ \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+ \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+ \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+ \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+ \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+ \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+ \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
+{
+ uint32_t timeout = FWDGT_PSC_TIMEOUT;
+ uint32_t flag_status = RESET;
+
+ /* enable write access to FWDGT_PSC */
+ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+
+ /* wait until the PUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+ }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+
+ if ((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+
+ /* configure FWDGT */
+ FWDGT_PSC = (uint32_t)prescaler_value;
+
+ return SUCCESS;
+}
+
+/*!
+ \brief configure the free watchdog timer counter reload value
+ \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
+{
+ uint32_t timeout = FWDGT_RLD_TIMEOUT;
+ uint32_t flag_status = RESET;
+
+ /* enable write access to FWDGT_RLD */
+ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+
+ /* wait until the RUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+ }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+
+ if ((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+
+ FWDGT_RLD = RLD_RLD(reload_value);
+
+ return SUCCESS;
+}
+
+/*!
+ \brief reload the counter of FWDGT
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_counter_reload(void)
+{
+ FWDGT_CTL = FWDGT_KEY_RELOAD;
+}
+
+/*!
+ \brief configure counter reload value, and prescaler divider value
+ \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
+ \param[in] prescaler_div: FWDGT prescaler value
+ only one parameter can be selected which is shown as below:
+ \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+ \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+ \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+ \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+ \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+ \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+ \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
+{
+ uint32_t timeout = FWDGT_PSC_TIMEOUT;
+ uint32_t flag_status = RESET;
+
+ /* enable write access to FWDGT_PSC,and FWDGT_RLD */
+ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+ /* wait until the PUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+ }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+
+ if((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+ /* configure FWDGT */
+ FWDGT_PSC = (uint32_t)prescaler_div;
+
+ timeout = FWDGT_RLD_TIMEOUT;
+ /* wait until the RUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+ }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+
+ if((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+ FWDGT_RLD = RLD_RLD(reload_value);
+ /* reload the counter */
+ FWDGT_CTL = FWDGT_KEY_RELOAD;
+
+ return SUCCESS;
+}
+
+/*!
+ \brief get flag state of FWDGT
+ \param[in] flag: flag to get
+ only one parameter can be selected which is shown as below:
+ \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
+ \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus fwdgt_flag_get(uint16_t flag)
+{
+ if(FWDGT_STAT & flag){
+ return SET;
+ }
+
+ return RESET;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c
new file mode 100644
index 0000000..db7e801
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c
@@ -0,0 +1,533 @@
+/*!
+ \file gd32f10x_gpio.c
+ \brief GPIO driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_gpio.h"
+
+#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/
+#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */
+#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */
+#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */
+#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */
+#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */
+#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */
+#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */
+#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/
+
+/*!
+ \brief reset GPIO port
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[out] none
+ \retval none
+*/
+void gpio_deinit(uint32_t gpio_periph)
+{
+ switch(gpio_periph){
+ case GPIOA:
+ /* reset GPIOA */
+ rcu_periph_reset_enable(RCU_GPIOARST);
+ rcu_periph_reset_disable(RCU_GPIOARST);
+ break;
+ case GPIOB:
+ /* reset GPIOB */
+ rcu_periph_reset_enable(RCU_GPIOBRST);
+ rcu_periph_reset_disable(RCU_GPIOBRST);
+ break;
+ case GPIOC:
+ /* reset GPIOC */
+ rcu_periph_reset_enable(RCU_GPIOCRST);
+ rcu_periph_reset_disable(RCU_GPIOCRST);
+ break;
+ case GPIOD:
+ /* reset GPIOD */
+ rcu_periph_reset_enable(RCU_GPIODRST);
+ rcu_periph_reset_disable(RCU_GPIODRST);
+ break;
+ case GPIOE:
+ /* reset GPIOE */
+ rcu_periph_reset_enable(RCU_GPIOERST);
+ rcu_periph_reset_disable(RCU_GPIOERST);
+ break;
+ case GPIOF:
+ /* reset GPIOF */
+ rcu_periph_reset_enable(RCU_GPIOFRST);
+ rcu_periph_reset_disable(RCU_GPIOFRST);
+ break;
+ case GPIOG:
+ /* reset GPIOG */
+ rcu_periph_reset_enable(RCU_GPIOGRST);
+ rcu_periph_reset_disable(RCU_GPIOGRST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief reset alternate function I/O(AFIO)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void gpio_afio_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_AFRST);
+ rcu_periph_reset_disable(RCU_AFRST);
+}
+
+/*!
+ \brief GPIO parameter initialization
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] mode: gpio pin mode
+ only one parameter can be selected which is shown as below:
+ \arg GPIO_MODE_AIN: analog input mode
+ \arg GPIO_MODE_IN_FLOATING: floating input mode
+ \arg GPIO_MODE_IPD: pull-down input mode
+ \arg GPIO_MODE_IPU: pull-up input mode
+ \arg GPIO_MODE_OUT_OD: GPIO output with open-drain
+ \arg GPIO_MODE_OUT_PP: GPIO output with push-pull
+ \arg GPIO_MODE_AF_OD: AFIO output with open-drain
+ \arg GPIO_MODE_AF_PP: AFIO output with push-pull
+ \param[in] speed: gpio output max speed value
+ only one parameter can be selected which is shown as below:
+ \arg GPIO_OSPEED_10MHZ: output max speed 10MHz
+ \arg GPIO_OSPEED_2MHZ: output max speed 2MHz
+ \arg GPIO_OSPEED_50MHZ: output max speed 50MHz
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+
+ \param[out] none
+ \retval none
+*/
+void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin)
+{
+ uint16_t i;
+ uint32_t temp_mode = 0U;
+ uint32_t reg = 0U;
+
+ /* GPIO mode configuration */
+ temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU));
+
+ /* GPIO speed configuration */
+ if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){
+ /* output mode max speed:10MHz,2MHz,50MHz */
+ temp_mode |= (uint32_t)speed;
+ }
+
+ /* configure the eight low port pins with GPIO_CTL0 */
+ for(i = 0U;i < 8U;i++){
+ if((1U << i) & pin){
+ reg = GPIO_CTL0(gpio_periph);
+
+ /* clear the specified pin mode bits */
+ reg &= ~GPIO_MODE_MASK(i);
+ /* set the specified pin mode bits */
+ reg |= GPIO_MODE_SET(i, temp_mode);
+
+ /* set IPD or IPU */
+ if(GPIO_MODE_IPD == mode){
+ /* reset the corresponding OCTL bit */
+ GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
+ }else{
+ /* set the corresponding OCTL bit */
+ if(GPIO_MODE_IPU == mode){
+ GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
+ }
+ }
+ /* set GPIO_CTL0 register */
+ GPIO_CTL0(gpio_periph) = reg;
+ }
+ }
+ /* configure the eight high port pins with GPIO_CTL1 */
+ for(i = 8U;i < 16U;i++){
+ if((1U << i) & pin){
+ reg = GPIO_CTL1(gpio_periph);
+
+ /* clear the specified pin mode bits */
+ reg &= ~GPIO_MODE_MASK(i - 8U);
+ /* set the specified pin mode bits */
+ reg |= GPIO_MODE_SET(i - 8U, temp_mode);
+
+ /* set IPD or IPU */
+ if(GPIO_MODE_IPD == mode){
+ /* reset the corresponding OCTL bit */
+ GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
+ }else{
+ /* set the corresponding OCTL bit */
+ if(GPIO_MODE_IPU == mode){
+ GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
+ }
+ }
+ /* set GPIO_CTL1 register */
+ GPIO_CTL1(gpio_periph) = reg;
+ }
+ }
+}
+
+/*!
+ \brief set GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
+{
+ GPIO_BOP(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+ \brief reset GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
+{
+ GPIO_BC(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+ \brief write data to the specified GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[in] bit_value: SET or RESET
+ \arg RESET: clear the port pin
+ \arg SET: set the port pin
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
+{
+ if(RESET != bit_value){
+ GPIO_BOP(gpio_periph) = (uint32_t)pin;
+ }else{
+ GPIO_BC(gpio_periph) = (uint32_t)pin;
+ }
+}
+
+/*!
+ \brief write data to the specified GPIO port
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] data: specify the value to be written to the port output data register
+ \param[out] none
+ \retval none
+*/
+void gpio_port_write(uint32_t gpio_periph,uint16_t data)
+{
+ GPIO_OCTL(gpio_periph) = (uint32_t)data;
+}
+
+/*!
+ \brief get GPIO pin input status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval input status of gpio pin: SET or RESET
+*/
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin)
+{
+ if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief get GPIO port input status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[out] none
+ \retval input status of gpio all pins
+*/
+uint16_t gpio_input_port_get(uint32_t gpio_periph)
+{
+ return (uint16_t)(GPIO_ISTAT(gpio_periph));
+}
+
+/*!
+ \brief get GPIO pin output status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval output status of gpio pin: SET or RESET
+*/
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
+{
+ if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief get GPIO port output status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[out] none
+ \retval output status of gpio all pins
+*/
+uint16_t gpio_output_port_get(uint32_t gpio_periph)
+{
+ return ((uint16_t)GPIO_OCTL(gpio_periph));
+}
+
+/*!
+ \brief configure GPIO pin remap
+ \param[in] gpio_remap: select the pin to remap
+ \arg GPIO_SPI0_REMAP: SPI0 remapping
+ \arg GPIO_I2C0_REMAP: I2C0 remapping
+ \arg GPIO_USART0_REMAP: USART0 remapping
+ \arg GPIO_USART1_REMAP: USART1 remapping
+ \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping
+ \arg GPIO_USART2_FULL_REMAP: USART2 full remapping
+ \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping
+ \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping
+ \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping
+ \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping
+ \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping
+ \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping
+ \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping
+ \arg GPIO_TIMER3_REMAP: TIMER3 remapping
+ \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
+ \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
+ \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices)
+ \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices)
+ \arg GPIO_PD01_REMAP: PD01 remapping
+ \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices)
+ \arg GPIO_ADC0_ETRGRT_REMAP: ADC0 external trigger routine conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
+ \arg GPIO_ADC1_ETRGRT_REMAP: ADC1 external trigger routine conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices)
+ \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices)
+ \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices)
+ \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST
+ \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled
+ \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled
+ \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL, GD32F10X_HD and GD32F10X_XD devices)
+ \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices)
+ \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices)
+ \arg GPIO_TIMER8_REMAP: TIMER8 remapping
+ \arg GPIO_TIMER9_REMAP: TIMER9 remapping
+ \arg GPIO_TIMER10_REMAP: TIMER10 remapping
+ \arg GPIO_TIMER12_REMAP: TIMER12 remapping
+ \arg GPIO_TIMER13_REMAP: TIMER13 remapping
+ \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue)
+{
+ uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
+
+ if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){
+ /* get AFIO_PCF1 regiter value */
+ temp_reg = AFIO_PCF1;
+ }else{
+ /* get AFIO_PCF0 regiter value */
+ temp_reg = AFIO_PCF0;
+ }
+
+ temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U;
+ remap1 = remap & LSB_16BIT_MASK;
+
+ /* judge pin remap type */
+ if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){
+ temp_reg &= PCF_SWJCFG_MASK;
+ AFIO_PCF0 &= PCF_SWJCFG_MASK;
+ }else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)){
+ remap2 = ((uint32_t)0x03U) << temp_mask;
+ temp_reg &= ~remap2;
+ temp_reg |= ~PCF_SWJCFG_MASK;
+ }else{
+ temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U));
+ temp_reg |= ~PCF_SWJCFG_MASK;
+ }
+
+ /* set pin remap value */
+ if(DISABLE != newvalue){
+ temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U));
+ }
+
+ if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){
+ /* set AFIO_PCF1 regiter value */
+ AFIO_PCF1 = temp_reg;
+ }else{
+ /* set AFIO_PCF0 regiter value */
+ AFIO_PCF0 = temp_reg;
+ }
+}
+
+/*!
+ \brief select GPIO pin exti sources
+ \param[in] gpio_outputport: gpio event output port
+ \arg GPIO_PORT_SOURCE_GPIOA: output port source A
+ \arg GPIO_PORT_SOURCE_GPIOB: output port source B
+ \arg GPIO_PORT_SOURCE_GPIOC: output port source C
+ \arg GPIO_PORT_SOURCE_GPIOD: output port source D
+ \arg GPIO_PORT_SOURCE_GPIOE: output port source E
+ \arg GPIO_PORT_SOURCE_GPIOF: output port source F
+ \arg GPIO_PORT_SOURCE_GPIOG: output port source G
+ \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15)
+ \param[out] none
+ \retval none
+*/
+void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin)
+{
+ uint32_t source = 0U;
+ source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK));
+
+ /* select EXTI sources */
+ if(GPIO_PIN_SOURCE_4 > output_pin){
+ /* select EXTI0/EXTI1/EXTI2/EXTI3 */
+ AFIO_EXTISS0 &= ~source;
+ AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+ }else if(GPIO_PIN_SOURCE_8 > output_pin){
+ /* select EXTI4/EXTI5/EXTI6/EXTI7 */
+ AFIO_EXTISS1 &= ~source;
+ AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+ }else if(GPIO_PIN_SOURCE_12 > output_pin){
+ /* select EXTI8/EXTI9/EXTI10/EXTI11 */
+ AFIO_EXTISS2 &= ~source;
+ AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+ }else{
+ /* select EXTI12/EXTI13/EXTI14/EXTI15 */
+ AFIO_EXTISS3 &= ~source;
+ AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+ }
+}
+
+/*!
+ \brief configure GPIO pin event output
+ \param[in] output_port: gpio event output port
+ only one parameter can be selected which are shown as below:
+ \arg GPIO_EVENT_PORT_GPIOA: event output port A
+ \arg GPIO_EVENT_PORT_GPIOB: event output port B
+ \arg GPIO_EVENT_PORT_GPIOC: event output port C
+ \arg GPIO_EVENT_PORT_GPIOD: event output port D
+ \arg GPIO_EVENT_PORT_GPIOE: event output port E
+ \arg GPIO_EVENT_PORT_GPIOE: event output port F
+ \arg GPIO_EVENT_PORT_GPIOE: event output port G
+ \param[in] output_pin:
+ only one parameter can be selected which are shown as below:
+ \arg GPIO_EVENT_PIN_x(x=0..15)
+ \param[out] none
+ \retval none
+*/
+void gpio_event_output_config(uint8_t output_port, uint8_t output_pin)
+{
+ uint32_t reg = 0U;
+ reg = AFIO_EC;
+
+ /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
+ reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN));
+
+ reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET);
+ reg |= (uint32_t)output_pin;
+
+ AFIO_EC = reg;
+}
+
+/*!
+ \brief enable GPIO pin event output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void gpio_event_output_enable(void)
+{
+ AFIO_EC |= AFIO_EC_EOE;
+}
+
+/*!
+ \brief disable GPIO pin event output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void gpio_event_output_disable(void)
+{
+ AFIO_EC &= (uint32_t)(~AFIO_EC_EOE);
+}
+
+/*!
+ \brief lock GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
+ \param[in] pin: GPIO pin
+ one or more parameters can be selected which are shown as below:
+ \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
+{
+ uint32_t lock = 0x00010000U;
+ lock |= pin;
+
+ /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
+ GPIO_LOCK(gpio_periph) = (uint32_t)lock;
+ GPIO_LOCK(gpio_periph) = (uint32_t)pin;
+ GPIO_LOCK(gpio_periph) = (uint32_t)lock;
+ lock = GPIO_LOCK(gpio_periph);
+ lock = GPIO_LOCK(gpio_periph);
+}
+
+#ifdef GD32F10X_CL
+/*!
+ \brief select ethernet MII or RMII PHY
+ \param[in] gpio_enetsel: ethernet MII or RMII PHY selection
+ \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY
+ \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY
+ \param[out] none
+ \retval none
+*/
+void gpio_ethernet_phy_select(uint32_t gpio_enetsel)
+{
+ /* clear AFIO_PCF0_ENET_PHY_SEL bit */
+ AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL);
+
+ /* select MII or RMII PHY */
+ AFIO_PCF0 |= (uint32_t)gpio_enetsel;
+}
+#endif
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c
new file mode 100644
index 0000000..dc20fcc
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c
@@ -0,0 +1,711 @@
+/*!
+ \file gd32f10x_i2c.c
+ \brief I2C driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_i2c.h"
+
+/* I2C register bit mask */
+#define I2CCLK_MAX ((uint32_t)0x00000036U) /*!< i2cclk maximum value */
+#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
+#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */
+#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */
+
+/* I2C register bit offset */
+#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */
+
+/*!
+ \brief reset I2C
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void i2c_deinit(uint32_t i2c_periph)
+{
+ switch(i2c_periph){
+ case I2C0:
+ /* reset I2C0 */
+ rcu_periph_reset_enable(RCU_I2C0RST);
+ rcu_periph_reset_disable(RCU_I2C0RST);
+ break;
+ case I2C1:
+ /* reset I2C1 */
+ rcu_periph_reset_enable(RCU_I2C1RST);
+ rcu_periph_reset_disable(RCU_I2C1RST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure I2C clock
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
+ \param[in] dutycyc: duty cycle in fast mode
+ only one parameter can be selected which is shown as below:
+ \arg I2C_DTCY_2: T_low/T_high=2
+ \arg I2C_DTCY_16_9: T_low/T_high=16/9
+ \param[out] none
+ \retval none
+*/
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
+{
+ uint32_t pclk1, clkc, freq, risetime;
+ uint32_t temp;
+
+ pclk1 = rcu_clock_freq_get(CK_APB1);
+ /* I2C peripheral clock frequency */
+ freq = (uint32_t)(pclk1/1000000U);
+ if(freq >= I2CCLK_MAX){
+ freq = I2CCLK_MAX;
+ }
+ temp = I2C_CTL1(i2c_periph);
+ temp &= ~I2C_CTL1_I2CCLK;
+ temp |= freq;
+
+ I2C_CTL1(i2c_periph) = temp;
+
+ if(100000U >= clkspeed){
+ /* the maximum SCL rise time is 1000ns in standard mode */
+ risetime = (uint32_t)((pclk1/1000000U)+1U);
+ if(risetime >= I2CCLK_MAX){
+ I2C_RT(i2c_periph) = I2CCLK_MAX;
+ }else if(risetime <= I2CCLK_MIN){
+ I2C_RT(i2c_periph) = I2CCLK_MIN;
+ }else{
+ I2C_RT(i2c_periph) = risetime;
+ }
+ clkc = (uint32_t)(pclk1/(clkspeed*2U));
+ if(clkc < 0x04U){
+ /* the CLKC in standard mode minmum value is 4 */
+ clkc = 0x04U;
+ }
+ I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
+
+ }else if(400000U >= clkspeed){
+ /* the maximum SCL rise time is 300ns in fast mode */
+ I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
+ if(I2C_DTCY_2 == dutycyc){
+ /* I2C duty cycle is 2 */
+ clkc = (uint32_t)(pclk1/(clkspeed*3U));
+ I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
+ }else{
+ /* I2C duty cycle is 16/9 */
+ clkc = (uint32_t)(pclk1/(clkspeed*25U));
+ I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
+ }
+ if(0U == (clkc & I2C_CKCFG_CLKC)){
+ /* the CLKC in fast mode minmum value is 1 */
+ clkc |= 0x0001U;
+ }
+ I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
+ I2C_CKCFG(i2c_periph) |= clkc;
+ }else{
+ }
+}
+
+/*!
+ \brief configure I2C address
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] mode:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_I2CMODE_ENABLE: I2C mode
+ \arg I2C_SMBUSMODE_ENABLE: SMBus mode
+ \param[in] addformat: 7bits or 10bits
+ only one parameter can be selected which is shown as below:
+ \arg I2C_ADDFORMAT_7BITS: address format is 7bits
+ \arg I2C_ADDFORMAT_10BITS: address format is 10bits
+ \param[in] addr: I2C address
+ \param[out] none
+ \retval none
+*/
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
+{
+ /* SMBus/I2C mode selected */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SMBEN);
+ ctl |= mode;
+ I2C_CTL0(i2c_periph) = ctl;
+ /* configure address */
+ addr = addr & I2C_ADDRESS_MASK;
+ I2C_SADDR0(i2c_periph) = (addformat | addr);
+}
+
+/*!
+ \brief select SMBus type
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] type:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_SMBUS_DEVICE: device
+ \arg I2C_SMBUS_HOST: host
+ \param[out] none
+ \retval none
+*/
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
+{
+ if(I2C_SMBUS_HOST == type){
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
+ }else{
+ I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
+ }
+}
+
+/*!
+ \brief whether or not to send an ACK
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] ack:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_ACK_ENABLE: ACK will be sent
+ \arg I2C_ACK_DISABLE: ACK will not be sent
+ \param[out] none
+ \retval none
+*/
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
+{
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_ACKEN);
+ ctl |= ack;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief configure I2C POAP position
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] pos:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte
+ \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte
+ \param[out] none
+ \retval none
+*/
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
+{
+ uint32_t ctl = 0U;
+ /* configure I2C POAP position */
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_POAP);
+ ctl |= pos;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief master sends slave address
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] addr: slave address
+ \param[in] trandirection: transmitter or receiver
+ only one parameter can be selected which is shown as below:
+ \arg I2C_TRANSMITTER: transmitter
+ \arg I2C_RECEIVER: receiver
+ \param[out] none
+ \retval none
+*/
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
+{
+ /* master is a transmitter or a receiver */
+ if(I2C_TRANSMITTER == trandirection){
+ addr = addr & I2C_TRANSMITTER;
+ }else{
+ addr = addr | I2C_RECEIVER;
+ }
+ /* send slave address */
+ I2C_DATA(i2c_periph) = addr;
+}
+
+/*!
+ \brief enable dual-address mode
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] addr: the second address in dual-address mode
+ \param[out] none
+ \retval none
+*/
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr)
+{
+ /* configure address */
+ addr = addr & I2C_ADDRESS2_MASK;
+ I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr);
+}
+
+/*!
+ \brief disable dual-address mode
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void i2c_dualaddr_disable(uint32_t i2c_periph)
+{
+ I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
+}
+
+/*!
+ \brief enable I2C
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void i2c_enable(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
+}
+
+/*!
+ \brief disable I2C
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void i2c_disable(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
+}
+
+/*!
+ \brief generate a START condition on I2C bus
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void i2c_start_on_bus(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
+}
+
+/*!
+ \brief generate a STOP condition on I2C bus
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void i2c_stop_on_bus(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
+}
+
+/*!
+ \brief I2C transmit data function
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] data: data of transmission
+ \param[out] none
+ \retval none
+*/
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
+{
+ I2C_DATA(i2c_periph) = DATA_TRANS(data);
+}
+
+/*!
+ \brief I2C receive data function
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval data of received
+*/
+uint8_t i2c_data_receive(uint32_t i2c_periph)
+{
+ return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
+}
+
+/*!
+ \brief configure I2C DMA mode
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] dmastate:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_DMA_ON: enable DMA mode
+ \arg I2C_DMA_OFF: disable DMA mode
+ \param[out] none
+ \retval none
+*/
+void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate)
+{
+ /* configure I2C DMA function */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL1(i2c_periph);
+ ctl &= ~(I2C_CTL1_DMAON);
+ ctl |= dmastate;
+ I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+ \brief configure whether next DMA EOT is DMA last transfer or not
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] dmalast:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_DMALST_ON: next DMA EOT is the last transfer
+ \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer
+ \param[out] none
+ \retval none
+*/
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
+{
+ /* configure DMA last transfer */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL1(i2c_periph);
+ ctl &= ~(I2C_CTL1_DMALST);
+ ctl |= dmalast;
+ I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+ \brief whether to stretch SCL low when data is not ready in slave mode
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] stretchpara:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching
+ \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching
+ \param[out] none
+ \retval none
+*/
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
+{
+ /* configure I2C SCL strerching */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SS);
+ ctl |= stretchpara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief whether or not to response to a general call
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] gcallpara:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_GCEN_ENABLE: slave will response to a general call
+ \arg I2C_GCEN_DISABLE: slave will not response to a general call
+ \param[out] none
+ \retval none
+*/
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
+{
+ /* configure slave response to a general call enable or disable */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_GCEN);
+ ctl |= gcallpara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief configure software reset of I2C
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] sreset:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_SRESET_SET: I2C is under reset
+ \arg I2C_SRESET_RESET: I2C is not under reset
+ \param[out] none
+ \retval none
+*/
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
+{
+ /* modify CTL0 and configure software reset I2C state */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SRESET);
+ ctl |= sreset;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief configure I2C PEC calculation
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] pecstate:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_PEC_ENABLE: PEC calculation on
+ \arg I2C_PEC_DISABLE: PEC calculation off
+ \param[out] none
+ \retval none
+*/
+void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate)
+{
+ /* on/off PEC calculation */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_PECEN);
+ ctl |= pecstate;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief configure whether to transfer PEC value
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] pecpara:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_PECTRANS_ENABLE: transfer PEC
+ \arg I2C_PECTRANS_DISABLE: not transfer PEC
+ \param[out] none
+ \retval none
+*/
+void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara)
+{
+ /* whether to transfer PEC */
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_PECTRANS);
+ ctl |= pecpara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief get packet error checking value
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[out] none
+ \retval PEC value
+*/
+uint8_t i2c_pec_value_get(uint32_t i2c_periph)
+{
+ return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET);
+}
+
+/*!
+ \brief configure I2C alert through SMBA pin
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] smbuspara:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin
+ \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
+ \param[out] none
+ \retval none
+*/
+void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara)
+{
+ /* issue alert through SMBA pin configure*/
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SALT);
+ ctl |= smbuspara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief configure I2C ARP protocol in SMBus
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] arpstate:
+ only one parameter can be selected which is shown as below:
+ \arg I2C_ARP_ENABLE: enable ARP
+ \arg I2C_ARP_DISABLE: disable ARP
+ \param[out] none
+ \retval none
+*/
+void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate)
+{
+ /* enable or disable I2C ARP protocol*/
+ uint32_t ctl = 0U;
+
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_ARPEN);
+ ctl |= arpstate;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief get I2C flag status
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] flag: I2C flags, refer to i2c_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg I2C_FLAG_SBSEND: start condition sent out in master mode
+ \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
+ \arg I2C_FLAG_BTC: byte transmission finishes
+ \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
+ \arg I2C_FLAG_STPDET: stop condition detected in slave mode
+ \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving
+ \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting
+ \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
+ \arg I2C_FLAG_LOSTARB: arbitration lost in master mode
+ \arg I2C_FLAG_AERR: acknowledge error
+ \arg I2C_FLAG_OUERR: over-run or underrun situation occurs in slave mode
+ \arg I2C_FLAG_PECERR: PEC error when receiving data
+ \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
+ \arg I2C_FLAG_SMBALT: SMBus alert status
+ \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
+ \arg I2C_FLAG_I2CBSY: busy flag
+ \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
+ \arg I2C_FLAG_RXGC: general call address (00h) received
+ \arg I2C_FLAG_DEFSMB: default address of SMBus device
+ \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
+ \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
+{
+ if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear I2C flag status
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] flag: I2C flags, refer to i2c_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg I2C_FLAG_SMBALT: SMBus alert status
+ \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
+ \arg I2C_FLAG_PECERR: PEC error when receiving data
+ \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
+ \arg I2C_FLAG_AERR: acknowledge error
+ \arg I2C_FLAG_LOSTARB: arbitration lost in master mode
+ \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
+ \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
+ \param[out] none
+ \retval none
+*/
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
+{
+ if(I2C_FLAG_ADDSEND == flag){
+ /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+ I2C_STAT0(i2c_periph);
+ I2C_STAT1(i2c_periph);
+ }else{
+ I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag));
+ }
+}
+
+/*!
+ \brief enable I2C interrupt
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum
+ only one parameter can be selected which is shown as below:
+ \arg I2C_INT_ERR: error interrupt
+ \arg I2C_INT_EV: event interrupt
+ \arg I2C_INT_BUF: buffer interrupt
+ \param[out] none
+ \retval none
+*/
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
+{
+ I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt));
+}
+
+/*!
+ \brief disable I2C interrupt
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg I2C_INT_ERR: error interrupt enable
+ \arg I2C_INT_EV: event interrupt enable
+ \arg I2C_INT_BUF: buffer interrupt enable
+ \param[out] none
+ \retval none
+*/
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
+{
+ I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt));
+}
+
+/*!
+ \brief get I2C interrupt flag status
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
+ \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+ \arg I2C_INT_FLAG_BTC: byte transmission finishes
+ \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
+ \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
+ \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
+ \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
+ \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+ \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+ \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+ \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+ \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+ \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+ \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
+{
+ uint32_t intenable = 0U, flagstatus = 0U, bufie;
+
+ /* check BUFIE */
+ bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
+
+ /* get the interrupt enable bit status */
+ intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
+ /* get the corresponding flag bit status */
+ flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));
+
+ if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){
+ if(intenable && bufie){
+ intenable = 1U;
+ }else{
+ intenable = 0U;
+ }
+ }
+ if((0U != flagstatus) && (0U != intenable)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear I2C interrupt flag status
+ \param[in] i2c_periph: I2Cx(x=0,1)
+ \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+ \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+ \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+ \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+ \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+ \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+ \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+ \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag
+ \param[out] none
+ \retval none
+*/
+void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
+{
+ if(I2C_INT_FLAG_ADDSEND == int_flag){
+ /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+ I2C_STAT0(i2c_periph);
+ I2C_STAT1(i2c_periph);
+ }else{
+ I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag));
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c
new file mode 100644
index 0000000..5f0d7f4
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c
@@ -0,0 +1,184 @@
+/*!
+ \file gd32f10x_misc.c
+ \brief MISC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_misc.h"
+
+/*!
+ \brief set the priority group
+ \param[in] nvic_prigroup: the NVIC priority group
+ \arg NVIC_PRIGROUP_PRE0_SUB4: 0 bits for pre-emption priority, 4 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE1_SUB3: 1 bits for pre-emption priority, 3 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE2_SUB2: 2 bits for pre-emption priority, 2 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE3_SUB1: 3 bits for pre-emption priority, 1 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE4_SUB0: 4 bits for pre-emption priority, 0 bits for subpriority
+ \param[out] none
+ \retval none
+*/
+void nvic_priority_group_set(uint32_t nvic_prigroup)
+{
+ /* set the priority group value */
+ SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
+}
+
+/*!
+ \brief enable NVIC interrupt request
+ \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+ \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
+ \param[in] nvic_irq_sub_priority: the subpriority needed to set
+ \param[out] none
+ \retval none
+*/
+void nvic_irq_enable(uint8_t nvic_irq,
+ uint8_t nvic_irq_pre_priority,
+ uint8_t nvic_irq_sub_priority)
+{
+ uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
+
+ /* use the priority group value to get the temp_pre and the temp_sub */
+ switch((SCB->AIRCR) & (uint32_t)0x700U) {
+ case NVIC_PRIGROUP_PRE0_SUB4:
+ temp_pre = 0U;
+ temp_sub = 0x4U;
+ break;
+ case NVIC_PRIGROUP_PRE1_SUB3:
+ temp_pre = 1U;
+ temp_sub = 0x3U;
+ break;
+ case NVIC_PRIGROUP_PRE2_SUB2:
+ temp_pre = 2U;
+ temp_sub = 0x2U;
+ break;
+ case NVIC_PRIGROUP_PRE3_SUB1:
+ temp_pre = 3U;
+ temp_sub = 0x1U;
+ break;
+ case NVIC_PRIGROUP_PRE4_SUB0:
+ temp_pre = 4U;
+ temp_sub = 0x0U;
+ break;
+ default:
+ nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+ temp_pre = 2U;
+ temp_sub = 0x2U;
+ break;
+ }
+
+ /* get the temp_priority to fill the NVIC->IP register */
+ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
+ temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
+ temp_priority = temp_priority << 0x04U;
+ NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+
+ /* enable the selected IRQ */
+ NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
+}
+
+/*!
+ \brief disable NVIC interrupt request
+ \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+ \param[out] none
+ \retval none
+*/
+void nvic_irq_disable(uint8_t nvic_irq)
+{
+ /* disable the selected IRQ.*/
+ NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
+}
+
+/*!
+ \brief set the NVIC vector table base address
+ \param[in] nvic_vict_tab: the RAM or FLASH base address
+ \arg NVIC_VECTTAB_RAM: RAM base address
+ \are NVIC_VECTTAB_FLASH: Flash base address
+ \param[in] offset: vector table offset
+ \param[out] none
+ \retval none
+*/
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
+{
+ SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
+ __DSB();
+}
+
+/*!
+ \brief set the state of the low power mode
+ \param[in] lowpower_mode: the low power mode state
+ \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
+ mode by exiting from ISR
+ \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
+ \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the low power mode can be woke up
+ by all the enable and disable interrupts
+ \param[out] none
+ \retval none
+*/
+void system_lowpower_set(uint8_t lowpower_mode)
+{
+ SCB->SCR |= (uint32_t)lowpower_mode;
+}
+
+/*!
+ \brief reset the state of the low power mode
+ \param[in] lowpower_mode: the low power mode state
+ \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
+ mode by exiting from ISR
+ \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
+ \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the low power mode only can be
+ woke up by the enable interrupts
+ \param[out] none
+ \retval none
+*/
+void system_lowpower_reset(uint8_t lowpower_mode)
+{
+ SCB->SCR &= (~(uint32_t)lowpower_mode);
+}
+
+/*!
+ \brief set the systick clock source
+ \param[in] systick_clksource: the systick clock source needed to choose
+ \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
+ \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
+ \param[out] none
+ \retval none
+*/
+
+void systick_clksource_set(uint32_t systick_clksource)
+{
+ if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) {
+ /* set the systick clock source from HCLK */
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ } else {
+ /* set the systick clock source from HCLK/8 */
+ SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c
new file mode 100644
index 0000000..0039ff3
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c
@@ -0,0 +1,276 @@
+/*!
+ \file gd32f10x_pmu.c
+ \brief PMU driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_pmu.h"
+
+/*!
+ \brief reset PMU register
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_deinit(void)
+{
+ /* reset PMU */
+ rcu_periph_reset_enable(RCU_PMURST);
+ rcu_periph_reset_disable(RCU_PMURST);
+}
+
+/*!
+ \brief select low voltage detector threshold
+ \param[in] lvdt_n:
+ only one parameter can be selected which is shown as below:
+ \arg PMU_LVDT_0: voltage threshold is 2.2V
+ \arg PMU_LVDT_1: voltage threshold is 2.3V
+ \arg PMU_LVDT_2: voltage threshold is 2.4V
+ \arg PMU_LVDT_3: voltage threshold is 2.5V
+ \arg PMU_LVDT_4: voltage threshold is 2.6V
+ \arg PMU_LVDT_5: voltage threshold is 2.7V
+ \arg PMU_LVDT_6: voltage threshold is 2.8V
+ \arg PMU_LVDT_7: voltage threshold is 2.9V
+ \param[out] none
+ \retval none
+*/
+void pmu_lvd_select(uint32_t lvdt_n)
+{
+ /* disable LVD */
+ PMU_CTL &= ~PMU_CTL_LVDEN;
+ /* clear LVDT bits */
+ PMU_CTL &= ~PMU_CTL_LVDT;
+ /* set LVDT bits according to lvdt_n */
+ PMU_CTL |= lvdt_n;
+ /* enable LVD */
+ PMU_CTL |= PMU_CTL_LVDEN;
+}
+
+/*!
+ \brief disable PMU lvd
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_lvd_disable(void)
+{
+ /* disable LVD */
+ PMU_CTL &= ~PMU_CTL_LVDEN;
+}
+
+/*!
+ \brief PMU work in sleep mode
+ \param[in] sleepmodecmd:
+ only one parameter can be selected which is shown as below:
+ \arg WFI_CMD: use WFI command
+ \arg WFE_CMD: use WFE command
+ \param[out] none
+ \retval none
+*/
+void pmu_to_sleepmode(uint8_t sleepmodecmd)
+{
+ /* clear sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ /* select WFI or WFE command to enter sleep mode */
+ if(WFI_CMD == sleepmodecmd){
+ __WFI();
+ }else{
+ __WFE();
+ }
+}
+
+/*!
+ \brief PMU work in deepsleep mode
+ \param[in] ldo:
+ only one parameter can be selected which is shown as below:
+ \arg PMU_LDO_NORMAL: LDO work in normal power mode when pmu enter deepsleep mode
+ \arg PMU_LDO_LOWPOWER: LDO work in low power mode when pmu enter deepsleep mode
+ \param[in] deepsleepmodecmd:
+ only one parameter can be selected which is shown as below:
+ \arg WFI_CMD: use WFI command
+ \arg WFE_CMD: use WFE command
+ \param[out] none
+ \retval none
+*/
+void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
+{
+ static uint32_t reg_snap[ 4 ];
+ /* clear stbmod and ldolp bits */
+ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
+
+ /* set ldolp bit according to pmu_ldo */
+ PMU_CTL |= ldo;
+
+ /* set sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ reg_snap[0] = REG32(0xE000E010U);
+ reg_snap[1] = REG32(0xE000E100U);
+ reg_snap[2] = REG32(0xE000E104U);
+ reg_snap[3] = REG32(0xE000E108U);
+
+ REG32(0xE000E010U) &= 0x00010004U;
+ REG32(0xE000E180U) = 0XFF7FF83DU;
+ REG32(0xE000E184U) = 0XBFFFF8FFU;
+ REG32(0xE000E188U) = 0xFFFFFFFFU;
+
+ /* select WFI or WFE command to enter deepsleep mode */
+ if(WFI_CMD == deepsleepmodecmd){
+ __WFI();
+ }else{
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ REG32(0xE000E010U) = reg_snap[0] ;
+ REG32(0xE000E100U) = reg_snap[1] ;
+ REG32(0xE000E104U) = reg_snap[2] ;
+ REG32(0xE000E108U) = reg_snap[3] ;
+
+ /* reset sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/*!
+ \brief pmu work in standby mode
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_to_standbymode(void)
+{
+ /* set stbmod bit */
+ PMU_CTL |= PMU_CTL_STBMOD;
+
+ /* reset wakeup flag */
+ PMU_CTL |= PMU_CTL_WURST;
+
+ /* set sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ REG32(0xE000E010U) &= 0x00010004U;
+ REG32(0xE000E180U) = 0XFFFFFFF7U;
+ REG32(0xE000E184U) = 0XFFFFFDFFU;
+ REG32(0xE000E188U) = 0xFFFFFFFFU;
+
+ /* select WFI command to enter standby mode */
+ __WFI();
+}
+
+/*!
+ \brief enable wakeup pin
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_wakeup_pin_enable(void)
+{
+ PMU_CS |= PMU_CS_WUPEN;
+}
+
+/*!
+ \brief disable wakeup pin
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_wakeup_pin_disable(void)
+{
+ PMU_CS &= ~PMU_CS_WUPEN;
+}
+
+/*!
+ \brief enable write access to the registers in backup domain
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_backup_write_enable(void)
+{
+ PMU_CTL |= PMU_CTL_BKPWEN;
+}
+
+/*!
+ \brief disable write access to the registers in backup domain
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_backup_write_disable(void)
+{
+ PMU_CTL &= ~PMU_CTL_BKPWEN;
+}
+
+/*!
+ \brief get flag state
+ \param[in] flag:
+ only one parameter can be selected which is shown as below:
+ \arg PMU_FLAG_WAKEUP: wakeup flag
+ \arg PMU_FLAG_STANDBY: standby flag
+ \arg PMU_FLAG_LVD: lvd flag
+ \param[out] none
+ \retval FlagStatus SET or RESET
+*/
+FlagStatus pmu_flag_get(uint32_t flag)
+{
+ if(PMU_CS & flag){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear flag bit
+ \param[in] flag:
+ only one parameter can be selected which is shown as below:
+ \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
+ \arg PMU_FLAG_RESET_STANDBY: reset standby flag
+ \param[out] none
+ \retval none
+*/
+void pmu_flag_clear(uint32_t flag)
+{
+ switch(flag){
+ case PMU_FLAG_RESET_WAKEUP:
+ /* reset wakeup flag */
+ PMU_CTL |= PMU_CTL_WURST;
+ break;
+ case PMU_FLAG_RESET_STANDBY:
+ /* reset standby flag */
+ PMU_CTL |= PMU_CTL_STBRST;
+ break;
+ default :
+ break;
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c
new file mode 100644
index 0000000..62fcc80
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c
@@ -0,0 +1,1192 @@
+/*!
+ \file gd32f10x_rcu.c
+ \brief RCU driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_rcu.h"
+
+/* define clock source */
+#define SEL_IRC8M ((uint16_t)0U)
+#define SEL_HXTAL ((uint16_t)1U)
+#define SEL_PLL ((uint16_t)2U)
+
+/* define startup timeout count */
+#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
+#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)
+
+/*!
+ \brief deinitialize the RCU
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_deinit(void)
+{
+ /* enable IRC8M */
+ RCU_CTL |= RCU_CTL_IRC8MEN;
+ rcu_osci_stab_wait(RCU_IRC8M);
+
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+
+ /* reset CTL register */
+ RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
+ RCU_CTL &= ~RCU_CTL_HXTALBPS;
+#ifdef GD32F10X_CL
+ RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
+#endif /* GD32F10X_CL */
+
+ /* reset CFG0 register */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
+ RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF |
+ RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2);
+#elif defined(GD32F10X_CL)
+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
+ RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
+ RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+ /* reset INT and CFG1 register */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ RCU_INT = 0x009f0000U;
+#elif defined(GD32F10X_CL)
+ RCU_INT = 0x00ff0000U;
+ RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
+ RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+}
+
+/*!
+ \brief enable the peripherals clock
+ \param[in] periph: RCU peripherals, refer to rcu_periph_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
+ \arg RCU_AF : alternate function clock
+ \arg RCU_CRC: CRC clock
+ \arg RCU_DMAx (x=0,1): DMA clock
+ \arg RCU_ENET: ENET clock(CL series available)
+ \arg RCU_ENETTX: ENETTX clock(CL series available)
+ \arg RCU_ENETRX: ENETRX clock(CL series available)
+ \arg RCU_USBD: USBD clock(HD,XD series available)
+ \arg RCU_USBFS: USBFS clock(CL series available)
+ \arg RCU_EXMC: EXMC clock
+ \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock
+ \arg RCU_WWDGT: WWDGT clock
+ \arg RCU_SPIx (x=0,1,2): SPI clock
+ \arg RCU_USARTx (x=0,1,2): USART clock
+ \arg RCU_UARTx (x=3,4): UART clock
+ \arg RCU_I2Cx (x=0,1): I2C clock
+ \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
+ \arg RCU_PMU: PMU clock
+ \arg RCU_DAC: DAC clock
+ \arg RCU_RTC: RTC clock
+ \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
+ \arg RCU_SDIO: SDIO clock(not available for CL series)
+ \arg RCU_BKPI: BKP interface clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_enable(rcu_periph_enum periph)
+{
+ RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief disable the peripherals clock
+ \param[in] periph: RCU peripherals, refer to rcu_periph_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock
+ \arg RCU_AF: alternate function clock
+ \arg RCU_CRC: CRC clock
+ \arg RCU_DMAx (x=0,1): DMA clock
+ \arg RCU_ENET: ENET clock(CL series available)
+ \arg RCU_ENETTX: ENETTX clock(CL series available)
+ \arg RCU_ENETRX: ENETRX clock(CL series available)
+ \arg RCU_USBD: USBD clock(HD,XD series available)
+ \arg RCU_USBFS: USBFS clock(CL series available)
+ \arg RCU_EXMC: EXMC clock
+ \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock
+ \arg RCU_WWDGT: WWDGT clock
+ \arg RCU_SPIx (x=0,1,2): SPI clock
+ \arg RCU_USARTx (x=0,1,2): USART clock
+ \arg RCU_UARTx (x=3,4): UART clock
+ \arg RCU_I2Cx (x=0,1): I2C clock
+ \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock
+ \arg RCU_PMU: PMU clock
+ \arg RCU_DAC: DAC clock
+ \arg RCU_RTC: RTC clock
+ \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock
+ \arg RCU_SDIO: SDIO clock(not available for CL series)
+ \arg RCU_BKPI: BKP interface clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_disable(rcu_periph_enum periph)
+{
+ RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief enable the peripherals clock when sleep mode
+ \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_FMC_SLP: FMC clock
+ \arg RCU_SRAM_SLP: SRAM clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
+{
+ RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief disable the peripherals clock when sleep mode
+ \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_FMC_SLP: FMC clock
+ \arg RCU_SRAM_SLP: SRAM clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
+{
+ RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief reset the peripherals
+ \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
+ \arg RCU_AFRST : reset alternate function clock
+ \arg RCU_ENETRST: reset ENET(CL series available)
+ \arg RCU_USBDRST: reset USBD(HD,XD series available)
+ \arg RCU_USBFSRST: reset USBFS(CL series available)
+ \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER
+ \arg RCU_WWDGTRST: reset WWDGT
+ \arg RCU_SPIxRST (x=0,1,2): reset SPI
+ \arg RCU_USARTxRST (x=0,1,2): reset USART
+ \arg RCU_UARTxRST (x=3,4): reset UART
+ \arg RCU_I2CxRST (x=0,1): reset I2C
+ \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
+ \arg RCU_PMURST: reset PMU
+ \arg RCU_DACRST: reset DAC
+ \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC
+ \arg RCU_BKPIRST: reset BKPI
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
+{
+ RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+ \brief disable reset the peripheral
+ \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports
+ \arg RCU_AFRST : reset alternate function clock
+ \arg RCU_ENETRST: reset ENET(CL series available)
+ \arg RCU_USBDRST: reset USBD(HD,XD series available)
+ \arg RCU_USBFSRST: reset USBFS(CL series available)
+ \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER
+ \arg RCU_WWDGTRST: reset WWDGT
+ \arg RCU_SPIxRST (x=0,1,2): reset SPI
+ \arg RCU_USARTxRST (x=0,1,2): reset USART
+ \arg RCU_UARTxRST (x=3,4): reset UART
+ \arg RCU_I2CxRST (x=0,1): reset I2C
+ \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN
+ \arg RCU_PMURST: reset PMU
+ \arg RCU_DACRST: reset DAC
+ \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC
+ \arg RCU_BKPIRST: reset BKPI
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
+{
+ RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+ \brief reset the BKP domain
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_bkp_reset_enable(void)
+{
+ RCU_BDCTL |= RCU_BDCTL_BKPRST;
+}
+
+/*!
+ \brief disable the BKP domain reset
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_bkp_reset_disable(void)
+{
+ RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
+}
+
+/*!
+ \brief configure the system clock source
+ \param[in] ck_sys: system clock source select
+ only one parameter can be selected which is shown as below:
+ \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
+ \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
+ \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
+ \param[out] none
+ \retval none
+*/
+void rcu_system_clock_source_config(uint32_t ck_sys)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG0;
+ /* reset the SCS bits and set according to ck_sys */
+ reg &= ~RCU_CFG0_SCS;
+ RCU_CFG0 = (reg | ck_sys);
+}
+
+/*!
+ \brief get the system clock source
+ \param[in] none
+ \param[out] none
+ \retval which clock is selected as CK_SYS source
+ \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source
+ \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
+ \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source
+*/
+uint32_t rcu_system_clock_source_get(void)
+{
+ return (RCU_CFG0 & RCU_CFG0_SCSS);
+}
+
+/*!
+ \brief configure the AHB clock prescaler selection
+ \param[in] ck_ahb: AHB clock prescaler selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
+ \param[out] none
+ \retval none
+*/
+void rcu_ahb_clock_config(uint32_t ck_ahb)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG0;
+
+ /* reset the AHBPSC bits and set according to ck_ahb */
+ reg &= ~RCU_CFG0_AHBPSC;
+ RCU_CFG0 = (reg | ck_ahb);
+}
+
+/*!
+ \brief configure the APB1 clock prescaler selection
+ \param[in] ck_apb1: APB1 clock prescaler selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
+ \param[out] none
+ \retval none
+*/
+void rcu_apb1_clock_config(uint32_t ck_apb1)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG0;
+
+ /* reset the APB1PSC and set according to ck_apb1 */
+ reg &= ~RCU_CFG0_APB1PSC;
+ RCU_CFG0 = (reg | ck_apb1);
+}
+
+/*!
+ \brief configure the APB2 clock prescaler selection
+ \param[in] ck_apb2: APB2 clock prescaler selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
+ \param[out] none
+ \retval none
+*/
+void rcu_apb2_clock_config(uint32_t ck_apb2)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG0;
+
+ /* reset the APB2PSC and set according to ck_apb2 */
+ reg &= ~RCU_CFG0_APB2PSC;
+ RCU_CFG0 = (reg | ck_apb2);
+}
+
+/*!
+ \brief configure the CK_OUT0 clock source
+ \param[in] ckout0_src: CK_OUT0 clock source selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_CKOUT0SRC_NONE: no clock selected
+ \arg RCU_CKOUT0SRC_CKSYS: system clock selected
+ \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected
+ \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected
+ \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
+ \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected
+ \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected
+ \arg RCU_CKOUT0SRC_EXT1: EXT1 selected
+ \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected
+ \param[out] none
+ \retval none
+*/
+void rcu_ckout0_config(uint32_t ckout0_src)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG0;
+
+ /* reset the CKOUT0SRC, set according to ckout0_src */
+ reg &= ~RCU_CFG0_CKOUT0SEL;
+ RCU_CFG0 = (reg | ckout0_src);
+}
+
+/*!
+ \brief configure the main PLL clock
+ \param[in] pll_src: PLL clock source selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL
+ \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL
+ \param[in] pll_mul: PLL clock multiplication factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32)
+ \param[out] none
+ \retval none
+*/
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
+{
+ uint32_t reg = 0U;
+
+ reg = RCU_CFG0;
+
+ /* PLL clock source and multiplication factor configuration */
+ reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+ reg |= (pll_src | pll_mul);
+
+ RCU_CFG0 = reg;
+}
+
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+/*!
+ \brief configure the PREDV0 division factor
+ \param[in] predv0_div: PREDV0 division factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PREDV0_DIVx, x = 1,2
+ \param[out] none
+ \retval none
+*/
+void rcu_predv0_config(uint32_t predv0_div)
+{
+ uint32_t reg = 0U;
+
+ reg = RCU_CFG0;
+ /* reset PREDV0 bit */
+ reg &= ~RCU_CFG0_PREDV0;
+ if(RCU_PREDV0_DIV2 == predv0_div){
+ /* set the PREDV0 bit */
+ reg |= RCU_CFG0_PREDV0;
+ }
+
+ RCU_CFG0 = reg;
+}
+#elif defined(GD32F10X_CL)
+/*!
+ \brief configure the PREDV0 division factor and clock source
+ \param[in] predv0_source: PREDV0 input clock source selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock
+ \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock
+ \param[in] predv0_div: PREDV0 division factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PREDV0_DIVx, x = 1..16
+ \param[out] none
+ \retval none
+*/
+void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div)
+{
+ uint32_t reg = 0U;
+
+ reg = RCU_CFG1;
+ /* reset PREDV0SEL and PREDV0 bits */
+ reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0);
+ /* set the PREDV0SEL and PREDV0 division factor */
+ reg |= (predv0_source | predv0_div);
+
+ RCU_CFG1 = reg;
+}
+
+/*!
+ \brief configure the PREDV1 division factor
+ \param[in] predv1_div: PREDV1 division factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PREDV1_DIVx, x = 1..16
+ \param[out] none
+ \retval none
+*/
+void rcu_predv1_config(uint32_t predv1_div)
+{
+ uint32_t reg = 0U;
+
+ reg = RCU_CFG1;
+ /* reset the PREDV1 bits */
+ reg &= ~RCU_CFG1_PREDV1;
+ /* set the PREDV1 division factor */
+ reg |= predv1_div;
+
+ RCU_CFG1 = reg;
+}
+
+/*!
+ \brief configure the PLL1 clock
+ \param[in] pll_mul: PLL clock multiplication factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PLL1_MULx (x = 8..16, 20)
+ \param[out] none
+ \retval none
+*/
+void rcu_pll1_config(uint32_t pll_mul)
+{
+ RCU_CFG1 &= ~RCU_CFG1_PLL1MF;
+ RCU_CFG1 |= pll_mul;
+}
+
+/*!
+ \brief configure the PLL2 clock
+ \param[in] pll_mul: PLL clock multiplication factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_PLL2_MULx (x = 8..16, 20)
+ \param[out] none
+ \retval none
+*/
+void rcu_pll2_config(uint32_t pll_mul)
+{
+ RCU_CFG1 &= ~RCU_CFG1_PLL2MF;
+ RCU_CFG1 |= pll_mul;
+}
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+/*!
+ \brief configure the ADC prescaler factor
+ \param[in] adc_psc: ADC prescaler factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2
+ \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4
+ \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6
+ \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8
+ \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12
+ \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16
+ \param[out] none
+ \retval none
+*/
+void rcu_adc_clock_config(uint32_t adc_psc)
+{
+ uint32_t reg0;
+
+ /* reset the ADCPSC bits */
+ reg0 = RCU_CFG0;
+ reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
+
+ /* set the ADC prescaler factor */
+ switch(adc_psc){
+ case RCU_CKADC_CKAPB2_DIV2:
+ case RCU_CKADC_CKAPB2_DIV4:
+ case RCU_CKADC_CKAPB2_DIV6:
+ case RCU_CKADC_CKAPB2_DIV8:
+ reg0 |= (adc_psc << 14);
+ break;
+
+ case RCU_CKADC_CKAPB2_DIV12:
+ case RCU_CKADC_CKAPB2_DIV16:
+ adc_psc &= ~BIT(2);
+ reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2);
+ break;
+
+ default:
+ break;
+ }
+
+ /* set the register */
+ RCU_CFG0 = reg0;
+}
+
+/*!
+ \brief configure the USBD/USBFS prescaler factor
+ \param[in] usb_psc: USB prescaler factor
+ only one parameter can be selected which is shown as below:
+ \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5
+ \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1
+ \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5
+ \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2
+ \param[out] none
+ \retval none
+*/
+void rcu_usb_clock_config(uint32_t usb_psc)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG0;
+
+ /* configure the USBD/USBFS prescaler factor */
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ reg &= ~RCU_CFG0_USBDPSC;
+#elif defined(GD32F10X_CL)
+ reg &= ~RCU_CFG0_USBFSPSC;
+#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */
+
+ RCU_CFG0 = (reg | usb_psc);
+}
+
+/*!
+ \brief configure the RTC clock source selection
+ \param[in] rtc_clock_source: RTC clock source selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_RTCSRC_NONE: no clock selected
+ \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
+ \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
+ \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock
+ \param[out] none
+ \retval none
+*/
+void rcu_rtc_clock_config(uint32_t rtc_clock_source)
+{
+ uint32_t reg;
+
+ reg = RCU_BDCTL;
+ /* reset the RTCSRC bits and set according to rtc_clock_source */
+ reg &= ~RCU_BDCTL_RTCSRC;
+ RCU_BDCTL = (reg | rtc_clock_source);
+}
+
+#ifdef GD32F10X_CL
+/*!
+ \brief configure the I2S1 clock source selection
+ \param[in] i2s_clock_source: I2S1 clock source selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock
+ \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock
+ \param[out] none
+ \retval none
+*/
+void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG1;
+ /* reset the I2S1SEL bit and set according to i2s_clock_source */
+ reg &= ~RCU_CFG1_I2S1SEL;
+ RCU_CFG1 = (reg | i2s_clock_source);
+}
+
+/*!
+ \brief configure the I2S2 clock source selection
+ \param[in] i2s_clock_source: I2S2 clock source selection
+ only one parameter can be selected which is shown as below:
+ \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock
+ \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock
+ \param[out] none
+ \retval none
+*/
+void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
+{
+ uint32_t reg;
+
+ reg = RCU_CFG1;
+ /* reset the I2S2SEL bit and set according to i2s_clock_source */
+ reg &= ~RCU_CFG1_I2S2SEL;
+ RCU_CFG1 = (reg | i2s_clock_source);
+}
+#endif /* GD32F10X_CL */
+
+/*!
+ \brief get the clock stabilization and periphral reset flags
+ \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
+ \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
+ \arg RCU_FLAG_PLLSTB: PLL stabilization flag
+ \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only)
+ \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only)
+ \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
+ \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
+ \arg RCU_FLAG_EPRST: external PIN reset flag
+ \arg RCU_FLAG_PORRST: power reset flag
+ \arg RCU_FLAG_SWRST: software reset flag
+ \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag
+ \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag
+ \arg RCU_FLAG_LPRST: low-power reset flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus rcu_flag_get(rcu_flag_enum flag)
+{
+ /* get the rcu flag */
+ if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear all the reset flag
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_all_reset_flag_clear(void)
+{
+ RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
+}
+
+/*!
+ \brief get the clock stabilization interrupt and ckm flags
+ \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
+ \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
+ \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
+ \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
+ \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
+ \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only)
+ \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only)
+ \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
+{
+ /* get the rcu interrupt flag */
+ if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear the interrupt flags
+ \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only)
+ \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only)
+ \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
+ \param[out] none
+ \retval none
+*/
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
+{
+ RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
+}
+
+/*!
+ \brief enable the stabilization interrupt
+ \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
+ Only one parameter can be selected which is shown as below:
+ \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
+ \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
+ \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
+ \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
+ \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
+ \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
+ \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
+ \param[out] none
+ \retval none
+*/
+void rcu_interrupt_enable(rcu_int_enum stab_int)
+{
+ RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
+}
+
+/*!
+ \brief disable the stabilization interrupt
+ \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
+ \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
+ \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
+ \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
+ \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
+ \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only)
+ \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only)
+ \param[out] none
+ \retval none
+*/
+void rcu_interrupt_disable(rcu_int_enum stab_int)
+{
+ RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
+}
+
+/*!
+ \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
+ \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
+ \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
+ \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
+ \arg RCU_PLL_CK: phase locked loop(PLL)
+ \arg RCU_PLL1_CK: phase locked loop 1(CL series only)
+ \arg RCU_PLL2_CK: phase locked loop 2(CL series only)
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
+{
+ uint32_t stb_cnt = 0U;
+ ErrStatus reval = ERROR;
+ FlagStatus osci_stat = RESET;
+
+ switch(osci){
+ /* wait HXTAL stable */
+ case RCU_HXTAL:
+ while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
+ reval = SUCCESS;
+ }
+ break;
+
+ /* wait LXTAL stable */
+ case RCU_LXTAL:
+ while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
+ reval = SUCCESS;
+ }
+ break;
+
+ /* wait IRC8M stable */
+ case RCU_IRC8M:
+ while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
+ reval = SUCCESS;
+ }
+ break;
+
+ /* wait IRC40K stable */
+ case RCU_IRC40K:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
+ reval = SUCCESS;
+ }
+ break;
+
+ /* wait PLL stable */
+ case RCU_PLL_CK:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
+ reval = SUCCESS;
+ }
+ break;
+
+#ifdef GD32F10X_CL
+ /* wait PLL1 stable */
+ case RCU_PLL1_CK:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){
+ reval = SUCCESS;
+ }
+ break;
+ /* wait PLL2 stable */
+ case RCU_PLL2_CK:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){
+ reval = SUCCESS;
+ }
+ break;
+#endif /* GD32F10X_CL */
+
+ default:
+ break;
+ }
+
+ /* return value */
+ return reval;
+}
+
+/*!
+ \brief turn on the oscillator
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
+ \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
+ \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
+ \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
+ \arg RCU_PLL_CK: phase locked loop(PLL)
+ \arg RCU_PLL1_CK: phase locked loop 1(CL series only)
+ \arg RCU_PLL2_CK: phase locked loop 2(CL series only)
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_on(rcu_osci_type_enum osci)
+{
+ RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+ \brief turn off the oscillator
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
+ \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
+ \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M)
+ \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K)
+ \arg RCU_PLL_CK: phase locked loop(PLL)
+ \arg RCU_PLL1_CK: phase locked loop 1(CL series only)
+ \arg RCU_PLL2_CK: phase locked loop 2(CL series only)
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_off(rcu_osci_type_enum osci)
+{
+ RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+ \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
+ \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
+{
+ uint32_t reg;
+
+ switch(osci){
+ /* enable HXTAL to bypass mode */
+ case RCU_HXTAL:
+ reg = RCU_CTL;
+ RCU_CTL &= ~RCU_CTL_HXTALEN;
+ RCU_CTL = (reg | RCU_CTL_HXTALBPS);
+ break;
+ /* enable LXTAL to bypass mode */
+ case RCU_LXTAL:
+ reg = RCU_BDCTL;
+ RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+ RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
+ break;
+ case RCU_IRC8M:
+ case RCU_IRC40K:
+ case RCU_PLL_CK:
+#ifdef GD32F10X_CL
+ case RCU_PLL1_CK:
+ case RCU_PLL2_CK:
+#endif /* GD32F10X_CL */
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_HXTAL: high speed crystal oscillator(HXTAL)
+ \arg RCU_LXTAL: low speed crystal oscillator(LXTAL)
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
+{
+ uint32_t reg;
+
+ switch(osci){
+ /* disable HXTAL to bypass mode */
+ case RCU_HXTAL:
+ reg = RCU_CTL;
+ RCU_CTL &= ~RCU_CTL_HXTALEN;
+ RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
+ break;
+ /* disable LXTAL to bypass mode */
+ case RCU_LXTAL:
+ reg = RCU_BDCTL;
+ RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+ RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
+ break;
+ case RCU_IRC8M:
+ case RCU_IRC40K:
+ case RCU_PLL_CK:
+#ifdef GD32F10X_CL
+ case RCU_PLL1_CK:
+ case RCU_PLL2_CK:
+#endif /* GD32F10X_CL */
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief enable the HXTAL clock monitor
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+
+void rcu_hxtal_clock_monitor_enable(void)
+{
+ RCU_CTL |= RCU_CTL_CKMEN;
+}
+
+/*!
+ \brief disable the HXTAL clock monitor
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_hxtal_clock_monitor_disable(void)
+{
+ RCU_CTL &= ~RCU_CTL_CKMEN;
+}
+
+/*!
+ \brief set the IRC8M adjust value
+ \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
+ \param[out] none
+ \retval none
+*/
+void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
+{
+ uint32_t reg;
+
+ reg = RCU_CTL;
+ /* reset the IRC8MADJ bits and set according to irc8m_adjval */
+ reg &= ~RCU_CTL_IRC8MADJ;
+ RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3));
+}
+
+/*!
+ \brief deep-sleep mode voltage select
+ \param[in] dsvol: deep sleep mode voltage
+ only one parameter can be selected which is shown as below:
+ \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V
+ \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V
+ \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
+ \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
+ \param[out] none
+ \retval none
+*/
+void rcu_deepsleep_voltage_set(uint32_t dsvol)
+{
+ dsvol &= RCU_DSV_DSLPVS;
+ RCU_DSV = dsvol;
+}
+
+/*!
+ \brief get the system clock, bus and peripheral clock frequency
+ \param[in] clock: the clock frequency which to get
+ only one parameter can be selected which is shown as below:
+ \arg CK_SYS: system clock frequency
+ \arg CK_AHB: AHB clock frequency
+ \arg CK_APB1: APB1 clock frequency
+ \arg CK_APB2: APB2 clock frequency
+ \param[out] none
+ \retval clock frequency of system, AHB, APB1, APB2
+*/
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
+{
+ uint32_t sws, ck_freq = 0U;
+ uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
+ uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp;
+#ifdef GD32F10X_CL
+ uint32_t predv0, predv1, pll1mf;
+#endif /* GD32F10X_CL */
+
+ /* exponent of AHB, APB1 and APB2 clock divider */
+ uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+ sws = GET_BITS(RCU_CFG0, 2, 3);
+ switch(sws){
+ /* IRC8M is selected as CK_SYS */
+ case SEL_IRC8M:
+ cksys_freq = IRC8M_VALUE;
+ break;
+ /* HXTAL is selected as CK_SYS */
+ case SEL_HXTAL:
+ cksys_freq = HXTAL_VALUE;
+ break;
+ /* PLL is selected as CK_SYS */
+ case SEL_PLL:
+ /* PLL clock source selection, HXTAL or IRC8M/2 */
+ pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
+
+ if(RCU_PLLSRC_HXTAL == pllsel) {
+ /* PLL clock source is HXTAL */
+ ck_src = HXTAL_VALUE;
+
+#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD))
+ predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0);
+ /* PREDV0 input source clock divided by 2 */
+ if(RCU_CFG0_PREDV0 == predv0sel){
+ ck_src = HXTAL_VALUE/2U;
+ }
+#elif defined(GD32F10X_CL)
+ predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
+ /* source clock use PLL1 */
+ if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
+ predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
+ pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
+ if(17U == pll1mf){
+ pll1mf = 20U;
+ }
+ ck_src = (ck_src / predv1) * pll1mf;
+ }
+ predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
+ ck_src /= predv0;
+#endif /* GD32F10X_HD and GD32F10X_XD */
+ }else{
+ /* PLL clock source is IRC8M/2 */
+ ck_src = IRC8M_VALUE/2U;
+ }
+
+ /* PLL multiplication factor */
+ pllmf = GET_BITS(RCU_CFG0, 18, 21);
+ if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
+ pllmf |= 0x10U;
+ }
+ if(pllmf < 15U){
+ pllmf += 2U;
+ }else{
+ pllmf += 1U;
+ }
+
+ cksys_freq = ck_src * pllmf;
+
+ #ifdef GD32F10X_CL
+ if(15U == pllmf){
+ /* PLL source clock multiply by 6.5 */
+ cksys_freq = ck_src * 6U + ck_src / 2U;
+ }
+ #endif /* GD32F10X_CL */
+
+ break;
+ /* IRC8M is selected as CK_SYS */
+ default:
+ cksys_freq = IRC8M_VALUE;
+ break;
+ }
+
+ /* calculate AHB clock frequency */
+ idx = GET_BITS(RCU_CFG0, 4, 7);
+ clk_exp = ahb_exp[idx];
+ ahb_freq = cksys_freq >> clk_exp;
+
+ /* calculate APB1 clock frequency */
+ idx = GET_BITS(RCU_CFG0, 8, 10);
+ clk_exp = apb1_exp[idx];
+ apb1_freq = ahb_freq >> clk_exp;
+
+ /* calculate APB2 clock frequency */
+ idx = GET_BITS(RCU_CFG0, 11, 13);
+ clk_exp = apb2_exp[idx];
+ apb2_freq = ahb_freq >> clk_exp;
+
+ /* return the clocks frequency */
+ switch(clock){
+ case CK_SYS:
+ ck_freq = cksys_freq;
+ break;
+ case CK_AHB:
+ ck_freq = ahb_freq;
+ break;
+ case CK_APB1:
+ ck_freq = apb1_freq;
+ break;
+ case CK_APB2:
+ ck_freq = apb2_freq;
+ break;
+ default:
+ break;
+ }
+ return ck_freq;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c
new file mode 100644
index 0000000..950656d
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c
@@ -0,0 +1,273 @@
+/*!
+ \file gd32f10x_rtc.c
+ \brief RTC driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_rtc.h"
+
+/* RTC register high / low bits mask */
+#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */
+#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */
+
+/* RTC register high bits offset */
+#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U)
+
+/*!
+ \brief enter RTC configuration mode
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rtc_configuration_mode_enter(void)
+{
+ RTC_CTL |= RTC_CTL_CMF;
+}
+
+/*!
+ \brief exit RTC configuration mode
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rtc_configuration_mode_exit(void)
+{
+ RTC_CTL &= ~RTC_CTL_CMF;
+}
+
+/*!
+ \brief set RTC counter value
+ \param[in] cnt: RTC counter value
+ \param[out] none
+ \retval none
+*/
+void rtc_counter_set(uint32_t cnt)
+{
+ rtc_configuration_mode_enter();
+ /* set the RTC counter high bits */
+ RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET);
+ /* set the RTC counter low bits */
+ RTC_CNTL = (cnt & RTC_LOW_BITS_MASK);
+ rtc_configuration_mode_exit();
+}
+
+/*!
+ \brief set RTC prescaler value
+ \param[in] psc: RTC prescaler value
+ \param[out] none
+ \retval none
+*/
+void rtc_prescaler_set(uint32_t psc)
+{
+ rtc_configuration_mode_enter();
+ /* set the RTC prescaler high bits */
+ RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET);
+ /* set the RTC prescaler low bits */
+ RTC_PSCL = (psc & RTC_LOW_BITS_MASK);
+ rtc_configuration_mode_exit();
+}
+
+/*!
+ \brief wait RTC last write operation finished flag set
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rtc_lwoff_wait(void)
+{
+ /* loop until LWOFF flag is set */
+ while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
+ }
+}
+
+/*!
+ \brief wait RTC registers synchronized flag set
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rtc_register_sync_wait(void)
+{
+ /* clear RSYNF flag */
+ RTC_CTL &= ~RTC_CTL_RSYNF;
+ /* loop until RSYNF flag is set */
+ while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
+ }
+}
+
+/*!
+ \brief set RTC alarm value
+ \param[in] alarm: RTC alarm value
+ \param[out] none
+ \retval none
+*/
+void rtc_alarm_config(uint32_t alarm)
+{
+ rtc_configuration_mode_enter();
+ /* set the alarm high bits */
+ RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET);
+ /* set the alarm low bits */
+ RTC_ALRML = (alarm & RTC_LOW_BITS_MASK);
+ rtc_configuration_mode_exit();
+}
+
+/*!
+ \brief get RTC counter value
+ \param[in] none
+ \param[out] none
+ \retval RTC counter value
+*/
+uint32_t rtc_counter_get(void)
+{
+ uint32_t temp = 0x0U;
+
+ temp = RTC_CNTL;
+ temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET);
+ return temp;
+}
+
+/*!
+ \brief get RTC divider value
+ \param[in] none
+ \param[out] none
+ \retval RTC divider value
+*/
+uint32_t rtc_divider_get(void)
+{
+ uint32_t temp = 0x00U;
+
+ temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET);
+ temp |= RTC_DIVL;
+ return temp;
+}
+
+/*!
+ \brief get RTC flag status
+ \param[in] flag: specify which flag status to get
+ only one parameter can be selected which is shown as below:
+ \arg RTC_FLAG_SECOND: second interrupt flag
+ \arg RTC_FLAG_ALARM: alarm interrupt flag
+ \arg RTC_FLAG_OVERFLOW: overflow interrupt flag
+ \arg RTC_FLAG_RSYN: registers synchronized flag
+ \arg RTC_FLAG_LWOF: last write operation finished flag
+ \param[out] none
+ \retval SET or RESET
+*/
+FlagStatus rtc_flag_get(uint32_t flag)
+{
+ if(RESET != (RTC_CTL & flag)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear RTC flag status
+ \param[in] flag: specify which flag status to clear
+ one or more parameters can be selected which are shown as below:
+ \arg RTC_FLAG_SECOND: second interrupt flag
+ \arg RTC_FLAG_ALARM: alarm interrupt flag
+ \arg RTC_FLAG_OVERFLOW: overflow interrupt flag
+ \arg RTC_FLAG_RSYN: registers synchronized flag
+ \param[out] none
+ \retval none
+*/
+void rtc_flag_clear(uint32_t flag)
+{
+ /* clear RTC flag */
+ RTC_CTL &= ~flag;
+}
+
+/*!
+ \brief get RTC interrupt flag status
+ \param[in] flag: specify which flag status to get
+ only one parameter can be selected which is shown as below:
+ \arg RTC_INT_FLAG_SECOND: second interrupt flag
+ \arg RTC_INT_FLAG_ALARM: alarm interrupt flag
+ \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
+ \param[out] none
+ \retval SET or RESET
+*/
+FlagStatus rtc_interrupt_flag_get(uint32_t flag)
+{
+ if(RESET != (RTC_CTL & flag)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear RTC interrupt flag status
+ \param[in] flag: specify which flag status to clear
+ one or more parameters can be selected which are shown as below:
+ \arg RTC_INT_FLAG_SECOND: second interrupt flag
+ \arg RTC_INT_FLAG_ALARM: alarm interrupt flag
+ \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
+ \param[out] none
+ \retval none
+*/
+void rtc_interrupt_flag_clear(uint32_t flag)
+{
+ /* clear RTC interrupt flag */
+ RTC_CTL &= ~flag;
+}
+
+/*!
+ \brief enable RTC interrupt
+ \param[in] interrupt: specify which interrupt to enbale
+ one or more parameters can be selected which are shown as below:
+ \arg RTC_INT_SECOND: second interrupt
+ \arg RTC_INT_ALARM: alarm interrupt
+ \arg RTC_INT_OVERFLOW: overflow interrupt
+ \param[out] none
+ \retval none
+*/
+void rtc_interrupt_enable(uint32_t interrupt)
+{
+ RTC_INTEN |= interrupt;
+}
+
+/*!
+ \brief disable RTC interrupt
+ \param[in] interrupt: specify which interrupt to disbale
+ one or more parameters can be selected which are shown as below:
+ \arg RTC_INT_SECOND: second interrupt
+ \arg RTC_INT_ALARM: alarm interrupt
+ \arg RTC_INT_OVERFLOW: overflow interrupt
+ \param[out] none
+ \retval none
+*/
+void rtc_interrupt_disable(uint32_t interrupt)
+{
+ RTC_INTEN &= ~interrupt;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c
new file mode 100644
index 0000000..f047c41
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c
@@ -0,0 +1,804 @@
+/*!
+ \file gd32f10x_sdio.c
+ \brief SDIO driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_sdio.h"
+
+#define DEFAULT_RESET_VALUE 0x00000000U
+
+/*!
+ \brief deinitialize the SDIO
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_deinit(void)
+{
+ SDIO_PWRCTL = DEFAULT_RESET_VALUE;
+ SDIO_CLKCTL = DEFAULT_RESET_VALUE;
+ SDIO_CMDAGMT = DEFAULT_RESET_VALUE;
+ SDIO_CMDCTL = DEFAULT_RESET_VALUE;
+ SDIO_DATATO = DEFAULT_RESET_VALUE;
+ SDIO_DATALEN = DEFAULT_RESET_VALUE;
+ SDIO_DATACTL = DEFAULT_RESET_VALUE;
+ SDIO_INTC = DEFAULT_RESET_VALUE;
+ SDIO_INTEN = DEFAULT_RESET_VALUE;
+}
+
+/*!
+ \brief configure the SDIO clock
+ \param[in] clock_edge: SDIO_CLK clock edge
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK
+ \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK
+ \param[in] clock_bypass: clock bypass
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass
+ \arg SDIO_CLOCKBYPASS_DISABLE: no bypass
+ \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle
+ \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on
+ \param[in] clock_division: clock division, less than 256
+ \param[out] none
+ \retval none
+*/
+void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
+{
+ uint32_t clock_config = 0U;
+ clock_config = SDIO_CLKCTL;
+ /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */
+ clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV);
+
+ /* configure the SDIO_CLKCTL according to the parameters */
+ clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division);
+ SDIO_CLKCTL = clock_config;
+}
+
+/*!
+ \brief enable hardware clock control
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_hardware_clock_enable(void)
+{
+ SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN;
+}
+
+/*!
+ \brief disable hardware clock control
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_hardware_clock_disable(void)
+{
+ SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN;
+}
+
+/*!
+ \brief set different SDIO card bus mode
+ \param[in] bus_mode: SDIO card bus mode
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode
+ \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode
+ \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode
+ \param[out] none
+ \retval none
+*/
+void sdio_bus_mode_set(uint32_t bus_mode)
+{
+ /* reset the SDIO card bus mode bits and set according to bus_mode */
+ SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE;
+ SDIO_CLKCTL |= bus_mode;
+}
+
+/*!
+ \brief set the SDIO power state
+ \param[in] power_state: SDIO power state
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_POWER_ON: SDIO power on
+ \arg SDIO_POWER_OFF: SDIO power off
+ \param[out] none
+ \retval none
+*/
+void sdio_power_state_set(uint32_t power_state)
+{
+ SDIO_PWRCTL = power_state;
+}
+
+/*!
+ \brief get the SDIO power state
+ \param[in] none
+ \param[out] none
+ \retval SDIO power state
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_POWER_ON: SDIO power on
+ \arg SDIO_POWER_OFF: SDIO power off
+*/
+uint32_t sdio_power_state_get(void)
+{
+ return SDIO_PWRCTL;
+}
+
+/*!
+ \brief enable SDIO_CLK clock output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_clock_enable(void)
+{
+ SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN;
+}
+
+/*!
+ \brief disable SDIO_CLK clock output
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_clock_disable(void)
+{
+ SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN;
+}
+
+/*!
+ \brief configure the command and response
+ \param[in] cmd_index: command index, refer to the related specifications
+ \param[in] cmd_argument: command argument, refer to the related specifications
+ \param[in] response_type: response type
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_RESPONSETYPE_NO: no response
+ \arg SDIO_RESPONSETYPE_SHORT: short response
+ \arg SDIO_RESPONSETYPE_LONG: long response
+ \param[out] none
+ \retval none
+*/
+void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
+{
+ uint32_t cmd_config = 0U;
+ /* reset the command index, command argument and response type */
+ SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT;
+ SDIO_CMDAGMT = cmd_argument;
+ cmd_config = SDIO_CMDCTL;
+ cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP);
+ /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */
+ cmd_config |= (cmd_index | response_type);
+ SDIO_CMDCTL = cmd_config;
+}
+
+/*!
+ \brief set the command state machine wait type
+ \param[in] wait_type: wait type
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_WAITTYPE_NO: not wait interrupt
+ \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt
+ \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer
+ \param[out] none
+ \retval none
+*/
+void sdio_wait_type_set(uint32_t wait_type)
+{
+ /* reset INTWAIT and WAITDEND */
+ SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND);
+ /* set the wait type according to wait_type */
+ SDIO_CMDCTL |= wait_type;
+}
+
+/*!
+ \brief enable the CSM(command state machine)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_csm_enable(void)
+{
+ SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN;
+}
+
+/*!
+ \brief disable the CSM(command state machine)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_csm_disable(void)
+{
+ SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN;
+}
+
+/*!
+ \brief get the last response command index
+ \param[in] none
+ \param[out] none
+ \retval last response command index
+*/
+uint8_t sdio_command_index_get(void)
+{
+ return (uint8_t)SDIO_RSPCMDIDX;
+}
+
+/*!
+ \brief get the response for the last received command
+ \param[in] responsex: SDIO response
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96]
+ \arg SDIO_RESPONSE1: card response[95:64]
+ \arg SDIO_RESPONSE2: card response[63:32]
+ \arg SDIO_RESPONSE3: card response[31:1], plus bit 0
+ \param[out] none
+ \retval response for the last received command
+*/
+uint32_t sdio_response_get(uint32_t responsex)
+{
+ uint32_t resp_content = 0U;
+ switch(responsex){
+ case SDIO_RESPONSE0:
+ resp_content = SDIO_RESP0;
+ break;
+ case SDIO_RESPONSE1:
+ resp_content = SDIO_RESP1;
+ break;
+ case SDIO_RESPONSE2:
+ resp_content = SDIO_RESP2;
+ break;
+ case SDIO_RESPONSE3:
+ resp_content = SDIO_RESP3;
+ break;
+ default:
+ break;
+ }
+ return resp_content;
+}
+
+/*!
+ \brief configure the data timeout, data length and data block size
+ \param[in] data_timeout: data timeout period in card bus clock periods
+ \param[in] data_length: number of data bytes to be transferred
+ \param[in] data_blocksize: size of data block for block transfer
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte
+ \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes
+ \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes
+ \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes
+ \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes
+ \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes
+ \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes
+ \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes
+ \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes
+ \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes
+ \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes
+ \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes
+ \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes
+ \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes
+ \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes
+ \param[out] none
+ \retval none
+*/
+void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
+{
+ /* reset data timeout, data length and data block size */
+ SDIO_DATATO &= ~SDIO_DATATO_DATATO;
+ SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN;
+ SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ;
+ /* configure the related parameters of data */
+ SDIO_DATATO = data_timeout;
+ SDIO_DATALEN = data_length;
+ SDIO_DATACTL |= data_blocksize;
+}
+
+/*!
+ \brief configure the data transfer mode and direction
+ \param[in] transfer_mode: mode of data transfer
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_TRANSMODE_BLOCK: block transfer
+ \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer
+ \param[in] transfer_direction: data transfer direction, read or write
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_TRANSDIRECTION_TOCARD: write data to card
+ \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card
+ \param[out] none
+ \retval none
+*/
+void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction)
+{
+ uint32_t data_trans = 0U;
+ /* reset the data transfer mode, transfer direction and set according to the parameters */
+ data_trans = SDIO_DATACTL;
+ data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR);
+ data_trans |= (transfer_mode | transfer_direction);
+ SDIO_DATACTL = data_trans;
+}
+
+/*!
+ \brief enable the DSM(data state machine) for data transfer
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_dsm_enable(void)
+{
+ SDIO_DATACTL |= SDIO_DATACTL_DATAEN;
+}
+
+/*!
+ \brief disable the DSM(data state machine)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_dsm_disable(void)
+{
+ SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN;
+}
+
+/*!
+ \brief write data(one word) to the transmit FIFO
+ \param[in] data: 32-bit data write to card
+ \param[out] none
+ \retval none
+*/
+void sdio_data_write(uint32_t data)
+{
+ SDIO_FIFO = data;
+}
+
+/*!
+ \brief read data(one word) from the receive FIFO
+ \param[in] none
+ \param[out] none
+ \retval received data
+*/
+uint32_t sdio_data_read(void)
+{
+ return SDIO_FIFO;
+}
+
+/*!
+ \brief get the number of remaining data bytes to be transferred to card
+ \param[in] none
+ \param[out] none
+ \retval number of remaining data bytes to be transferred
+*/
+uint32_t sdio_data_counter_get(void)
+{
+ return SDIO_DATACNT;
+}
+
+/*!
+ \brief get the number of words remaining to be written or read from FIFO
+ \param[in] none
+ \param[out] none
+ \retval remaining number of words
+*/
+uint32_t sdio_fifo_counter_get(void)
+{
+ return SDIO_FIFOCNT;
+}
+
+/*!
+ \brief enable the DMA request for SDIO
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_dma_enable(void)
+{
+ SDIO_DATACTL |= SDIO_DATACTL_DMAEN;
+}
+
+/*!
+ \brief disable the DMA request for SDIO
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_dma_disable(void)
+{
+ SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN;
+}
+
+/*!
+ \brief get the flags state of SDIO
+ \param[in] flag: flags state of SDIO
+ one or more parameters can be selected which are shown as below:
+ \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
+ \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
+ \arg SDIO_FLAG_CMDTMOUT: command response timeout flag
+ \arg SDIO_FLAG_DTTMOUT: data timeout flag
+ \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
+ \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
+ \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
+ \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag
+ \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
+ \arg SDIO_FLAG_STBITE: start bit error in the bus flag
+ \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
+ \arg SDIO_FLAG_CMDRUN: command transmission in progress flag
+ \arg SDIO_FLAG_TXRUN: data transmission in progress flag
+ \arg SDIO_FLAG_RXRUN: data reception in progress flag
+ \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO
+ \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO
+ \arg SDIO_FLAG_TFF: transmit FIFO is full flag
+ \arg SDIO_FLAG_RFF: receive FIFO is full flag
+ \arg SDIO_FLAG_TFE: transmit FIFO is empty flag
+ \arg SDIO_FLAG_RFE: receive FIFO is empty flag
+ \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag
+ \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag
+ \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
+ \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus sdio_flag_get(uint32_t flag)
+{
+ FlagStatus temp_flag = RESET;
+ if(RESET != (SDIO_STAT & flag)){
+ temp_flag = SET;
+ }
+ return temp_flag;
+}
+
+/*!
+ \brief clear the pending flags of SDIO
+ \param[in] flag: flags state of SDIO
+ one or more parameters can be selected which are shown as below:
+ \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
+ \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
+ \arg SDIO_FLAG_CMDTMOUT: command response timeout flag
+ \arg SDIO_FLAG_DTTMOUT: data timeout flag
+ \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
+ \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
+ \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
+ \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag
+ \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
+ \arg SDIO_FLAG_STBITE: start bit error in the bus flag
+ \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
+ \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
+ \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
+ \param[out] none
+ \retval none
+*/
+void sdio_flag_clear(uint32_t flag)
+{
+ SDIO_INTC = flag;
+}
+
+/*!
+ \brief enable the SDIO interrupt
+ \param[in] int_flag: interrupt flags state of SDIO
+ one or more parameters can be selected which are shown as below:
+ \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
+ \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
+ \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
+ \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
+ \arg SDIO_INT_TXURE: SDIO TXURE interrupt
+ \arg SDIO_INT_RXORE: SDIO RXORE interrupt
+ \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
+ \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
+ \arg SDIO_INT_DTEND: SDIO DTEND interrupt
+ \arg SDIO_INT_STBITE: SDIO STBITE interrupt
+ \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
+ \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
+ \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt
+ \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt
+ \arg SDIO_INT_TFH: SDIO TFH interrupt
+ \arg SDIO_INT_RFH: SDIO RFH interrupt
+ \arg SDIO_INT_TFF: SDIO TFF interrupt
+ \arg SDIO_INT_RFF: SDIO RFF interrupt
+ \arg SDIO_INT_TFE: SDIO TFE interrupt
+ \arg SDIO_INT_RFE: SDIO RFE interrupt
+ \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
+ \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
+ \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
+ \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt
+ \param[out] none
+ \retval none
+*/
+void sdio_interrupt_enable(uint32_t int_flag)
+{
+ SDIO_INTEN |= int_flag;
+}
+
+/*!
+ \brief disable the SDIO interrupt
+ \param[in] int_flag: interrupt flags state of SDIO
+ one or more parameters can be selected which are shown as below:
+ \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
+ \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
+ \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
+ \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
+ \arg SDIO_INT_TXURE: SDIO TXURE interrupt
+ \arg SDIO_INT_RXORE: SDIO RXORE interrupt
+ \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
+ \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
+ \arg SDIO_INT_DTEND: SDIO DTEND interrupt
+ \arg SDIO_INT_STBITE: SDIO STBITE interrupt
+ \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
+ \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
+ \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt
+ \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt
+ \arg SDIO_INT_TFH: SDIO TFH interrupt
+ \arg SDIO_INT_RFH: SDIO RFH interrupt
+ \arg SDIO_INT_TFF: SDIO TFF interrupt
+ \arg SDIO_INT_RFF: SDIO RFF interrupt
+ \arg SDIO_INT_TFE: SDIO TFE interrupt
+ \arg SDIO_INT_RFE: SDIO RFE interrupt
+ \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
+ \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
+ \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
+ \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt
+ \param[out] none
+ \retval none
+*/
+void sdio_interrupt_disable(uint32_t int_flag)
+{
+ SDIO_INTEN &= ~int_flag;
+}
+
+/*!
+ \brief get the interrupt flags state of SDIO
+ \param[in] int_flag: interrupt flags state of SDIO
+ one or more parameters can be selected which are shown as below:
+ \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag
+ \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag
+ \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag
+ \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag
+ \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag
+ \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag
+ \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag
+ \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag
+ \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag
+ \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag
+ \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag
+ \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag
+ \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag
+ \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag
+ \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag
+ \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag
+ \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag
+ \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag
+ \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag
+ \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag
+ \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag
+ \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag
+ \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag
+ \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus sdio_interrupt_flag_get(uint32_t int_flag)
+{
+ if(RESET != (SDIO_STAT & int_flag)){
+ return SET;
+ }
+ return RESET;
+}
+
+/*!
+ \brief clear the interrupt pending flags of SDIO
+ \param[in] int_flag: interrupt flags state of SDIO
+ one or more parameters can be selected which are shown as below:
+ \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag
+ \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
+ \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag
+ \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag
+ \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag
+ \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag
+ \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag
+ \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag
+ \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
+ \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag
+ \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
+ \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag
+ \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
+ \param[out] none
+ \retval none
+*/
+void sdio_interrupt_flag_clear(uint32_t int_flag)
+{
+ SDIO_INTC = int_flag;
+}
+
+/*!
+ \brief enable the read wait mode(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_readwait_enable(void)
+{
+ SDIO_DATACTL |= SDIO_DATACTL_RWEN;
+}
+
+/*!
+ \brief disable the read wait mode(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_readwait_disable(void)
+{
+ SDIO_DATACTL &= ~SDIO_DATACTL_RWEN;
+}
+
+/*!
+ \brief enable the function that stop the read wait process(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_stop_readwait_enable(void)
+{
+ SDIO_DATACTL |= SDIO_DATACTL_RWSTOP;
+}
+
+/*!
+ \brief disable the function that stop the read wait process(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_stop_readwait_disable(void)
+{
+ SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP;
+}
+
+/*!
+ \brief set the read wait type(SD I/O only)
+ \param[in] readwait_type: SD I/O read wait type
+ only one parameter can be selected which is shown as below:
+ \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK
+ \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2]
+ \param[out] none
+ \retval none
+*/
+void sdio_readwait_type_set(uint32_t readwait_type)
+{
+ if(SDIO_READWAITTYPE_CLK == readwait_type){
+ SDIO_DATACTL |= SDIO_DATACTL_RWTYPE;
+ }else{
+ SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE;
+ }
+}
+
+/*!
+ \brief enable the SD I/O mode specific operation(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_operation_enable(void)
+{
+ SDIO_DATACTL |= SDIO_DATACTL_IOEN;
+}
+
+/*!
+ \brief disable the SD I/O mode specific operation(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_operation_disable(void)
+{
+ SDIO_DATACTL &= ~SDIO_DATACTL_IOEN;
+}
+
+/*!
+ \brief enable the SD I/O suspend operation(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_suspend_enable(void)
+{
+ SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND;
+}
+
+/*!
+ \brief disable the SD I/O suspend operation(SD I/O only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_suspend_disable(void)
+{
+ SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND;
+}
+
+/*!
+ \brief enable the CE-ATA command(CE-ATA only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_ceata_command_enable(void)
+{
+ SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN;
+}
+
+/*!
+ \brief disable the CE-ATA command(CE-ATA only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_ceata_command_disable(void)
+{
+ SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN;
+}
+
+/*!
+ \brief enable the CE-ATA interrupt(CE-ATA only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_ceata_interrupt_enable(void)
+{
+ SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN;
+}
+
+/*!
+ \brief disable the CE-ATA interrupt(CE-ATA only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_ceata_interrupt_disable(void)
+{
+ SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN;
+}
+
+/*!
+ \brief enable the CE-ATA command completion signal(CE-ATA only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_ceata_command_completion_enable(void)
+{
+ SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC;
+}
+
+/*!
+ \brief disable the CE-ATA command completion signal(CE-ATA only)
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void sdio_ceata_command_completion_disable(void)
+{
+ SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC;
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c
new file mode 100644
index 0000000..fbb63a6
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c
@@ -0,0 +1,687 @@
+/*!
+ \file gd32f10x_spi.c
+ \brief SPI driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_spi.h"
+
+/* SPI/I2S parameter initialization mask */
+#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */
+#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */
+
+/* I2S clock source selection, multiplication and division mask */
+#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */
+#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */
+#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */
+#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */
+
+/* reset value and offset */
+#define SPI_I2SPSC_RESET ((uint32_t)0x00000002U) /*!< I2S clock prescaler register reset value */
+#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */
+#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */
+
+/*!
+ \brief reset SPI and I2S
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_i2s_deinit(uint32_t spi_periph)
+{
+ switch(spi_periph) {
+ case SPI0:
+ /* reset SPI0 */
+ rcu_periph_reset_enable(RCU_SPI0RST);
+ rcu_periph_reset_disable(RCU_SPI0RST);
+ break;
+ case SPI1:
+ /* reset SPI1 and I2S1 */
+ rcu_periph_reset_enable(RCU_SPI1RST);
+ rcu_periph_reset_disable(RCU_SPI1RST);
+ break;
+ case SPI2:
+ /* reset SPI2 and I2S2 */
+ rcu_periph_reset_enable(RCU_SPI2RST);
+ rcu_periph_reset_disable(RCU_SPI2RST);
+ break;
+ default :
+ break;
+ }
+}
+
+/*!
+ \brief initialize the parameters of SPI structure with the default values
+ \param[in] none
+ \param[out] spi_parameter_struct: the initialized structure spi_parameter_struct pointer
+ \retval none
+*/
+void spi_struct_para_init(spi_parameter_struct *spi_struct)
+{
+ /* configure the SPI structure with the default values */
+ spi_struct->device_mode = SPI_SLAVE;
+ spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
+ spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
+ spi_struct->nss = SPI_NSS_HARD;
+ spi_struct->endian = SPI_ENDIAN_MSB;
+ spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
+ spi_struct->prescale = SPI_PSC_2;
+}
+
+/*!
+ \brief initialize SPI parameters
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] spi_struct: SPI parameter initialization stuct members of the structure
+ and the member values are shown as below:
+ device_mode: SPI_MASTER, SPI_SLAVE
+ trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
+ SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
+ frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
+ nss: SPI_NSS_SOFT, SPI_NSS_HARD
+ endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
+ clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
+ SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
+ prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
+ \param[out] none
+ \retval none
+*/
+void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct)
+{
+ uint32_t reg = 0U;
+ reg = SPI_CTL0(spi_periph);
+ reg &= SPI_INIT_MASK;
+
+ /* select SPI as master or slave */
+ reg |= spi_struct->device_mode;
+ /* select SPI transfer mode */
+ reg |= spi_struct->trans_mode;
+ /* select SPI frame size */
+ reg |= spi_struct->frame_size;
+ /* select SPI NSS use hardware or software */
+ reg |= spi_struct->nss;
+ /* select SPI LSB or MSB */
+ reg |= spi_struct->endian;
+ /* select SPI polarity and phase */
+ reg |= spi_struct->clock_polarity_phase;
+ /* select SPI prescale to adjust transmit speed */
+ reg |= spi_struct->prescale;
+
+ /* write to SPI_CTL0 register */
+ SPI_CTL0(spi_periph) = (uint32_t)reg;
+
+ /* select SPI mode */
+ SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
+}
+
+/*!
+ \brief enable SPI
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_enable(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
+}
+
+/*!
+ \brief disable SPI
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_disable(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
+}
+
+/*!
+ \brief initialize I2S parameter
+ \param[in] spi_periph: SPIx(x=1,2)
+ \param[in] mode: I2S operation mode
+ only one parameter can be selected which is shown as below:
+ \arg I2S_MODE_SLAVETX: I2S slave transmit mode
+ \arg I2S_MODE_SLAVERX: I2S slave receive mode
+ \arg I2S_MODE_MASTERTX: I2S master transmit mode
+ \arg I2S_MODE_MASTERRX: I2S master receive mode
+ \param[in] standard: I2S standard
+ only one parameter can be selected which is shown as below:
+ \arg I2S_STD_PHILLIPS: I2S phillips standard
+ \arg I2S_STD_MSB: I2S MSB standard
+ \arg I2S_STD_LSB: I2S LSB standard
+ \arg I2S_STD_PCMSHORT: I2S PCM short standard
+ \arg I2S_STD_PCMLONG: I2S PCM long standard
+ \param[in] ckpl: I2S idle state clock polarity
+ only one parameter can be selected which is shown as below:
+ \arg I2S_CKPL_LOW: I2S clock polarity low level
+ \arg I2S_CKPL_HIGH: I2S clock polarity high level
+ \param[out] none
+ \retval none
+*/
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
+{
+ uint32_t reg = 0U;
+ reg = SPI_I2SCTL(spi_periph);
+ reg &= I2S_INIT_MASK;
+
+ /* enable I2S mode */
+ reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
+ /* select I2S mode */
+ reg |= (uint32_t)mode;
+ /* select I2S standard */
+ reg |= (uint32_t)standard;
+ /* select I2S polarity */
+ reg |= (uint32_t)ckpl;
+
+ /* write to SPI_I2SCTL register */
+ SPI_I2SCTL(spi_periph) = (uint32_t)reg;
+}
+
+/*!
+ \brief configure I2S prescaler
+ \param[in] spi_periph: SPIx(x=1,2)
+ \param[in] audiosample: I2S audio sample rate
+ only one parameter can be selected which is shown as below:
+ \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
+ \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
+ \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
+ \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
+ \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
+ \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
+ \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
+ \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
+ \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
+ \param[in] frameformat: I2S data length and channel length
+ only one parameter can be selected which is shown as below:
+ \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
+ \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
+ \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
+ \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
+ \param[in] mckout: I2S master clock output
+ only one parameter can be selected which is shown as below:
+ \arg I2S_MCKOUT_ENABLE: enable I2S master clock output
+ \arg I2S_MCKOUT_DISABLE: disable 2S master clock output
+ \param[out] none
+ \retval none
+*/
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
+{
+ uint32_t i2sdiv = 2U, i2sof = 0U;
+ uint32_t clks = 0U;
+ uint32_t i2sclock = 0U;
+
+ /* deinitialize SPI_I2SPSC register */
+ SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET;
+
+#ifdef GD32F10X_CL
+ /* get the I2S clock source */
+ if(SPI1 == ((uint32_t)spi_periph)) {
+ /* I2S1 clock source selection */
+ clks = I2S1_CLOCK_SEL;
+ } else {
+ /* I2S2 clock source selection */
+ clks = I2S2_CLOCK_SEL;
+ }
+
+ if(0U != (RCU_CFG1 & clks)) {
+ /* get RCU PLL2 clock multiplication factor */
+ clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET);
+
+ if((clks > 5U) && (clks < 15U)) {
+ /* multiplier is between 8 and 14 */
+ clks += 2U;
+ } else {
+ if(15U == clks) {
+ /* multiplier is 20 */
+ clks = 20U;
+ }
+ }
+
+ /* get the PREDV1 value */
+ i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U);
+ /* calculate I2S clock based on PLL2 and PREDV1 */
+ i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
+ } else {
+ /* get system clock */
+ i2sclock = rcu_clock_freq_get(CK_SYS);
+ }
+#else
+ /* get system clock */
+ i2sclock = rcu_clock_freq_get(CK_SYS);
+#endif /* GD32F10X_CL */
+
+ /* configure the prescaler depending on the mclk output state, the frame format and audio sample rate */
+ if(I2S_MCKOUT_ENABLE == mckout) {
+ clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
+ } else {
+ if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) {
+ clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample);
+ } else {
+ clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample);
+ }
+ }
+
+ /* remove the floating point */
+ clks = (clks + 5U) / 10U;
+ i2sof = (clks & 0x00000001U);
+ i2sdiv = ((clks - i2sof) / 2U);
+ i2sof = (i2sof << 8U);
+
+ /* set the default values */
+ if((i2sdiv < 2U) || (i2sdiv > 255U)) {
+ i2sdiv = 2U;
+ i2sof = 0U;
+ }
+
+ /* configure SPI_I2SPSC */
+ SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
+
+ /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
+ SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
+ /* configure data frame format */
+ SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
+}
+
+/*!
+ \brief enable I2S
+ \param[in] spi_periph: SPIx(x=1,2)
+ \param[out] none
+ \retval none
+*/
+void i2s_enable(uint32_t spi_periph)
+{
+ SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
+}
+
+/*!
+ \brief disable I2S
+ \param[in] spi_periph: SPIx(x=1,2)
+ \param[out] none
+ \retval none
+*/
+void i2s_disable(uint32_t spi_periph)
+{
+ SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
+}
+
+/*!
+ \brief enable SPI NSS output
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_nss_output_enable(uint32_t spi_periph)
+{
+ SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
+}
+
+/*!
+ \brief disable SPI NSS output
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_nss_output_disable(uint32_t spi_periph)
+{
+ SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
+}
+
+/*!
+ \brief SPI NSS pin high level in software mode
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_nss_internal_high(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
+}
+
+/*!
+ \brief SPI NSS pin low level in software mode
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_nss_internal_low(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
+}
+
+/*!
+ \brief enable SPI DMA send or receive
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] dma: SPI DMA mode
+ only one parameter can be selected which is shown as below:
+ \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA
+ \arg SPI_DMA_RECEIVE: SPI receive data using DMA
+ \param[out] none
+ \retval none
+*/
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
+{
+ if(SPI_DMA_TRANSMIT == dma) {
+ SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
+ } else {
+ SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
+ }
+}
+
+/*!
+ \brief disable SPI DMA send or receive
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] dma: SPI DMA mode
+ only one parameter can be selected which is shown as below:
+ \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA
+ \arg SPI_DMA_RECEIVE: SPI receive data using DMA
+ \param[out] none
+ \retval none
+*/
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
+{
+ if(SPI_DMA_TRANSMIT == dma) {
+ SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
+ } else {
+ SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
+ }
+}
+
+/*!
+ \brief configure SPI data frame format
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] frame_format: SPI frame size
+ only one parameter can be selected which is shown as below:
+ \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
+ \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
+ \param[out] none
+ \retval none
+*/
+void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
+{
+ /* clear SPI_CTL0_FF16 bit */
+ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
+ /* configure SPI_CTL0_FF16 bit */
+ SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
+}
+
+/*!
+ \brief configure SPI bidirectional transfer direction
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] transfer_direction: SPI transfer direction
+ only one parameter can be selected which is shown as below:
+ \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
+ \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
+ \param[out] none
+ \retval none
+*/
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
+{
+ if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) {
+ /* set the transmit only mode */
+ SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
+ } else {
+ /* set the receive only mode */
+ SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
+ }
+}
+
+/*!
+ \brief SPI transmit data
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] data: 16-bit data
+ \param[out] none
+ \retval none
+*/
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
+{
+ SPI_DATA(spi_periph) = (uint32_t)data;
+}
+
+/*!
+ \brief SPI receive data
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval 16-bit data
+*/
+uint16_t spi_i2s_data_receive(uint32_t spi_periph)
+{
+ return ((uint16_t)SPI_DATA(spi_periph));
+}
+
+/*!
+ \brief set SPI CRC polynomial
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] crc_poly: CRC polynomial value
+ \param[out] none
+ \retval none
+*/
+void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
+{
+ /* enable SPI CRC */
+ SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
+ /* set SPI CRC polynomial */
+ SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
+}
+
+/*!
+ \brief get SPI CRC polynomial
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval 16-bit CRC polynomial
+*/
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
+{
+ return ((uint16_t)SPI_CRCPOLY(spi_periph));
+}
+
+/*!
+ \brief turn on SPI CRC function
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_crc_on(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
+}
+
+/*!
+ \brief turn off SPI CRC function
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_crc_off(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
+}
+
+/*!
+ \brief SPI next data is CRC value
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_crc_next(uint32_t spi_periph)
+{
+ SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
+}
+
+/*!
+ \brief get SPI CRC send value or receive value
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] crc: SPI crc value
+ only one parameter can be selected which is shown as below:
+ \arg SPI_CRC_TX: get transmit crc value
+ \arg SPI_CRC_RX: get receive crc value
+ \param[out] none
+ \retval 16-bit CRC value
+*/
+uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
+{
+ if(SPI_CRC_TX == crc) {
+ return ((uint16_t)(SPI_TCRC(spi_periph)));
+ } else {
+ return ((uint16_t)(SPI_RCRC(spi_periph)));
+ }
+}
+
+/*!
+ \brief clear SPI CRC error flag status
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void spi_crc_error_clear(uint32_t spi_periph)
+{
+ SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR);
+}
+
+/*!
+ \brief get SPI and I2S flag status
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] flag: SPI/I2S flag status
+ one or more parameters can be selected which are shown as below:
+ \arg SPI_FLAG_TBE: transmit buffer empty flag
+ \arg SPI_FLAG_RBNE: receive buffer not empty flag
+ \arg SPI_FLAG_TRANS: transmit on-going flag
+ \arg SPI_FLAG_RXORERR: receive overrun error flag
+ \arg SPI_FLAG_CONFERR: mode config error flag
+ \arg SPI_FLAG_CRCERR: CRC error flag
+ \arg I2S_FLAG_RXORERR: overrun error flag
+ \arg I2S_FLAG_TXURERR: underrun error flag
+ \arg I2S_FLAG_CH: channel side flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
+{
+ if(RESET != (SPI_STAT(spi_periph) & flag)) {
+ return SET;
+ } else {
+ return RESET;
+ }
+}
+
+/*!
+ \brief enable SPI and I2S interrupt
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] interrupt: SPI/I2S interrupt
+ only one parameter can be selected which is shown as below:
+ \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
+ \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
+ \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error,
+ transmission underrun error and format error interrupt
+ \param[out] none
+ \retval none
+*/
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
+{
+ SPI_CTL1(spi_periph) |= (uint32_t)interrupt;
+}
+
+/*!
+ \brief disable SPI and I2S interrupt
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] interrupt: SPI/I2S interrupt
+ only one parameter can be selected which is shown as below:
+ \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
+ \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
+ \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error,
+ transmission underrun error and format error interrupt
+ \param[out] none
+ \retval none
+*/
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
+{
+ SPI_CTL1(spi_periph) &= ~(uint32_t)interrupt;
+}
+
+/*!
+ \brief get SPI and I2S interrupt flag status
+ \param[in] spi_periph: SPIx(x=0,1,2)
+ \param[in] interrupt: SPI/I2S interrupt flag status
+ only one parameter can be selected which is shown as below:
+ \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
+ \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
+ \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
+ \arg SPI_INT_FLAG_CONFERR: config error interrupt flag
+ \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag
+ \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
+{
+ uint32_t reg1 = SPI_STAT(spi_periph);
+ uint32_t reg2 = SPI_CTL1(spi_periph);
+
+ switch(interrupt) {
+ /* SPI/I2S transmit buffer empty interrupt */
+ case SPI_I2S_INT_FLAG_TBE:
+ reg1 = reg1 & SPI_STAT_TBE;
+ reg2 = reg2 & SPI_CTL1_TBEIE;
+ break;
+ /* SPI/I2S receive buffer not empty interrupt */
+ case SPI_I2S_INT_FLAG_RBNE:
+ reg1 = reg1 & SPI_STAT_RBNE;
+ reg2 = reg2 & SPI_CTL1_RBNEIE;
+ break;
+ /* SPI/I2S overrun interrupt */
+ case SPI_I2S_INT_FLAG_RXORERR:
+ reg1 = reg1 & SPI_STAT_RXORERR;
+ reg2 = reg2 & SPI_CTL1_ERRIE;
+ break;
+ /* SPI config error interrupt */
+ case SPI_INT_FLAG_CONFERR:
+ reg1 = reg1 & SPI_STAT_CONFERR;
+ reg2 = reg2 & SPI_CTL1_ERRIE;
+ break;
+ /* SPI CRC error interrupt */
+ case SPI_INT_FLAG_CRCERR:
+ reg1 = reg1 & SPI_STAT_CRCERR;
+ reg2 = reg2 & SPI_CTL1_ERRIE;
+ break;
+ /* I2S underrun error interrupt */
+ case I2S_INT_FLAG_TXURERR:
+ reg1 = reg1 & SPI_STAT_TXURERR;
+ reg2 = reg2 & SPI_CTL1_ERRIE;
+ break;
+ default :
+ break;
+ }
+ /*get SPI/I2S interrupt flag status */
+ if((0U != reg1) && (0U != reg2)) {
+ return SET;
+ } else {
+ return RESET;
+ }
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c
new file mode 100644
index 0000000..6456a6a
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c
@@ -0,0 +1,1999 @@
+/*!
+ \file gd32f10x_timer.c
+ \brief TIMER driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_timer.h"
+
+/* TIMER init parameter mask */
+#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */
+#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */
+#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */
+
+/*!
+ \brief deinit a TIMER
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_deinit(uint32_t timer_periph)
+{
+ switch(timer_periph){
+ case TIMER0:
+ /* reset TIMER0 */
+ rcu_periph_reset_enable(RCU_TIMER0RST);
+ rcu_periph_reset_disable(RCU_TIMER0RST);
+ break;
+ case TIMER1:
+ /* reset TIMER1 */
+ rcu_periph_reset_enable(RCU_TIMER1RST);
+ rcu_periph_reset_disable(RCU_TIMER1RST);
+ break;
+ case TIMER2:
+ /* reset TIMER2 */
+ rcu_periph_reset_enable(RCU_TIMER2RST);
+ rcu_periph_reset_disable(RCU_TIMER2RST);
+ break;
+ case TIMER3:
+ /* reset TIMER3 */
+ rcu_periph_reset_enable(RCU_TIMER3RST);
+ rcu_periph_reset_disable(RCU_TIMER3RST);
+ break;
+ case TIMER4:
+ /* reset TIMER4 */
+ rcu_periph_reset_enable(RCU_TIMER4RST);
+ rcu_periph_reset_disable(RCU_TIMER4RST);
+ break;
+ case TIMER5:
+ /* reset TIMER5 */
+ rcu_periph_reset_enable(RCU_TIMER5RST);
+ rcu_periph_reset_disable(RCU_TIMER5RST);
+ break;
+ case TIMER6:
+ /* reset TIMER6 */
+ rcu_periph_reset_enable(RCU_TIMER6RST);
+ rcu_periph_reset_disable(RCU_TIMER6RST);
+ break;
+ case TIMER7:
+ /* reset TIMER7 */
+ rcu_periph_reset_enable(RCU_TIMER7RST);
+ rcu_periph_reset_disable(RCU_TIMER7RST);
+ break;
+#ifdef GD32F10X_XD
+ case TIMER8:
+ /* reset TIMER8 */
+ rcu_periph_reset_enable(RCU_TIMER8RST);
+ rcu_periph_reset_disable(RCU_TIMER8RST);
+ break;
+ case TIMER9:
+ /* reset TIMER9 */
+ rcu_periph_reset_enable(RCU_TIMER9RST);
+ rcu_periph_reset_disable(RCU_TIMER9RST);
+ break;
+ case TIMER10:
+ /* reset TIMER10 */
+ rcu_periph_reset_enable(RCU_TIMER10RST);
+ rcu_periph_reset_disable(RCU_TIMER10RST);
+ break;
+ case TIMER11:
+ /* reset TIMER11 */
+ rcu_periph_reset_enable(RCU_TIMER11RST);
+ rcu_periph_reset_disable(RCU_TIMER11RST);
+ break;
+ case TIMER12:
+ /* reset TIMER12 */
+ rcu_periph_reset_enable(RCU_TIMER12RST);
+ rcu_periph_reset_disable(RCU_TIMER12RST);
+ break;
+ case TIMER13:
+ /* reset TIMER13 */
+ rcu_periph_reset_enable(RCU_TIMER13RST);
+ rcu_periph_reset_disable(RCU_TIMER13RST);
+ break;
+#endif /* GD32F10X_XD */
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief initialize TIMER init parameter struct with a default value
+ \param[in] initpara: init parameter struct
+ \param[out] none
+ \retval none
+*/
+void timer_struct_para_init(timer_parameter_struct* initpara)
+{
+ /* initialize the init parameter struct member with the default value */
+ initpara->prescaler = 0U;
+ initpara->alignedmode = TIMER_COUNTER_EDGE;
+ initpara->counterdirection = TIMER_COUNTER_UP;
+ initpara->period = 65535U;
+ initpara->clockdivision = TIMER_CKDIV_DIV1;
+ initpara->repetitioncounter = 0U;
+}
+
+/*!
+ \brief initialize TIMER counter
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[in] initpara: init parameter struct
+ prescaler: prescaler value of the counter clock,0~65535
+ alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,
+ TIMER_COUNTER_CENTER_BOTH
+ counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN
+ period: counter auto reload value,0~65535
+ clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4
+ repetitioncounter: counter repetition value,0~255
+ \param[out] none
+ \retval none
+*/
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
+{
+ /* configure the counter prescaler value */
+ TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
+
+ /* configure the counter direction and aligned mode */
+ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) ||
+ (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) ||
+ (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){
+ TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
+ TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
+ TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
+ }
+
+ /* configure the autoreload value */
+ TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
+
+ if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
+ /* reset the CKDIV bit */
+ TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
+ TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
+ }
+
+ if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
+ /* configure the repetition counter value */
+ TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
+ }
+
+ /* generate an update event */
+ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+}
+
+/*!
+ \brief enable a TIMER
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_enable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
+}
+
+/*!
+ \brief disable a TIMER
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_disable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
+}
+
+/*!
+ \brief enable the auto reload shadow function
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_auto_reload_shadow_enable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
+}
+
+/*!
+ \brief disable the auto reload shadow function
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_auto_reload_shadow_disable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
+}
+
+/*!
+ \brief enable the update event
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_update_event_enable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
+}
+
+/*!
+ \brief disable the update event
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval none
+*/
+void timer_update_event_disable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
+}
+
+/*!
+ \brief set TIMER counter alignment mode
+ \param[in] timer_periph: TIMERx(x=0..4,7..13)
+ \param[in] aligned:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_COUNTER_EDGE: edge-aligned mode
+ \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
+ \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
+ \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
+ \param[out] none
+ \retval none
+*/
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
+{
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
+ TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
+}
+
+/*!
+ \brief set TIMER counter up direction
+ \param[in] timer_periph: TIMERx(x=0..4,7..13)
+ \param[out] none
+ \retval none
+*/
+void timer_counter_up_direction(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
+}
+
+/*!
+ \brief set TIMER counter down direction
+ \param[in] timer_periph: TIMERx(x=0..4,7..13)
+ \param[out] none
+ \retval none
+*/
+void timer_counter_down_direction(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
+}
+
+/*!
+ \brief configure TIMER prescaler
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[in] prescaler: prescaler value
+ \param[in] pscreload: prescaler reload mode
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
+ \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
+ \param[out] none
+ \retval none
+*/
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
+{
+ TIMER_PSC(timer_periph) = (uint32_t)prescaler;
+
+ if(TIMER_PSC_RELOAD_NOW == pscreload){
+ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+ }
+}
+
+/*!
+ \brief configure TIMER repetition register value
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[in] repetition: the counter repetition value,0~255
+ \param[out] none
+ \retval none
+*/
+void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition)
+{
+ TIMER_CREP(timer_periph) = (uint32_t)repetition;
+}
+
+/*!
+ \brief configure TIMER autoreload register value
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[in] autoreload: the counter auto-reload value
+ \param[out] none
+ \retval none
+*/
+void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
+{
+ TIMER_CAR(timer_periph) = (uint32_t)autoreload;
+}
+
+/*!
+ \brief configure TIMER counter register value
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[in] counter: the counter value
+ \param[out] none
+ \retval none
+*/
+void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
+{
+ TIMER_CNT(timer_periph) = (uint32_t)counter;
+}
+
+/*!
+ \brief read TIMER counter value
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval counter value
+*/
+uint32_t timer_counter_read(uint32_t timer_periph)
+{
+ uint32_t count_value = 0U;
+ count_value = TIMER_CNT(timer_periph);
+ return (count_value);
+}
+
+/*!
+ \brief read TIMER prescaler value
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[out] none
+ \retval prescaler register value
+*/
+uint16_t timer_prescaler_read(uint32_t timer_periph)
+{
+ uint16_t prescaler_value = 0U;
+ prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
+ return (prescaler_value);
+}
+
+/*!
+ \brief configure TIMER single pulse mode
+ \param[in] timer_periph: TIMERx(x=0..8,11)
+ \param[in] spmode:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_SP_MODE_SINGLE: single pulse mode
+ \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
+ \param[out] none
+ \retval none
+*/
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
+{
+ if(TIMER_SP_MODE_SINGLE == spmode){
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
+ }else if(TIMER_SP_MODE_REPETITIVE == spmode){
+ TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure TIMER update source
+ \param[in] timer_periph: TIMERx(x=0..13)
+ \param[in] update:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,
+ or the slave mode controller trigger
+ \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
+ \param[out] none
+ \retval none
+*/
+void timer_update_source_config(uint32_t timer_periph, uint32_t update)
+{
+ if(TIMER_UPDATE_SRC_REGULAR == update){
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
+ }else if(TIMER_UPDATE_SRC_GLOBAL == update){
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief enable the TIMER DMA
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] dma: timer DMA source enable
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7)
+ \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7)
+ \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7)
+ \param[out] none
+ \retval none
+*/
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
+{
+ TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
+}
+
+/*!
+ \brief disable the TIMER DMA
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] dma: timer DMA source disable
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_DMA_UPD: update DMA disable,TIMERx(x=0..7)
+ \arg TIMER_DMA_CH0D: channel 0 DMA disable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CH1D: channel 1 DMA disable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CH2D: channel 2 DMA disable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CH3D: channel 3 DMA disable,TIMERx(x=0..4,7)
+ \arg TIMER_DMA_CMTD: commutation DMA request disable,TIMERx(x=0,7)
+ \arg TIMER_DMA_TRGD: trigger DMA disable,TIMERx(x=0..4,7)
+ \param[out] none
+ \retval none
+*/
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
+{
+ TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
+}
+
+/*!
+ \brief channel DMA request source selection
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[in] dma_request: channel DMA request source selection
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
+ \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
+ \param[out] none
+ \retval none
+*/
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
+{
+ if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
+ }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
+ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure the TIMER DMA transfer
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] dma_baseaddr:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7)
+ \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7)
+ \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7)
+ \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7)
+ \param[in] dma_lenth:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
+ \param[out] none
+ \retval none
+*/
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
+{
+ TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
+ TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
+}
+
+/*!
+ \brief software generate events
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] event: the timer software event generation sources
+ one or more parameters can be selected which are shown as below:
+ \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13)
+ \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13)
+ \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11)
+ \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7)
+ \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7)
+ \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7)
+ \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11)
+ \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
+{
+ TIMER_SWEVG(timer_periph) |= (uint32_t)event;
+}
+
+/*!
+ \brief initialize TIMER break parameter struct with a default value
+ \param[in] breakpara: TIMER break parameter struct
+ \param[out] none
+ \retval none
+*/
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
+{
+ /* initialize the break parameter struct member with the default value */
+ breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
+ breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
+ breakpara->deadtime = 0U;
+ breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW;
+ breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
+ breakpara->protectmode = TIMER_CCHP_PROT_OFF;
+ breakpara->breakstate = TIMER_BREAK_DISABLE;
+}
+
+/*!
+ \brief configure TIMER break function
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[in] breakpara: TIMER break parameter struct
+ runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
+ ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
+ deadtime: 0~255
+ breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
+ outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
+ protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
+ breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
+ \param[out] none
+ \retval none
+*/
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
+{
+ TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
+ ((uint32_t)(breakpara->ideloffstate)) |
+ ((uint32_t)(breakpara->deadtime)) |
+ ((uint32_t)(breakpara->breakpolarity)) |
+ ((uint32_t)(breakpara->outputautostate)) |
+ ((uint32_t)(breakpara->protectmode)) |
+ ((uint32_t)(breakpara->breakstate))) ;
+}
+
+/*!
+ \brief enable TIMER break function
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_break_enable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
+}
+
+/*!
+ \brief disable TIMER break function
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_break_disable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
+}
+
+/*!
+ \brief enable TIMER output automatic function
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_automatic_output_enable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
+}
+
+/*!
+ \brief disable TIMER output automatic function
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_automatic_output_disable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
+}
+
+/*!
+ \brief enable or disable TIMER primary output function
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+ if(ENABLE == newvalue){
+ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
+ }else{
+ TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
+ }
+}
+
+/*!
+ \brief enable or disable channel capture/compare control shadow register
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+ if(ENABLE == newvalue){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
+ }else{
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
+ }
+}
+
+/*!
+ \brief configure TIMER channel control shadow register update control
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[in] ccuctl: channel control shadow register update control
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
+ \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
+ \param[out] none
+ \retval none
+*/
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
+{
+ if(TIMER_UPDATECTL_CCU == ccuctl){
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
+ }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief initialize TIMER channel output parameter struct with a default value
+ \param[in] ocpara: TIMER channel n output parameter struct
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
+{
+ /* initialize the channel output parameter struct member with the default value */
+ ocpara->outputstate = TIMER_CCX_DISABLE;
+ ocpara->outputnstate = TIMER_CCXN_DISABLE;
+ ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
+ ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
+ ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
+ ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
+}
+
+/*!
+ \brief configure TIMER channel output function
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7))
+ \param[in] ocpara: TIMER channeln output parameter struct
+ outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
+ outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
+ ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
+ ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
+ ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
+ ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+ TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
+ /* reset the CH0P bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
+ /* set the CH0P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
+
+ if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
+ /* reset the CH0NEN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
+ /* set the CH0NEN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
+ /* reset the CH0NP bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
+ /* set the CH0NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
+ /* reset the ISO0 bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
+ /* set the ISO0 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
+ /* reset the ISO0N bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
+ /* set the ISO0N bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
+ }
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+ TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U);
+ /* reset the CH1P bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
+ /* set the CH1P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U);
+
+ if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
+ /* reset the CH1NEN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
+ /* set the CH1NEN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U);
+ /* reset the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
+ /* set the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U);
+ /* reset the ISO1 bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
+ /* set the ISO1 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U);
+ /* reset the ISO1N bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
+ /* set the ISO1N bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U);
+ }
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ /* reset the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+ TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
+ /* set the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U);
+ /* reset the CH2P bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
+ /* set the CH2P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U);
+
+ if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
+ /* reset the CH2NEN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
+ /* set the CH2NEN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U);
+ /* reset the CH2NP bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
+ /* set the CH2NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U);
+ /* reset the ISO2 bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
+ /* set the ISO2 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U);
+ /* reset the ISO2N bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
+ /* set the ISO2N bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U);
+ }
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ /* reset the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
+ TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
+ /* set the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
+ /* reset the CH3P bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
+ /* set the CH3P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U);
+
+ if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){
+ /* reset the ISO3 bit */
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
+ /* set the ISO3 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output compare mode
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] ocmode: channel output compare mode
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_OC_MODE_TIMING: timing mode
+ \arg TIMER_OC_MODE_ACTIVE: active mode
+ \arg TIMER_OC_MODE_INACTIVE: inactive mode
+ \arg TIMER_OC_MODE_TOGGLE: toggle mode
+ \arg TIMER_OC_MODE_LOW: force low mode
+ \arg TIMER_OC_MODE_HIGH: force high mode
+ \arg TIMER_OC_MODE_PWM0: PWM0 mode
+ \arg TIMER_OC_MODE_PWM1: PWM1 mode
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output pulse value
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] pulse: channel output pulse value
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint16_t pulse)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output shadow function
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] ocshadow: channel output shadow state
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
+ \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output fast function
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] ocfast: channel output fast function
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
+ \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output clear function
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0
+ \arg TIMER_CH_1: TIMER channel1
+ \arg TIMER_CH_2: TIMER channel2
+ \arg TIMER_CH_3: TIMER channel3
+ \param[in] occlear: channel output clear function
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
+ \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output polarity
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] ocpolarity: channel output polarity
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
+ \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel complementary output polarity
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \param[in] ocnpolarity: channel complementary output polarity
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
+ \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
+ \param[out] none
+ \retval none
+*/
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel enable state
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] state: TIMER channel enable state
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CCX_ENABLE: channel enable
+ \arg TIMER_CCX_DISABLE: channel disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel complementary output enable state
+ \param[in] timer_periph: TIMERx(x=0,7)
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0
+ \arg TIMER_CH_1: TIMER channel1
+ \arg TIMER_CH_2: TIMER channel2
+ \param[in] ocnstate: TIMER channel complementary output enable state
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CCXN_ENABLE: channel complementary enable
+ \arg TIMER_CCXN_DISABLE: channel complementary disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief initialize TIMER channel input parameter struct with a default value
+ \param[in] icpara: TIMER channel intput parameter struct
+ \param[out] none
+ \retval none
+*/
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
+{
+ /* initialize the channel input parameter struct member with the default value */
+ icpara->icpolarity = TIMER_IC_POLARITY_RISING;
+ icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
+ icpara->icprescaler = TIMER_IC_PSC_DIV1;
+ icpara->icfilter = 0U;
+}
+
+/*!
+ \brief configure TIMER input capture parameter
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7))
+ \param[in] icpara: TIMER channel intput parameter struct
+ icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING
+ icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI,
+ TIMER_IC_SELECTION_ITS
+ icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4,
+ TIMER_IC_PSC_DIV8
+ icfilter: 0~15
+ \param[out] none
+ \retval none
+*/
+void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
+
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ break;
+
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+
+ /* reset the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
+
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ /* reset the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+
+ /* reset the CH2P and CH2NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
+
+ /* reset the CH2MS bit */
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
+
+ /* reset the CH2CAPFLT bit */
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
+
+ /* set the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ /* reset the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
+
+ /* reset the CH3P bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
+
+ /* reset the CH3MS bit */
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
+
+ /* reset the CH3CAPFLT bit */
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
+
+ /* set the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
+ break;
+ default:
+ break;
+ }
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler));
+}
+
+/*!
+ \brief configure TIMER channel input capture prescaler value
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[in] prescaler: channel input capture prescaler value
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_IC_PSC_DIV1: no prescaler
+ \arg TIMER_IC_PSC_DIV2: divided by 2
+ \arg TIMER_IC_PSC_DIV4: divided by 4
+ \arg TIMER_IC_PSC_DIV8: divided by 8
+ \param[out] none
+ \retval none
+*/
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
+ TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
+ TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief read TIMER channel capture compare register value
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
+ \param[out] none
+ \retval channel capture compare register value
+*/
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
+{
+ uint32_t count_value = 0U;
+
+ switch(channel){
+ case TIMER_CH_0:
+ /* read TIMER channel 0 capture compare register value */
+ count_value = TIMER_CH0CV(timer_periph);
+ break;
+ case TIMER_CH_1:
+ /* read TIMER channel 1 capture compare register value */
+ count_value = TIMER_CH1CV(timer_periph);
+ break;
+ case TIMER_CH_2:
+ /* read TIMER channel 2 capture compare register value */
+ count_value = TIMER_CH2CV(timer_periph);
+ break;
+ case TIMER_CH_3:
+ /* read TIMER channel 3 capture compare register value */
+ count_value = TIMER_CH3CV(timer_periph);
+ break;
+ default:
+ break;
+ }
+ return (count_value);
+}
+
+/*!
+ \brief configure TIMER input pwm capture function
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] channel:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_CH_0: TIMER channel0
+ \arg TIMER_CH_1: TIMER channel1
+ \param[in] icpwm:TIMER channel intput pwm parameter struct
+ icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
+ icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
+ icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
+ icfilter: 0~15
+ \param[out] none
+ \retval none
+*/
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
+{
+ uint16_t icpolarity = 0x0U;
+ uint16_t icselection = 0x0U;
+
+ /* Set channel input polarity */
+ if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
+ icpolarity = TIMER_IC_POLARITY_FALLING;
+ }else{
+ icpolarity = TIMER_IC_POLARITY_RISING;
+ }
+ /* Set channel input mode selection */
+ if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
+ icselection = TIMER_IC_SELECTION_INDIRECTTI;
+ }else{
+ icselection = TIMER_IC_SELECTION_DIRECTTI;
+ }
+
+ if(TIMER_CH_0 == channel){
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+ /* set the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+ /* set the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+ /* set the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
+
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+ /* reset the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ /* set the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+ /* set the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+ /* set the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
+ }else{
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+ /* reset the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ /* set the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+ /* set the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+ /* set the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
+
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ /* set the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+ /* set the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+ /* set the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
+ }
+}
+
+/*!
+ \brief configure TIMER hall sensor mode
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[in] hallmode:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
+ \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
+ \param[out] none
+ \retval none
+*/
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
+{
+ if(TIMER_HALLINTERFACE_ENABLE == hallmode){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
+ }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
+ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief select TIMER input trigger source
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] intrigger:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger,TIMERx(x=0..4,7)
+ \param[out] none
+ \retval none
+*/
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
+{
+ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
+}
+
+/*!
+ \brief select TIMER master mode output trigger source
+ \param[in] timer_periph: TIMERx(x=0..7)
+ \param[in] outrigger:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7))
+ \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7))
+ \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7))
+ \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4,7))
+ \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7))
+ \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7))
+ \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7))
+ \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7))
+ \param[out] none
+ \retval none
+*/
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
+{
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
+ TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
+}
+
+/*!
+ \brief select TIMER slave mode
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] slavemode:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
+ \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0
+ \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1
+ \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2
+ \arg TIMER_SLAVE_MODE_RESTART: restart mode
+ \arg TIMER_SLAVE_MODE_PAUSE: pause mode
+ \arg TIMER_SLAVE_MODE_EVENT: event mode
+ \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.
+ \param[out] none
+ \retval none
+*/
+
+void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
+{
+ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+
+ TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
+}
+
+/*!
+ \brief configure TIMER master slave mode
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] masterslave:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
+ \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
+ \param[out] none
+ \retval none
+*/
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
+{
+ if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
+ }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure TIMER external trigger input
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[in] extprescaler:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_EXT_TRI_PSC_OFF: no divided
+ \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
+ \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
+ \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
+ \param[in] expolarity:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_ETP_FALLING: active low or falling edge active
+ \arg TIMER_ETP_RISING: active high or rising edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter)
+{
+ TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
+ TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
+}
+
+/*!
+ \brief configure TIMER quadrature decoder mode
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] decomode:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
+ \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
+ \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
+ \param[in] ic0polarity:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_IC_POLARITY_RISING: capture rising edge
+ \arg TIMER_IC_POLARITY_FALLING: capture falling edge
+ \param[in] ic1polarity:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_IC_POLARITY_RISING: capture rising edge
+ \arg TIMER_IC_POLARITY_FALLING: capture falling edge
+ \param[out] none
+ \retval none
+*/
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
+{
+ /* configure the quadrature decoder mode */
+ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
+ /* configure input capture selection */
+ TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
+ /* configure channel input capture polarity */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+ TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
+}
+
+/*!
+ \brief configure TIMER internal clock mode
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[out] none
+ \retval none
+*/
+void timer_internal_clock_config(uint32_t timer_periph)
+{
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+}
+
+/*!
+ \brief configure TIMER the internal trigger as external clock input
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] intrigger:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
+ \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
+ \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
+ \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
+ \param[out] none
+ \retval none
+*/
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
+{
+ timer_input_trigger_source_select(timer_periph,intrigger);
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+ \brief configure TIMER the external trigger as external clock input
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] extrigger:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
+ \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
+ \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
+ \param[in] expolarity:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_IC_POLARITY_RISING: active high or rising edge active
+ \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint8_t extfilter)
+{
+ if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+ /* reset the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ /* set the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+ /* set the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+ /* set the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ }else{
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ /* set the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+ /* set the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ }
+ /* select TIMER input trigger source */
+ timer_input_trigger_source_select(timer_periph,extrigger);
+ /* reset the SMC bit */
+ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+ /* set the SMC bit */
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+ \brief configure TIMER the external clock mode0
+ \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
+ \param[in] extprescaler:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_EXT_TRI_PSC_OFF: no divided
+ \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
+ \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
+ \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
+ \param[in] expolarity:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_ETP_FALLING: active low or falling edge active
+ \arg TIMER_ETP_RISING: active high or rising edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter)
+{
+ /* configure TIMER external trigger input */
+ timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
+ /* reset the SMC bit,TRGS bit */
+ TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
+ /* set the SMC bit,TRGS bit */
+ TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
+}
+
+/*!
+ \brief configure TIMER the external clock mode1
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[in] extprescaler:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_EXT_TRI_PSC_OFF: no divided
+ \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
+ \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
+ \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
+ \param[in] extpolarity:
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_ETP_FALLING: active low or falling edge active
+ \arg TIMER_ETP_RISING: active high or rising edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter)
+{
+ /* configure TIMER external trigger input */
+ timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+ \brief disable TIMER the external clock mode1
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[out] none
+ \retval none
+*/
+void timer_external_clock_mode1_disable(uint32_t timer_periph)
+{
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+ \brief enable the TIMER interrupt
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] interrupt: timer interrupt enable source
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
+ \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
+ \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
+ \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
+ \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
+ \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
+ \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
+ \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
+{
+ TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
+}
+
+/*!
+ \brief disable the TIMER interrupt
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] interrupt: timer interrupt source disable
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..13)
+ \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..4,7..13)
+ \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..4,7,8,11)
+ \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..4,7)
+ \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..4,7)
+ \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,7)
+ \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..4,7,8,11)
+ \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
+{
+ TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
+}
+
+/*!
+ \brief get timer interrupt flag
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] interrupt: the timer interrupt bits
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
+ \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
+ \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
+ \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
+ \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
+ \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
+ \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
+{
+ uint32_t val;
+ val = (TIMER_DMAINTEN(timer_periph) & interrupt);
+ if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear TIMER interrupt flag
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] interrupt: the timer interrupt bits
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
+ \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
+ \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
+ \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
+ \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
+ \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
+ \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
+ \param[out] none
+ \retval none
+*/
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
+{
+ TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
+}
+
+/*!
+ \brief get TIMER flags
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] flag: the timer interrupt flags
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
+ \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
+ \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
+ \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
+ \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7)
+ \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
+ \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
+ \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
+ \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
+ \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
+{
+ if(RESET != (TIMER_INTF(timer_periph) & flag)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear TIMER flags
+ \param[in] timer_periph: please refer to the following parameters
+ \param[in] flag: the timer interrupt flags
+ only one parameter can be selected which is shown as below:
+ \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
+ \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
+ \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
+ \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
+ \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
+ \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
+ \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
+ \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
+ \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
+ \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
+ \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
+ \param[out] none
+ \retval none
+*/
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
+{
+ TIMER_INTF(timer_periph) = (~(uint32_t)flag);
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c
new file mode 100644
index 0000000..6b7621a
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c
@@ -0,0 +1,739 @@
+/*!
+ \file gd32f10x_usart.c
+ \brief USART driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_usart.h"
+
+/* USART register bit offset */
+#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */
+
+/*!
+ \brief reset USART/UART
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_deinit(uint32_t usart_periph)
+{
+ switch(usart_periph){
+ case USART0:
+ /* reset USART0 */
+ rcu_periph_reset_enable(RCU_USART0RST);
+ rcu_periph_reset_disable(RCU_USART0RST);
+ break;
+ case USART1:
+ /* reset USART1 */
+ rcu_periph_reset_enable(RCU_USART1RST);
+ rcu_periph_reset_disable(RCU_USART1RST);
+ break;
+ case USART2:
+ /* reset USART2 */
+ rcu_periph_reset_enable(RCU_USART2RST);
+ rcu_periph_reset_disable(RCU_USART2RST);
+ break;
+ case UART3:
+ /* reset UART3 */
+ rcu_periph_reset_enable(RCU_UART3RST);
+ rcu_periph_reset_disable(RCU_UART3RST);
+ break;
+ case UART4:
+ /* reset UART4 */
+ rcu_periph_reset_enable(RCU_UART4RST);
+ rcu_periph_reset_disable(RCU_UART4RST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure USART baud rate value
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] baudval: baud rate value
+ \param[out] none
+ \retval none
+*/
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
+{
+ uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U;
+ switch(usart_periph){
+ /* get clock frequency */
+ case USART0:
+ /* get USART0 clock */
+ uclk=rcu_clock_freq_get(CK_APB2);
+ break;
+ case USART1:
+ /* get USART1 clock */
+ uclk=rcu_clock_freq_get(CK_APB1);
+ break;
+ case USART2:
+ /* get USART2 clock */
+ uclk=rcu_clock_freq_get(CK_APB1);
+ break;
+ case UART3:
+ /* get UART3 clock */
+ uclk=rcu_clock_freq_get(CK_APB1);
+ break;
+ case UART4:
+ /* get UART4 clock */
+ uclk=rcu_clock_freq_get(CK_APB1);
+ break;
+ default:
+ break;
+ }
+ /* oversampling by 16, configure the value of USART_BAUD */
+ udiv = (uclk+baudval/2U)/baudval;
+ intdiv = udiv & (0x0000fff0U);
+ fradiv = udiv & (0x0000000fU);
+ USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
+}
+
+/*!
+ \brief configure USART parity
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] paritycfg: configure USART parity
+ only one parameter can be selected which is shown as below:
+ \arg USART_PM_NONE: no parity
+ \arg USART_PM_ODD: odd parity
+ \arg USART_PM_EVEN: even parity
+ \param[out] none
+ \retval none
+*/
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
+{
+ /* clear USART_CTL0 PM,PCEN bits */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
+ /* configure USART parity mode */
+ USART_CTL0(usart_periph) |= paritycfg ;
+}
+
+/*!
+ \brief configure USART word length
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] wlen: USART word length configure
+ only one parameter can be selected which is shown as below:
+ \arg USART_WL_8BIT: 8 bits
+ \arg USART_WL_9BIT: 9 bits
+ \param[out] none
+ \retval none
+*/
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
+{
+ /* clear USART_CTL0 WL bit */
+ USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
+ /* configure USART word length */
+ USART_CTL0(usart_periph) |= wlen;
+}
+
+/*!
+ \brief configure USART stop bit length
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] stblen: USART stop bit configure
+ only one parameter can be selected which is shown as below:
+ \arg USART_STB_1BIT: 1 bit
+ \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4)
+ \arg USART_STB_2BIT: 2 bits
+ \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
+{
+ /* clear USART_CTL1 STB bits */
+ USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
+ /* configure USART stop bits */
+ USART_CTL1(usart_periph) |= stblen;
+}
+/*!
+ \brief enable USART
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_enable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) |= USART_CTL0_UEN;
+}
+
+/*!
+ \brief disable USART
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_disable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+}
+
+/*!
+ \brief configure USART transmitter
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] txconfig: enable or disable USART transmitter
+ only one parameter can be selected which is shown as below:
+ \arg USART_TRANSMIT_ENABLE: enable USART transmission
+ \arg USART_TRANSMIT_DISABLE: disable USART transmission
+ \param[out] none
+ \retval none
+*/
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
+{
+ uint32_t ctl = 0U;
+
+ ctl = USART_CTL0(usart_periph);
+ ctl &= ~USART_CTL0_TEN;
+ ctl |= txconfig;
+ /* configure transfer mode */
+ USART_CTL0(usart_periph) = ctl;
+}
+
+/*!
+ \brief configure USART receiver
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] rxconfig: enable or disable USART receiver
+ only one parameter can be selected which is shown as below:
+ \arg USART_RECEIVE_ENABLE: enable USART reception
+ \arg USART_RECEIVE_DISABLE: disable USART reception
+ \param[out] none
+ \retval none
+*/
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
+{
+ uint32_t ctl = 0U;
+
+ ctl = USART_CTL0(usart_periph);
+ ctl &= ~USART_CTL0_REN;
+ ctl |= rxconfig;
+ /* configure receiver mode */
+ USART_CTL0(usart_periph) = ctl;
+}
+
+/*!
+ \brief USART transmit data function
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] data: data of transmission
+ \param[out] none
+ \retval none
+*/
+void usart_data_transmit(uint32_t usart_periph, uint16_t data)
+{
+ USART_DATA(usart_periph) = USART_DATA_DATA & (uint32_t)data;
+}
+
+/*!
+ \brief USART receive data function
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval data of received
+*/
+uint16_t usart_data_receive(uint32_t usart_periph)
+{
+ return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U));
+}
+
+/*!
+ \brief configure the address of the USART in wake up by address match mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] addr: address of USART/UART
+ \param[out] none
+ \retval none
+*/
+void usart_address_config(uint32_t usart_periph, uint8_t addr)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
+ USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (uint32_t)addr);
+}
+
+/*!
+ \brief receiver in mute mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_mute_mode_enable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) |= USART_CTL0_RWU;
+}
+
+/*!
+ \brief receiver in active mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_mute_mode_disable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU);
+}
+
+/*!
+ \brief configure wakeup method in mute mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] wmethod: two methods be used to enter or exit the mute mode
+ only one parameter can be selected which is shown as below:
+ \arg USART_WM_IDLE: idle line
+ \arg USART_WM_ADDR: address mask
+ \param[out] none
+ \retval none
+*/
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
+ USART_CTL0(usart_periph) |= wmethod;
+}
+
+/*!
+ \brief enable LIN mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_lin_mode_enable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
+}
+
+/*!
+ \brief disable LIN mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_lin_mode_disable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
+}
+
+/*!
+ \brief configure lin break frame length
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] lblen: lin break frame length
+ only one parameter can be selected which is shown as below:
+ \arg USART_LBLEN_10B: 10 bits
+ \arg USART_LBLEN_11B: 11 bits
+ \param[out] none
+ \retval none
+*/
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
+ USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen);
+}
+
+/*!
+ \brief send break frame
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_send_break(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD;
+}
+
+/*!
+ \brief enable half duplex mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_halfduplex_enable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
+}
+
+/*!
+ \brief disable half duplex mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_halfduplex_disable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
+}
+
+/*!
+ \brief enable CK pin in synchronous mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void usart_synchronous_clock_enable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
+}
+
+/*!
+ \brief disable CK pin in synchronous mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void usart_synchronous_clock_disable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
+}
+
+/*!
+ \brief configure USART synchronous mode parameters
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[in] clen: CK length
+ only one parameter can be selected which is shown as below:
+ \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame
+ \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame
+ \param[in] cph: clock phase
+ only one parameter can be selected which is shown as below:
+ \arg USART_CPH_1CK: first clock transition is the first data capture edge
+ \arg USART_CPH_2CK: second clock transition is the first data capture edge
+ \param[in] cpl: clock polarity
+ only one parameter can be selected which is shown as below:
+ \arg USART_CPL_LOW: steady low value on CK pin
+ \arg USART_CPL_HIGH: steady high value on CK pin
+ \param[out] none
+ \retval none
+*/
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
+ USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
+}
+
+/*!
+ \brief configure guard time value in smartcard mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[in] guat: guard time value
+ \param[out] none
+ \retval none
+*/
+void usart_guard_time_config(uint32_t usart_periph,uint8_t guat)
+{
+ USART_GP(usart_periph) &= ~(USART_GP_GUAT);
+ USART_GP(usart_periph) |= (USART_GP_GUAT & ((uint32_t)guat << GP_GUAT_OFFSET));
+}
+
+/*!
+ \brief enable smartcard mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_enable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
+}
+
+/*!
+ \brief disable smartcard mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_disable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
+}
+
+/*!
+ \brief enable NACK in smartcard mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
+}
+
+/*!
+ \brief disable NACK in smartcard mode
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
+}
+
+/*!
+ \brief enable IrDA mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_irda_mode_enable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) |= USART_CTL2_IREN;
+}
+
+/*!
+ \brief disable IrDA mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[out] none
+ \retval none
+*/
+void usart_irda_mode_disable(uint32_t usart_periph)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
+}
+
+/*!
+ \brief configure the peripheral clock prescaler in USART IrDA low-power mode
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] psc: 0x00-0xFF
+ \param[out] none
+ \retval none
+*/
+void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
+{
+ USART_GP(usart_periph) &= ~(USART_GP_PSC);
+ USART_GP(usart_periph) |= (uint32_t)psc;
+}
+
+/*!
+ \brief configure IrDA low-power
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] irlp: IrDA low-power or normal
+ only one parameter can be selected which is shown as below:
+ \arg USART_IRLP_LOW: low-power
+ \arg USART_IRLP_NORMAL: normal
+ \param[out] none
+ \retval none
+*/
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
+ USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
+}
+
+/*!
+ \brief configure hardware flow control RTS
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[in] rtsconfig: enable or disable RTS
+ only one parameter can be selected which is shown as below:
+ \arg USART_RTS_ENABLE: enable RTS
+ \arg USART_RTS_DISABLE: disable RTS
+ \param[out] none
+ \retval none
+*/
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
+ USART_CTL2(usart_periph) |= (USART_CTL2_RTSEN & rtsconfig);
+}
+
+/*!
+ \brief configure hardware flow control CTS
+ \param[in] usart_periph: USARTx(x=0,1,2)
+ \param[in] ctsconfig: enable or disable CTS
+ only one parameter can be selected which is shown as below:
+ \arg USART_CTS_ENABLE: enable CTS
+ \arg USART_CTS_DISABLE: disable CTS
+ \param[out] none
+ \retval none
+*/
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_CTSEN);
+ USART_CTL2(usart_periph) |= (USART_CTL2_CTSEN & ctsconfig);
+}
+
+/*!
+ \brief configure USART DMA reception
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3)
+ \param[in] dmacmd: enable or disable DMA for reception
+ only one parameter can be selected which is shown as below:
+ \arg USART_RECEIVE_DMA_ENABLE: enable USART DMA for reception
+ \arg USART_RECEIVE_DMA_DISABLE: disable USART DMA for reception
+ \param[out] none
+ \retval none
+*/
+void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_DENR);
+ USART_CTL2(usart_periph) |= (USART_CTL2_DENR & dmaconfig);
+}
+
+/*!
+ \brief configure USART DMA transmission
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3)
+ \param[in] dmacmd: enable or disable DMA for transmission
+ only one parameter can be selected which is shown as below:
+ \arg USART_TRANSMIT_DMA_ENABLE: enable USART DMA for transmission
+ \arg USART_TRANSMIT_DMA_DISABLE: disable USART DMA for transmission
+ \param[out] none
+ \retval none
+*/
+void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig)
+{
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_DENT);
+ USART_CTL2(usart_periph) |= (USART_CTL2_DENT & dmaconfig);
+}
+
+/*!
+ \brief get flag in STAT register
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] flag: USART flags, refer to usart_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg USART_FLAG_CTSF: CTS change flag
+ \arg USART_FLAG_LBDF: LIN break detected flag
+ \arg USART_FLAG_TBE: transmit data buffer empty
+ \arg USART_FLAG_TC: transmission complete
+ \arg USART_FLAG_RBNE: read data buffer not empty
+ \arg USART_FLAG_IDLEF: IDLE frame detected flag
+ \arg USART_FLAG_ORERR: overrun error
+ \arg USART_FLAG_NERR: noise error flag
+ \arg USART_FLAG_FERR: frame error flag
+ \arg USART_FLAG_PERR: parity error flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
+{
+ if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear flag in STAT register
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] flag: USART flags, refer to usart_flag_enum
+ only one parameter can be selected which is shown as below:
+ \arg USART_FLAG_CTSF: CTS change flag
+ \arg USART_FLAG_LBDF: LIN break detected flag
+ \arg USART_FLAG_TC: transmission complete
+ \arg USART_FLAG_RBNE: read data buffer not empty
+ \param[out] none
+ \retval none
+*/
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
+{
+ USART_REG_VAL(usart_periph, flag) = ~BIT(USART_BIT_POS(flag));
+}
+
+/*!
+ \brief enable USART interrupt
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] int_flag
+ only one parameter can be selected which is shown as below:
+ \arg USART_INT_PERR: parity error interrupt
+ \arg USART_INT_TBE: transmitter buffer empty interrupt
+ \arg USART_INT_TC: transmission complete interrupt
+ \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
+ \arg USART_INT_IDLE: IDLE line detected interrupt
+ \arg USART_INT_LBD: LIN break detected interrupt
+ \arg USART_INT_ERR: error interrupt
+ \arg USART_INT_CTS: CTS interrupt
+ \param[out] none
+ \retval none
+*/
+void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
+{
+ USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
+}
+
+/*!
+ \brief disable USART interrupt
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] int_flag
+ only one parameter can be selected which is shown as below:
+ \arg USART_INT_PERR: parity error interrupt
+ \arg USART_INT_TBE: transmitter buffer empty interrupt
+ \arg USART_INT_TC: transmission complete interrupt
+ \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
+ \arg USART_INT_IDLE: IDLE line detected interrupt
+ \arg USART_INT_LBD: LIN break detected interrupt
+ \arg USART_INT_ERR: error interrupt
+ \arg USART_INT_CTS: CTS interrupt
+ \param[out] none
+ \retval none
+*/
+void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
+{
+ USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
+}
+
+/*!
+ \brief get USART interrupt and flag status
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] int_flag
+ only one parameter can be selected which is shown as below:
+ \arg USART_INT_FLAG_PERR: parity error interrupt and flag
+ \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
+ \arg USART_INT_FLAG_TC: transmission complete interrupt and flag
+ \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
+ \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
+ \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
+ \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag
+ \arg USART_INT_FLAG_CTS: CTS interrupt and flag
+ \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
+ \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
+ \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
+{
+ uint32_t intenable = 0U, flagstatus = 0U;
+ /* get the interrupt enable bit status */
+ intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
+ /* get the corresponding flag bit status */
+ flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
+
+ if(flagstatus && intenable){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear USART interrupt flag in STAT register
+ \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+ \param[in] flag: USART interrupt flag
+ only one parameter can be selected which is shown as below:
+ \arg USART_INT_FLAG_CTS: CTS change flag
+ \arg USART_INT_FLAG_LBD: LIN break detected flag
+ \arg USART_INT_FLAG_TC: transmission complete
+ \arg USART_INT_FLAG_RBNE: read data buffer not empty
+ \param[out] none
+ \retval none
+*/
+void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
+{
+ USART_REG_VAL2(usart_periph, flag) = ~BIT(USART_BIT_POS2(flag));
+}
diff --git a/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c
new file mode 100644
index 0000000..54f8e40
--- /dev/null
+++ b/boot_source/platform/Chip_peripheral_dev/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c
@@ -0,0 +1,125 @@
+/*!
+ \file gd32f10x_wwdgt.c
+ \brief WWDGT driver
+
+ \version 2024-01-05, V2.3.0, firmware for GD32F10x
+*/
+
+/*
+ Copyright (c) 2024, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f10x_wwdgt.h"
+
+/*!
+ \brief reset the window watchdog timer configuration
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_WWDGTRST);
+ rcu_periph_reset_disable(RCU_WWDGTRST);
+}
+
+/*!
+ \brief start the window watchdog timer counter
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_enable(void)
+{
+ WWDGT_CTL |= WWDGT_CTL_WDGTEN;
+}
+
+/*!
+ \brief configure the window watchdog timer counter value
+ \param[in] counter_value: 0x00 - 0x7F
+ \param[out] none
+ \retval none
+*/
+void wwdgt_counter_update(uint16_t counter_value)
+{
+ WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value));
+}
+
+/*!
+ \brief configure counter value, window value, and prescaler divider value
+ \param[in] counter: 0x00 - 0x7F
+ \param[in] window: 0x00 - 0x7F
+ \param[in] prescaler: wwdgt prescaler value
+ only one parameter can be selected which is shown as below:
+ \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
+ \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
+ \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
+ \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
+ \param[out] none
+ \retval none
+*/
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
+{
+ WWDGT_CTL = (uint32_t)(CTL_CNT(counter));
+ WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler);
+}
+
+/*!
+ \brief check early wakeup interrupt state of WWDGT
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus wwdgt_flag_get(void)
+{
+ if(WWDGT_STAT & WWDGT_STAT_EWIF) {
+ return SET;
+ }
+
+ return RESET;
+}
+
+/*!
+ \brief clear early wakeup interrupt state of WWDGT
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_flag_clear(void)
+{
+ WWDGT_STAT = (uint32_t)(RESET);
+}
+
+/*!
+ \brief enable early wakeup interrupt of WWDGT
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_interrupt_enable(void)
+{
+ WWDGT_CFG |= WWDGT_CFG_EWIE;
+}
diff --git a/boot_source/platform/drivers/inc/24cxx.h b/boot_source/platform/drivers/inc/24cxx.h
index 0319258..02fb26a 100644
Binary files a/boot_source/platform/drivers/inc/24cxx.h and b/boot_source/platform/drivers/inc/24cxx.h differ
diff --git a/boot_source/platform/drivers/inc/bsp_i2c_gpio.h b/boot_source/platform/drivers/inc/bsp_i2c_gpio.h
index 0939659..aca7e99 100644
Binary files a/boot_source/platform/drivers/inc/bsp_i2c_gpio.h and b/boot_source/platform/drivers/inc/bsp_i2c_gpio.h differ
diff --git a/boot_source/platform/drivers/inc/can.h b/boot_source/platform/drivers/inc/can.h
index bd0397a..cb75f22 100644
Binary files a/boot_source/platform/drivers/inc/can.h and b/boot_source/platform/drivers/inc/can.h differ
diff --git a/boot_source/platform/drivers/inc/can2.h b/boot_source/platform/drivers/inc/can2.h
index a92fb72..f3d4ef0 100644
Binary files a/boot_source/platform/drivers/inc/can2.h and b/boot_source/platform/drivers/inc/can2.h differ
diff --git a/boot_source/platform/drivers/inc/ecual_flash.h b/boot_source/platform/drivers/inc/ecual_flash.h
index d209502..97f5bad 100644
Binary files a/boot_source/platform/drivers/inc/ecual_flash.h and b/boot_source/platform/drivers/inc/ecual_flash.h differ
diff --git a/boot_source/platform/drivers/inc/led.h b/boot_source/platform/drivers/inc/led.h
index dcfb8ca..df02d1f 100644
Binary files a/boot_source/platform/drivers/inc/led.h and b/boot_source/platform/drivers/inc/led.h differ
diff --git a/boot_source/platform/drivers/src/CAN2/can2.c b/boot_source/platform/drivers/src/CAN2/can2.c
index e03fb0d..d0fffdb 100644
Binary files a/boot_source/platform/drivers/src/CAN2/can2.c and b/boot_source/platform/drivers/src/CAN2/can2.c differ
diff --git a/boot_source/platform/drivers/src/EEROM/bsp_i2c_gpio.c b/boot_source/platform/drivers/src/EEROM/bsp_i2c_gpio.c
index 909307b..0242598 100644
Binary files a/boot_source/platform/drivers/src/EEROM/bsp_i2c_gpio.c and b/boot_source/platform/drivers/src/EEROM/bsp_i2c_gpio.c differ
diff --git a/boot_source/platform/drivers/src/LED/led.c b/boot_source/platform/drivers/src/LED/led.c
index 35ee323..51ea1d8 100644
Binary files a/boot_source/platform/drivers/src/LED/led.c and b/boot_source/platform/drivers/src/LED/led.c differ
diff --git a/boot_source/platform/drivers/src/flash/ecual_flash.c b/boot_source/platform/drivers/src/flash/ecual_flash.c
index b9b56b1..e69de29 100644
Binary files a/boot_source/platform/drivers/src/flash/ecual_flash.c and b/boot_source/platform/drivers/src/flash/ecual_flash.c differ